Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-video
[platform/kernel/u-boot.git] / drivers / watchdog / ast_wdt.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017 Google, Inc
4  */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <wdt.h>
10 #include <asm/io.h>
11 #include <asm/arch/wdt.h>
12
13 #define WDT_AST2500     2500
14 #define WDT_AST2400     2400
15
16 struct ast_wdt_priv {
17         struct ast_wdt *regs;
18 };
19
20 static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
21 {
22         struct ast_wdt_priv *priv = dev_get_priv(dev);
23         ulong driver_data = dev_get_driver_data(dev);
24         u32 reset_mode = ast_reset_mode_from_flags(flags);
25
26         clrsetbits_le32(&priv->regs->ctrl,
27                         WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT,
28                         reset_mode << WDT_CTRL_RESET_MODE_SHIFT);
29
30         if (driver_data >= WDT_AST2500 && reset_mode == WDT_CTRL_RESET_SOC)
31                 writel(ast_reset_mask_from_flags(flags),
32                        &priv->regs->reset_mask);
33
34         writel((u32) timeout, &priv->regs->counter_reload_val);
35         writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
36         /*
37          * Setting CLK1MHZ bit is just for compatibility with ast2400 part.
38          * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
39          * read-only
40          */
41         setbits_le32(&priv->regs->ctrl,
42                      WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
43
44         return 0;
45 }
46
47 static int ast_wdt_stop(struct udevice *dev)
48 {
49         struct ast_wdt_priv *priv = dev_get_priv(dev);
50
51         clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
52
53         writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask);
54         return 0;
55 }
56
57 static int ast_wdt_reset(struct udevice *dev)
58 {
59         struct ast_wdt_priv *priv = dev_get_priv(dev);
60
61         writel(WDT_COUNTER_RESTART_VAL, &priv->regs->counter_restart);
62
63         return 0;
64 }
65
66 static int ast_wdt_expire_now(struct udevice *dev, ulong flags)
67 {
68         struct ast_wdt_priv *priv = dev_get_priv(dev);
69         int ret;
70
71         ret = ast_wdt_start(dev, 1, flags);
72         if (ret)
73                 return ret;
74
75         while (readl(&priv->regs->ctrl) & WDT_CTRL_EN)
76                 ;
77
78         return ast_wdt_stop(dev);
79 }
80
81 static int ast_wdt_ofdata_to_platdata(struct udevice *dev)
82 {
83         struct ast_wdt_priv *priv = dev_get_priv(dev);
84
85         priv->regs = devfdt_get_addr_ptr(dev);
86         if (IS_ERR(priv->regs))
87                 return PTR_ERR(priv->regs);
88
89         return 0;
90 }
91
92 static const struct wdt_ops ast_wdt_ops = {
93         .start = ast_wdt_start,
94         .reset = ast_wdt_reset,
95         .stop = ast_wdt_stop,
96         .expire_now = ast_wdt_expire_now,
97 };
98
99 static const struct udevice_id ast_wdt_ids[] = {
100         { .compatible = "aspeed,wdt", .data = WDT_AST2500 },
101         { .compatible = "aspeed,ast2500-wdt", .data = WDT_AST2500 },
102         { .compatible = "aspeed,ast2400-wdt", .data = WDT_AST2400 },
103         {}
104 };
105
106 static int ast_wdt_probe(struct udevice *dev)
107 {
108         debug("%s() wdt%u\n", __func__, dev->seq);
109         ast_wdt_stop(dev);
110
111         return 0;
112 }
113
114 U_BOOT_DRIVER(ast_wdt) = {
115         .name = "ast_wdt",
116         .id = UCLASS_WDT,
117         .of_match = ast_wdt_ids,
118         .probe = ast_wdt_probe,
119         .priv_auto_alloc_size = sizeof(struct ast_wdt_priv),
120         .ofdata_to_platdata = ast_wdt_ofdata_to_platdata,
121         .ops = &ast_wdt_ops,
122 };