2 * drivers/w1/masters/omap_hdq.c
4 * Copyright (C) 2007,2012 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
18 #include <linux/sched.h>
19 #include <linux/pm_runtime.h>
24 #define MOD_NAME "OMAP_HDQ:"
26 #define OMAP_HDQ_REVISION 0x00
27 #define OMAP_HDQ_TX_DATA 0x04
28 #define OMAP_HDQ_RX_DATA 0x08
29 #define OMAP_HDQ_CTRL_STATUS 0x0c
30 #define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7)
31 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6)
32 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5)
33 #define OMAP_HDQ_CTRL_STATUS_GO BIT(4)
34 #define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3)
35 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2)
36 #define OMAP_HDQ_CTRL_STATUS_DIR BIT(1)
37 #define OMAP_HDQ_INT_STATUS 0x10
38 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2)
39 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1)
40 #define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0)
42 #define OMAP_HDQ_FLAG_CLEAR 0
43 #define OMAP_HDQ_FLAG_SET 1
44 #define OMAP_HDQ_TIMEOUT (HZ/5)
46 #define OMAP_HDQ_MAX_USER 4
48 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
51 module_param(w1_id, int, 0400);
52 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode");
56 void __iomem *hdq_base;
57 /* lock read/write/break operations */
58 struct mutex hdq_mutex;
59 /* interrupt status and a lock for it */
61 spinlock_t hdq_spinlock;
62 /* mode: 0-HDQ 1-W1 */
67 /* HDQ register I/O routines */
68 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
70 return __raw_readl(hdq_data->hdq_base + offset);
73 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
75 __raw_writel(val, hdq_data->hdq_base + offset);
78 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
81 u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
83 __raw_writel(new_val, hdq_data->hdq_base + offset);
89 * Wait for one or more bits in flag change.
90 * HDQ_FLAG_SET: wait until any bit in the flag is set.
91 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
92 * return 0 on success and -ETIMEDOUT in the case of timeout.
94 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
95 u8 flag, u8 flag_set, u8 *status)
98 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
100 if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
101 /* wait for the flag clear */
102 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
103 && time_before(jiffies, timeout)) {
104 schedule_timeout_uninterruptible(1);
108 } else if (flag_set == OMAP_HDQ_FLAG_SET) {
109 /* wait for the flag set */
110 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
111 && time_before(jiffies, timeout)) {
112 schedule_timeout_uninterruptible(1);
114 if (!(*status & flag))
122 /* Clear saved irqstatus after using an interrupt */
123 static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits)
125 unsigned long irqflags;
128 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
129 status = hdq_data->hdq_irqstatus;
130 /* this is a read-modify-write */
131 hdq_data->hdq_irqstatus &= ~bits;
132 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
137 /* write out a byte and fill *status with HDQ_INT_STATUS */
138 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
143 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
149 if (hdq_data->hdq_irqstatus)
150 dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n",
151 hdq_data->hdq_irqstatus);
155 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
158 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
159 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
160 /* wait for the TXCOMPLETE bit */
161 ret = wait_event_timeout(hdq_wait_queue,
162 (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
164 *status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
166 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
171 /* check irqstatus */
172 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
173 dev_dbg(hdq_data->dev, "timeout waiting for"
174 " TXCOMPLETE/RXCOMPLETE, %x\n", *status);
179 /* wait for the GO bit return to zero */
180 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
181 OMAP_HDQ_CTRL_STATUS_GO,
182 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
184 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
185 " return to zero, %x\n", tmp_status);
189 mutex_unlock(&hdq_data->hdq_mutex);
194 /* HDQ Interrupt service routine */
195 static irqreturn_t hdq_isr(int irq, void *_hdq)
197 struct hdq_data *hdq_data = _hdq;
198 unsigned long irqflags;
200 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
201 hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
202 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
203 dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus);
205 if (hdq_data->hdq_irqstatus &
206 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
207 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
208 /* wake up sleeping process */
209 wake_up(&hdq_wait_queue);
215 /* W1 search callback function in HDQ mode */
216 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
217 u8 search_type, w1_slave_found_callback slave_found)
219 u64 module_id, rn_le, cs, id;
226 rn_le = cpu_to_le64(module_id);
228 * HDQ might not obey truly the 1-wire spec.
229 * So calculate CRC based on module parameter.
231 cs = w1_calc_crc8((u8 *)&rn_le, 7);
232 id = (cs << 56) | module_id;
234 slave_found(master_dev, id);
237 /* Issue break pulse to the device */
238 static int omap_hdq_break(struct hdq_data *hdq_data)
243 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
245 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
250 if (hdq_data->hdq_irqstatus)
251 dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n",
252 hdq_data->hdq_irqstatus);
254 /* set the INIT and GO bit */
255 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
256 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
257 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
258 OMAP_HDQ_CTRL_STATUS_GO);
260 /* wait for the TIMEOUT bit */
261 ret = wait_event_timeout(hdq_wait_queue,
262 (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT),
264 tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT);
266 dev_dbg(hdq_data->dev, "break wait elapsed\n");
271 /* check irqstatus */
272 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
273 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n",
280 * check for the presence detect bit to get
281 * set to show that the slave is responding
283 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
284 OMAP_HDQ_CTRL_STATUS_PRESENCE)) {
285 dev_dbg(hdq_data->dev, "Presence bit not set\n");
291 * wait for both INIT and GO bits rerurn to zero.
292 * zero wait time expected for interrupt mode.
294 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
295 OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
296 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
299 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
300 " return to zero, %x\n", tmp_status);
303 mutex_unlock(&hdq_data->hdq_mutex);
308 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
313 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
319 if (pm_runtime_suspended(hdq_data->dev)) {
324 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
325 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
326 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
327 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
329 * The RX comes immediately after TX.
331 wait_event_timeout(hdq_wait_queue,
332 (hdq_data->hdq_irqstatus
333 & (OMAP_HDQ_INT_STATUS_RXCOMPLETE |
334 OMAP_HDQ_INT_STATUS_TIMEOUT)),
336 status = hdq_reset_irqstatus(hdq_data,
337 OMAP_HDQ_INT_STATUS_RXCOMPLETE |
338 OMAP_HDQ_INT_STATUS_TIMEOUT);
339 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
340 OMAP_HDQ_CTRL_STATUS_DIR);
342 /* check irqstatus */
343 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
344 dev_dbg(hdq_data->dev, "timeout waiting for"
345 " RXCOMPLETE, %x", status);
349 } else { /* interrupt had occurred before hdq_read_byte was called */
350 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
352 /* the data is ready. Read it in! */
353 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
355 mutex_unlock(&hdq_data->hdq_mutex);
362 * W1 triplet callback function - used for searching ROM addresses.
363 * Registered only when controller is in 1-wire mode.
365 static u8 omap_w1_triplet(void *_hdq, u8 bdir)
369 u8 ret = 0x3; /* no slaves responded */
370 struct hdq_data *hdq_data = _hdq;
371 u8 ctrl = OMAP_HDQ_CTRL_STATUS_SINGLE | OMAP_HDQ_CTRL_STATUS_GO |
372 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK;
373 u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR;
375 err = pm_runtime_get_sync(hdq_data->dev);
377 pm_runtime_put_noidle(hdq_data->dev);
382 err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
384 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
389 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
390 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
391 err = wait_event_timeout(hdq_wait_queue,
392 (hdq_data->hdq_irqstatus
393 & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
395 /* Must clear irqstatus for another RXCOMPLETE interrupt */
396 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
399 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
402 id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
405 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
406 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
407 err = wait_event_timeout(hdq_wait_queue,
408 (hdq_data->hdq_irqstatus
409 & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
411 /* Must clear irqstatus for another RXCOMPLETE interrupt */
412 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
415 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
418 comp_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
420 if (id_bit && comp_bit) {
421 ret = 0x03; /* no slaves responded */
424 if (!id_bit && !comp_bit) {
425 /* Both bits are valid, take the direction given */
426 ret = bdir ? 0x04 : 0;
428 /* Only one bit is valid, take that direction */
430 ret = id_bit ? 0x05 : 0x02;
434 hdq_reg_out(_hdq, OMAP_HDQ_TX_DATA, bdir);
435 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask);
436 err = wait_event_timeout(hdq_wait_queue,
437 (hdq_data->hdq_irqstatus
438 & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
440 /* Must clear irqstatus for another TXCOMPLETE interrupt */
441 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
444 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
448 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 0,
449 OMAP_HDQ_CTRL_STATUS_SINGLE);
452 mutex_unlock(&hdq_data->hdq_mutex);
454 pm_runtime_mark_last_busy(hdq_data->dev);
455 pm_runtime_put_autosuspend(hdq_data->dev);
461 static u8 omap_w1_reset_bus(void *_hdq)
463 struct hdq_data *hdq_data = _hdq;
466 err = pm_runtime_get_sync(hdq_data->dev);
468 pm_runtime_put_noidle(hdq_data->dev);
473 omap_hdq_break(hdq_data);
475 pm_runtime_mark_last_busy(hdq_data->dev);
476 pm_runtime_put_autosuspend(hdq_data->dev);
481 /* Read a byte of data from the device */
482 static u8 omap_w1_read_byte(void *_hdq)
484 struct hdq_data *hdq_data = _hdq;
488 ret = pm_runtime_get_sync(hdq_data->dev);
490 pm_runtime_put_noidle(hdq_data->dev);
495 ret = hdq_read_byte(hdq_data, &val);
499 pm_runtime_mark_last_busy(hdq_data->dev);
500 pm_runtime_put_autosuspend(hdq_data->dev);
505 /* Write a byte of data to the device */
506 static void omap_w1_write_byte(void *_hdq, u8 byte)
508 struct hdq_data *hdq_data = _hdq;
512 ret = pm_runtime_get_sync(hdq_data->dev);
514 pm_runtime_put_noidle(hdq_data->dev);
520 * We need to reset the slave before
521 * issuing the SKIP ROM command, else
522 * the slave will not work.
524 if (byte == W1_SKIP_ROM)
525 omap_hdq_break(hdq_data);
527 ret = hdq_write_byte(hdq_data, byte, &status);
529 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
534 pm_runtime_mark_last_busy(hdq_data->dev);
535 pm_runtime_put_autosuspend(hdq_data->dev);
538 static struct w1_bus_master omap_w1_master = {
539 .read_byte = omap_w1_read_byte,
540 .write_byte = omap_w1_write_byte,
541 .reset_bus = omap_w1_reset_bus,
544 static int __maybe_unused omap_hdq_runtime_suspend(struct device *dev)
546 struct hdq_data *hdq_data = dev_get_drvdata(dev);
548 hdq_reg_out(hdq_data, 0, hdq_data->mode);
549 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
554 static int __maybe_unused omap_hdq_runtime_resume(struct device *dev)
556 struct hdq_data *hdq_data = dev_get_drvdata(dev);
558 /* select HDQ/1W mode & enable clocks */
559 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
560 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
561 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
563 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
568 static const struct dev_pm_ops omap_hdq_pm_ops = {
569 SET_RUNTIME_PM_OPS(omap_hdq_runtime_suspend,
570 omap_hdq_runtime_resume, NULL)
573 static int omap_hdq_probe(struct platform_device *pdev)
575 struct device *dev = &pdev->dev;
576 struct hdq_data *hdq_data;
581 hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
583 dev_dbg(&pdev->dev, "unable to allocate memory\n");
588 platform_set_drvdata(pdev, hdq_data);
590 hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0);
591 if (IS_ERR(hdq_data->hdq_base))
592 return PTR_ERR(hdq_data->hdq_base);
594 mutex_init(&hdq_data->hdq_mutex);
596 ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
597 if (ret < 0 || !strcmp(mode, "hdq")) {
599 omap_w1_master.search = omap_w1_search_bus;
602 omap_w1_master.triplet = omap_w1_triplet;
605 pm_runtime_enable(&pdev->dev);
606 pm_runtime_use_autosuspend(&pdev->dev);
607 pm_runtime_set_autosuspend_delay(&pdev->dev, 300);
608 ret = pm_runtime_get_sync(&pdev->dev);
610 pm_runtime_put_noidle(&pdev->dev);
611 dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
615 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
616 dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
617 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
619 spin_lock_init(&hdq_data->hdq_spinlock);
621 irq = platform_get_irq(pdev, 0);
623 dev_dbg(&pdev->dev, "Failed to get IRQ: %d\n", irq);
628 ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
630 dev_dbg(&pdev->dev, "could not request irq\n");
634 omap_hdq_break(hdq_data);
636 pm_runtime_mark_last_busy(&pdev->dev);
637 pm_runtime_put_autosuspend(&pdev->dev);
639 omap_w1_master.data = hdq_data;
641 ret = w1_add_master_device(&omap_w1_master);
643 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
650 pm_runtime_put_sync(&pdev->dev);
652 pm_runtime_dont_use_autosuspend(&pdev->dev);
653 pm_runtime_disable(&pdev->dev);
658 static int omap_hdq_remove(struct platform_device *pdev)
662 active = pm_runtime_get_sync(&pdev->dev);
664 pm_runtime_put_noidle(&pdev->dev);
666 w1_remove_master_device(&omap_w1_master);
668 pm_runtime_dont_use_autosuspend(&pdev->dev);
670 pm_runtime_put_sync(&pdev->dev);
671 pm_runtime_disable(&pdev->dev);
676 static const struct of_device_id omap_hdq_dt_ids[] = {
677 { .compatible = "ti,omap3-1w" },
678 { .compatible = "ti,am4372-hdq" },
681 MODULE_DEVICE_TABLE(of, omap_hdq_dt_ids);
683 static struct platform_driver omap_hdq_driver = {
684 .probe = omap_hdq_probe,
685 .remove = omap_hdq_remove,
688 .of_match_table = omap_hdq_dt_ids,
689 .pm = &omap_hdq_pm_ops,
692 module_platform_driver(omap_hdq_driver);
694 MODULE_AUTHOR("Texas Instruments");
695 MODULE_DESCRIPTION("HDQ-1W driver Library");
696 MODULE_LICENSE("GPL");