drivers/w1/masters/omap_hdq.c

   1 /*
   2  * drivers/w1/masters/omap_hdq.c
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  *
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/sched.h>
  20
  21 #include <asm/irq.h>
  22 #include <mach/hardware.h>
  23
  24 #include "../w1.h"
  25 #include "../w1_int.h"
  26
  27 #define MOD_NAME        "OMAP_HDQ:"
  28
  29 #define OMAP_HDQ_REVISION                       0x00
  30 #define OMAP_HDQ_TX_DATA                        0x04
  31 #define OMAP_HDQ_RX_DATA                        0x08
  32 #define OMAP_HDQ_CTRL_STATUS                    0x0c
  33 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK      (1<<6)
  34 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE        (1<<5)
  35 #define OMAP_HDQ_CTRL_STATUS_GO                 (1<<4)
  36 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION     (1<<2)
  37 #define OMAP_HDQ_CTRL_STATUS_DIR                (1<<1)
  38 #define OMAP_HDQ_CTRL_STATUS_MODE               (1<<0)
  39 #define OMAP_HDQ_INT_STATUS                     0x10
  40 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE          (1<<2)
  41 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE          (1<<1)
  42 #define OMAP_HDQ_INT_STATUS_TIMEOUT             (1<<0)
  43 #define OMAP_HDQ_SYSCONFIG                      0x14
  44 #define OMAP_HDQ_SYSCONFIG_SOFTRESET            (1<<1)
  45 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE             (1<<0)
  46 #define OMAP_HDQ_SYSSTATUS                      0x18
  47 #define OMAP_HDQ_SYSSTATUS_RESETDONE            (1<<0)
  48
  49 #define OMAP_HDQ_FLAG_CLEAR                     0
  50 #define OMAP_HDQ_FLAG_SET                       1
  51 #define OMAP_HDQ_TIMEOUT                        (HZ/5)
  52
  53 #define OMAP_HDQ_MAX_USER                       4
  54
  55 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
  56 static int w1_id;
  57
  58 struct hdq_data {
  59         struct device           *dev;
  60         void __iomem            *hdq_base;
  61         /* lock status update */
  62         struct  mutex           hdq_mutex;
  63         int                     hdq_usecount;
  64         struct  clk             *hdq_ick;
  65         struct  clk             *hdq_fck;
  66         u8                      hdq_irqstatus;
  67         /* device lock */
  68         spinlock_t              hdq_spinlock;
  69         /*
  70          * Used to control the call to omap_hdq_get and omap_hdq_put.
  71          * HDQ Protocol: Write the CMD|REG_address first, followed by
  72          * the data wrire or read.
  73          */
  74         int                     init_trans;
  75 };
  76
  77 static int __devinit omap_hdq_probe(struct platform_device *pdev);
  78 static int omap_hdq_remove(struct platform_device *pdev);
  79
  80 static struct platform_driver omap_hdq_driver = {
  81         .probe =        omap_hdq_probe,
  82         .remove =       omap_hdq_remove,
  83         .driver =       {
  84                 .name = "omap_hdq",
  85         },
  86 };
  87
  88 static u8 omap_w1_read_byte(void *_hdq);
  89 static void omap_w1_write_byte(void *_hdq, u8 byte);
  90 static u8 omap_w1_reset_bus(void *_hdq);
  91 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
  92                 u8 search_type, w1_slave_found_callback slave_found);
  93
  94
  95 static struct w1_bus_master omap_w1_master = {
  96         .read_byte      = omap_w1_read_byte,
  97         .write_byte     = omap_w1_write_byte,
  98         .reset_bus      = omap_w1_reset_bus,
  99         .search         = omap_w1_search_bus,
 100 };
 101
 102 /* HDQ register I/O routines */
 103 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
 104 {
 105         return __raw_readb(hdq_data->hdq_base + offset);
 106 }
 107
 108 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
 109 {
 110         __raw_writeb(val, hdq_data->hdq_base + offset);
 111 }
 112
 113 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
 114                         u8 val, u8 mask)
 115 {
 116         u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
 117                         | (val & mask);
 118         __raw_writeb(new_val, hdq_data->hdq_base + offset);
 119
 120         return new_val;
 121 }
 122
 123 /*
 124  * Wait for one or more bits in flag change.
 125  * HDQ_FLAG_SET: wait until any bit in the flag is set.
 126  * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 127  * return 0 on success and -ETIMEDOUT in the case of timeout.
 128  */
 129 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
 130                 u8 flag, u8 flag_set, u8 *status)
 131 {
 132         int ret = 0;
 133         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 134
 135         if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
 136                 /* wait for the flag clear */
 137                 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
 138                         && time_before(jiffies, timeout)) {
 139                         schedule_timeout_uninterruptible(1);
 140                 }
 141                 if (*status & flag)
 142                         ret = -ETIMEDOUT;
 143         } else if (flag_set == OMAP_HDQ_FLAG_SET) {
 144                 /* wait for the flag set */
 145                 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
 146                         && time_before(jiffies, timeout)) {
 147                         schedule_timeout_uninterruptible(1);
 148                 }
 149                 if (!(*status & flag))
 150                         ret = -ETIMEDOUT;
 151         } else
 152                 return -EINVAL;
 153
 154         return ret;
 155 }
 156
 157 /* write out a byte and fill *status with HDQ_INT_STATUS */
 158 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
 159 {
 160         int ret;
 161         u8 tmp_status;
 162         unsigned long irqflags;
 163
 164         *status = 0;
 165
 166         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 167         /* clear interrupt flags via a dummy read */
 168         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 169         /* ISR loads it with new INT_STATUS */
 170         hdq_data->hdq_irqstatus = 0;
 171         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 172
 173         hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
 174
 175         /* set the GO bit */
 176         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 177                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 178         /* wait for the TXCOMPLETE bit */
 179         ret = wait_event_timeout(hdq_wait_queue,
 180                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 181         if (ret == 0) {
 182                 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
 183                 ret = -ETIMEDOUT;
 184                 goto out;
 185         }
 186
 187         *status = hdq_data->hdq_irqstatus;
 188         /* check irqstatus */
 189         if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
 190                 dev_dbg(hdq_data->dev, "timeout waiting for"
 191                         " TXCOMPLETE/RXCOMPLETE, %x", *status);
 192                 ret = -ETIMEDOUT;
 193                 goto out;
 194         }
 195
 196         /* wait for the GO bit return to zero */
 197         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 198                         OMAP_HDQ_CTRL_STATUS_GO,
 199                         OMAP_HDQ_FLAG_CLEAR, &tmp_status);
 200         if (ret) {
 201                 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
 202                         " return to zero, %x", tmp_status);
 203         }
 204
 205 out:
 206         return ret;
 207 }
 208
 209 /* HDQ Interrupt service routine */
 210 static irqreturn_t hdq_isr(int irq, void *_hdq)
 211 {
 212         struct hdq_data *hdq_data = _hdq;
 213         unsigned long irqflags;
 214
 215         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 216         hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 217         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 218         dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
 219
 220         if (hdq_data->hdq_irqstatus &
 221                 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
 222                 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 223                 /* wake up sleeping process */
 224                 wake_up(&hdq_wait_queue);
 225         }
 226
 227         return IRQ_HANDLED;
 228 }
 229
 230 /* HDQ Mode: always return success */
 231 static u8 omap_w1_reset_bus(void *_hdq)
 232 {
 233         return 0;
 234 }
 235
 236 /* W1 search callback function */
 237 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
 238                 u8 search_type, w1_slave_found_callback slave_found)
 239 {
 240         u64 module_id, rn_le, cs, id;
 241
 242         if (w1_id)
 243                 module_id = w1_id;
 244         else
 245                 module_id = 0x1;
 246
 247         rn_le = cpu_to_le64(module_id);
 248         /*
 249          * HDQ might not obey truly the 1-wire spec.
 250          * So calculate CRC based on module parameter.
 251          */
 252         cs = w1_calc_crc8((u8 *)&rn_le, 7);
 253         id = (cs << 56) | module_id;
 254
 255         slave_found(master_dev, id);
 256 }
 257
 258 static int _omap_hdq_reset(struct hdq_data *hdq_data)
 259 {
 260         int ret;
 261         u8 tmp_status;
 262
 263         hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
 264         /*
 265          * Select HDQ mode & enable clocks.
 266          * It is observed that INT flags can't be cleared via a read and GO/INIT
 267          * won't return to zero if interrupt is disabled. So we always enable
 268          * interrupt.
 269          */
 270         hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 271                 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 272                 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 273
 274         /* wait for reset to complete */
 275         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
 276                 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
 277         if (ret)
 278                 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
 279                                 tmp_status);
 280         else {
 281                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 282                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 283                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 284                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 285                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 286         }
 287
 288         return ret;
 289 }
 290
 291 /* Issue break pulse to the device */
 292 static int omap_hdq_break(struct hdq_data *hdq_data)
 293 {
 294         int ret = 0;
 295         u8 tmp_status;
 296         unsigned long irqflags;
 297
 298         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 299         if (ret < 0) {
 300                 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 301                 ret = -EINTR;
 302                 goto rtn;
 303         }
 304
 305         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 306         /* clear interrupt flags via a dummy read */
 307         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 308         /* ISR loads it with new INT_STATUS */
 309         hdq_data->hdq_irqstatus = 0;
 310         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 311
 312         /* set the INIT and GO bit */
 313         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 314                 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
 315                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 316                 OMAP_HDQ_CTRL_STATUS_GO);
 317
 318         /* wait for the TIMEOUT bit */
 319         ret = wait_event_timeout(hdq_wait_queue,
 320                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 321         if (ret == 0) {
 322                 dev_dbg(hdq_data->dev, "break wait elapsed\n");
 323                 ret = -EINTR;
 324                 goto out;
 325         }
 326
 327         tmp_status = hdq_data->hdq_irqstatus;
 328         /* check irqstatus */
 329         if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 330                 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
 331                                 tmp_status);
 332                 ret = -ETIMEDOUT;
 333                 goto out;
 334         }
 335         /*
 336          * wait for both INIT and GO bits rerurn to zero.
 337          * zero wait time expected for interrupt mode.
 338          */
 339         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 340                         OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 341                         OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
 342                         &tmp_status);
 343         if (ret)
 344                 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
 345                         " return to zero, %x", tmp_status);
 346
 347 out:
 348         mutex_unlock(&hdq_data->hdq_mutex);
 349 rtn:
 350         return ret;
 351 }
 352
 353 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
 354 {
 355         int ret = 0;
 356         u8 status;
 357
 358         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 359         if (ret < 0) {
 360                 ret = -EINTR;
 361                 goto rtn;
 362         }
 363
 364         if (!hdq_data->hdq_usecount) {
 365                 ret = -EINVAL;
 366                 goto out;
 367         }
 368
 369         if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 370                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 371                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
 372                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 373                 /*
 374                  * The RX comes immediately after TX.
 375                  */
 376                 wait_event_timeout(hdq_wait_queue,
 377                                    (hdq_data->hdq_irqstatus
 378                                     & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
 379                                    OMAP_HDQ_TIMEOUT);
 380
 381                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
 382                         OMAP_HDQ_CTRL_STATUS_DIR);
 383                 status = hdq_data->hdq_irqstatus;
 384                 /* check irqstatus */
 385                 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 386                         dev_dbg(hdq_data->dev, "timeout waiting for"
 387                                 " RXCOMPLETE, %x", status);
 388                         ret = -ETIMEDOUT;
 389                         goto out;
 390                 }
 391         }
 392         /* the data is ready. Read it in! */
 393         *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
 394 out:
 395         mutex_unlock(&hdq_data->hdq_mutex);
 396 rtn:
 397         return ret;
 398
 399 }
 400
 401 /* Enable clocks and set the controller to HDQ mode */
 402 static int omap_hdq_get(struct hdq_data *hdq_data)
 403 {
 404         int ret = 0;
 405
 406         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 407         if (ret < 0) {
 408                 ret = -EINTR;
 409                 goto rtn;
 410         }
 411
 412         if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
 413                 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
 414                 ret = -EINVAL;
 415                 goto out;
 416         } else {
 417                 hdq_data->hdq_usecount++;
 418                 try_module_get(THIS_MODULE);
 419                 if (1 == hdq_data->hdq_usecount) {
 420                         if (clk_enable(hdq_data->hdq_ick)) {
 421                                 dev_dbg(hdq_data->dev, "Can not enable ick\n");
 422                                 ret = -ENODEV;
 423                                 goto clk_err;
 424                         }
 425                         if (clk_enable(hdq_data->hdq_fck)) {
 426                                 dev_dbg(hdq_data->dev, "Can not enable fck\n");
 427                                 clk_disable(hdq_data->hdq_ick);
 428                                 ret = -ENODEV;
 429                                 goto clk_err;
 430                         }
 431
 432                         /* make sure HDQ is out of reset */
 433                         if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
 434                                 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
 435                                 ret = _omap_hdq_reset(hdq_data);
 436                                 if (ret)
 437                                         /* back up the count */
 438                                         hdq_data->hdq_usecount--;
 439                         } else {
 440                                 /* select HDQ mode & enable clocks */
 441                                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 442                                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 443                                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 444                                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 445                                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 446                                 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 447                         }
 448                 }
 449         }
 450
 451 clk_err:
 452         clk_put(hdq_data->hdq_ick);
 453         clk_put(hdq_data->hdq_fck);
 454 out:
 455         mutex_unlock(&hdq_data->hdq_mutex);
 456 rtn:
 457         return ret;
 458 }
 459
 460 /* Disable clocks to the module */
 461 static int omap_hdq_put(struct hdq_data *hdq_data)
 462 {
 463         int ret = 0;
 464
 465         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 466         if (ret < 0)
 467                 return -EINTR;
 468
 469         if (0 == hdq_data->hdq_usecount) {
 470                 dev_dbg(hdq_data->dev, "attempt to decrement use count"
 471                         " when it is zero");
 472                 ret = -EINVAL;
 473         } else {
 474                 hdq_data->hdq_usecount--;
 475                 module_put(THIS_MODULE);
 476                 if (0 == hdq_data->hdq_usecount) {
 477                         clk_disable(hdq_data->hdq_ick);
 478                         clk_disable(hdq_data->hdq_fck);
 479                 }
 480         }
 481         mutex_unlock(&hdq_data->hdq_mutex);
 482
 483         return ret;
 484 }
 485
 486 /* Read a byte of data from the device */
 487 static u8 omap_w1_read_byte(void *_hdq)
 488 {
 489         struct hdq_data *hdq_data = _hdq;
 490         u8 val = 0;
 491         int ret;
 492
 493         ret = hdq_read_byte(hdq_data, &val);
 494         if (ret) {
 495                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 496                 if (ret < 0) {
 497                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 498                         return -EINTR;
 499                 }
 500                 hdq_data->init_trans = 0;
 501                 mutex_unlock(&hdq_data->hdq_mutex);
 502                 omap_hdq_put(hdq_data);
 503                 return -1;
 504         }
 505
 506         /* Write followed by a read, release the module */
 507         if (hdq_data->init_trans) {
 508                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 509                 if (ret < 0) {
 510                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 511                         return -EINTR;
 512                 }
 513                 hdq_data->init_trans = 0;
 514                 mutex_unlock(&hdq_data->hdq_mutex);
 515                 omap_hdq_put(hdq_data);
 516         }
 517
 518         return val;
 519 }
 520
 521 /* Write a byte of data to the device */
 522 static void omap_w1_write_byte(void *_hdq, u8 byte)
 523 {
 524         struct hdq_data *hdq_data = _hdq;
 525         int ret;
 526         u8 status;
 527
 528         /* First write to initialize the transfer */
 529         if (hdq_data->init_trans == 0)
 530                 omap_hdq_get(hdq_data);
 531
 532         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 533         if (ret < 0) {
 534                 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 535                 return;
 536         }
 537         hdq_data->init_trans++;
 538         mutex_unlock(&hdq_data->hdq_mutex);
 539
 540         ret = hdq_write_byte(hdq_data, byte, &status);
 541         if (ret < 0) {
 542                 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
 543                 return;
 544         }
 545
 546         /* Second write, data transferred. Release the module */
 547         if (hdq_data->init_trans > 1) {
 548                 omap_hdq_put(hdq_data);
 549                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 550                 if (ret < 0) {
 551                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 552                         return;
 553                 }
 554                 hdq_data->init_trans = 0;
 555                 mutex_unlock(&hdq_data->hdq_mutex);
 556         }
 557
 558         return;
 559 }
 560
 561 static int __devinit omap_hdq_probe(struct platform_device *pdev)
 562 {
 563         struct hdq_data *hdq_data;
 564         struct resource *res;
 565         int ret, irq;
 566         u8 rev;
 567
 568         hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
 569         if (!hdq_data) {
 570                 dev_dbg(&pdev->dev, "unable to allocate memory\n");
 571                 ret = -ENOMEM;
 572                 goto err_kmalloc;
 573         }
 574
 575         hdq_data->dev = &pdev->dev;
 576         platform_set_drvdata(pdev, hdq_data);
 577
 578         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 579         if (!res) {
 580                 dev_dbg(&pdev->dev, "unable to get resource\n");
 581                 ret = -ENXIO;
 582                 goto err_resource;
 583         }
 584
 585         hdq_data->hdq_base = ioremap(res->start, SZ_4K);
 586         if (!hdq_data->hdq_base) {
 587                 dev_dbg(&pdev->dev, "ioremap failed\n");
 588                 ret = -EINVAL;
 589                 goto err_ioremap;
 590         }
 591
 592         /* get interface & functional clock objects */
 593         hdq_data->hdq_ick = clk_get(&pdev->dev, "ick");
 594         if (IS_ERR(hdq_data->hdq_ick)) {
 595                 dev_dbg(&pdev->dev, "Can't get HDQ ick clock object\n");
 596                 ret = PTR_ERR(hdq_data->hdq_ick);
 597                 goto err_ick;
 598         }
 599
 600         hdq_data->hdq_fck = clk_get(&pdev->dev, "fck");
 601         if (IS_ERR(hdq_data->hdq_fck)) {
 602                 dev_dbg(&pdev->dev, "Can't get HDQ fck clock object\n");
 603                 ret = PTR_ERR(hdq_data->hdq_fck);
 604                 goto err_fck;
 605         }
 606
 607         hdq_data->hdq_usecount = 0;
 608         mutex_init(&hdq_data->hdq_mutex);
 609
 610         if (clk_enable(hdq_data->hdq_ick)) {
 611                 dev_dbg(&pdev->dev, "Can not enable ick\n");
 612                 ret = -ENODEV;
 613                 goto err_intfclk;
 614         }
 615
 616         if (clk_enable(hdq_data->hdq_fck)) {
 617                 dev_dbg(&pdev->dev, "Can not enable fck\n");
 618                 ret = -ENODEV;
 619                 goto err_fnclk;
 620         }
 621
 622         rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
 623         dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
 624                 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
 625
 626         spin_lock_init(&hdq_data->hdq_spinlock);
 627
 628         irq = platform_get_irq(pdev, 0);
 629         if (irq < 0) {
 630                 ret = -ENXIO;
 631                 goto err_irq;
 632         }
 633
 634         ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
 635         if (ret < 0) {
 636                 dev_dbg(&pdev->dev, "could not request irq\n");
 637                 goto err_irq;
 638         }
 639
 640         omap_hdq_break(hdq_data);
 641
 642         /* don't clock the HDQ until it is needed */
 643         clk_disable(hdq_data->hdq_ick);
 644         clk_disable(hdq_data->hdq_fck);
 645
 646         omap_w1_master.data = hdq_data;
 647
 648         ret = w1_add_master_device(&omap_w1_master);
 649         if (ret) {
 650                 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
 651                 goto err_w1;
 652         }
 653
 654         return 0;
 655
 656 err_w1:
 657 err_irq:
 658         clk_disable(hdq_data->hdq_fck);
 659
 660 err_fnclk:
 661         clk_disable(hdq_data->hdq_ick);
 662
 663 err_intfclk:
 664         clk_put(hdq_data->hdq_fck);
 665
 666 err_fck:
 667         clk_put(hdq_data->hdq_ick);
 668
 669 err_ick:
 670         iounmap(hdq_data->hdq_base);
 671
 672 err_ioremap:
 673 err_resource:
 674         platform_set_drvdata(pdev, NULL);
 675         kfree(hdq_data);
 676
 677 err_kmalloc:
 678         return ret;
 679
 680 }
 681
 682 static int omap_hdq_remove(struct platform_device *pdev)
 683 {
 684         struct hdq_data *hdq_data = platform_get_drvdata(pdev);
 685
 686         mutex_lock(&hdq_data->hdq_mutex);
 687
 688         if (hdq_data->hdq_usecount) {
 689                 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
 690                 mutex_unlock(&hdq_data->hdq_mutex);
 691                 return -EBUSY;
 692         }
 693
 694         mutex_unlock(&hdq_data->hdq_mutex);
 695
 696         /* remove module dependency */
 697         clk_put(hdq_data->hdq_ick);
 698         clk_put(hdq_data->hdq_fck);
 699         free_irq(INT_24XX_HDQ_IRQ, hdq_data);
 700         platform_set_drvdata(pdev, NULL);
 701         iounmap(hdq_data->hdq_base);
 702         kfree(hdq_data);
 703
 704         return 0;
 705 }
 706
 707 static int __init
 708 omap_hdq_init(void)
 709 {
 710         return platform_driver_register(&omap_hdq_driver);
 711 }
 712 module_init(omap_hdq_init);
 713
 714 static void __exit
 715 omap_hdq_exit(void)
 716 {
 717         platform_driver_unregister(&omap_hdq_driver);
 718 }
 719 module_exit(omap_hdq_exit);
 720
 721 module_param(w1_id, int, S_IRUSR);
 722 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
 723
 724 MODULE_AUTHOR("Texas Instruments");
 725 MODULE_DESCRIPTION("HDQ driver Library");
 726 MODULE_LICENSE("GPL");