1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
5 * From Linux kernel include/uapi/linux/virtio_pci.h
8 #ifndef _LINUX_VIRTIO_PCI_H
9 #define _LINUX_VIRTIO_PCI_H
11 #ifndef VIRTIO_PCI_NO_LEGACY
13 /* A 32-bit r/o bitmask of the features supported by the host */
14 #define VIRTIO_PCI_HOST_FEATURES 0
16 /* A 32-bit r/w bitmask of features activated by the guest */
17 #define VIRTIO_PCI_GUEST_FEATURES 4
19 /* A 32-bit r/w PFN for the currently selected queue */
20 #define VIRTIO_PCI_QUEUE_PFN 8
22 /* A 16-bit r/o queue size for the currently selected queue */
23 #define VIRTIO_PCI_QUEUE_NUM 12
25 /* A 16-bit r/w queue selector */
26 #define VIRTIO_PCI_QUEUE_SEL 14
28 /* A 16-bit r/w queue notifier */
29 #define VIRTIO_PCI_QUEUE_NOTIFY 16
31 /* An 8-bit device status register */
32 #define VIRTIO_PCI_STATUS 18
35 * An 8-bit r/o interrupt status register. Reading the value will return the
36 * current contents of the ISR and will also clear it. This is effectively
37 * a read-and-acknowledge.
39 #define VIRTIO_PCI_ISR 19
41 /* MSI-X registers: only enabled if MSI-X is enabled */
43 /* A 16-bit vector for configuration changes */
44 #define VIRTIO_MSI_CONFIG_VECTOR 20
45 /* A 16-bit vector for selected queue notifications */
46 #define VIRTIO_MSI_QUEUE_VECTOR 22
49 * The remaining space is defined by each driver as the per-driver
52 #define VIRTIO_PCI_CONFIG_OFF(msix) ((msix) ? 24 : 20)
54 /* Virtio ABI version, this must match exactly */
55 #define VIRTIO_PCI_ABI_VERSION 0
58 * How many bits to shift physical queue address written to QUEUE_PFN.
59 * 12 is historical, and due to x86 page size.
61 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
64 * The alignment to use between consumer and producer parts of vring.
67 #define VIRTIO_PCI_VRING_ALIGN 4096
69 #endif /* VIRTIO_PCI_NO_LEGACY */
71 /* The bit of the ISR which indicates a device configuration change */
72 #define VIRTIO_PCI_ISR_CONFIG 0x2
73 /* Vector value used to disable MSI for queue */
74 #define VIRTIO_MSI_NO_VECTOR 0xffff
76 #ifndef VIRTIO_PCI_NO_MODERN
78 /* IDs for different capabilities. Must all exist. */
80 /* Common configuration */
81 #define VIRTIO_PCI_CAP_COMMON_CFG 1
83 #define VIRTIO_PCI_CAP_NOTIFY_CFG 2
85 #define VIRTIO_PCI_CAP_ISR_CFG 3
86 /* Device specific configuration */
87 #define VIRTIO_PCI_CAP_DEVICE_CFG 4
88 /* PCI configuration access */
89 #define VIRTIO_PCI_CAP_PCI_CFG 5
91 /* This is the PCI capability header: */
92 struct virtio_pci_cap {
93 __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
94 __u8 cap_next; /* Generic PCI field: next ptr */
95 __u8 cap_len; /* Generic PCI field: capability length */
96 __u8 cfg_type; /* Identifies the structure */
97 __u8 bar; /* Where to find it */
98 __u8 padding[3]; /* Pad to full dword */
99 __le32 offset; /* Offset within bar */
100 __le32 length; /* Length of the structure, in bytes */
103 struct virtio_pci_notify_cap {
104 struct virtio_pci_cap cap;
105 __le32 notify_off_multiplier; /* Multiplier for queue_notify_off */
108 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
109 struct virtio_pci_common_cfg {
110 /* About the whole device */
111 __le32 device_feature_select; /* read-write */
112 __le32 device_feature; /* read-only */
113 __le32 guest_feature_select; /* read-write */
114 __le32 guest_feature; /* read-write */
115 __le16 msix_config; /* read-write */
116 __le16 num_queues; /* read-only */
117 __u8 device_status; /* read-write */
118 __u8 config_generation; /* read-only */
120 /* About a specific virtqueue */
121 __le16 queue_select; /* read-write */
122 __le16 queue_size; /* read-write, power of 2 */
123 __le16 queue_msix_vector; /* read-write */
124 __le16 queue_enable; /* read-write */
125 __le16 queue_notify_off; /* read-only */
126 __le32 queue_desc_lo; /* read-write */
127 __le32 queue_desc_hi; /* read-write */
128 __le32 queue_avail_lo; /* read-write */
129 __le32 queue_avail_hi; /* read-write */
130 __le32 queue_used_lo; /* read-write */
131 __le32 queue_used_hi; /* read-write */
134 /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
135 struct virtio_pci_cfg_cap {
136 struct virtio_pci_cap cap;
137 __u8 pci_cfg_data[4]; /* Data for BAR access */
140 /* Macro versions of offsets for the Old Timers! */
141 #define VIRTIO_PCI_CAP_VNDR 0
142 #define VIRTIO_PCI_CAP_NEXT 1
143 #define VIRTIO_PCI_CAP_LEN 2
144 #define VIRTIO_PCI_CAP_CFG_TYPE 3
145 #define VIRTIO_PCI_CAP_BAR 4
146 #define VIRTIO_PCI_CAP_OFFSET 8
147 #define VIRTIO_PCI_CAP_LENGTH 12
149 #define VIRTIO_PCI_NOTIFY_CAP_MULT 16
151 #define VIRTIO_PCI_COMMON_DFSELECT 0
152 #define VIRTIO_PCI_COMMON_DF 4
153 #define VIRTIO_PCI_COMMON_GFSELECT 8
154 #define VIRTIO_PCI_COMMON_GF 12
155 #define VIRTIO_PCI_COMMON_MSIX 16
156 #define VIRTIO_PCI_COMMON_NUMQ 18
157 #define VIRTIO_PCI_COMMON_STATUS 20
158 #define VIRTIO_PCI_COMMON_CFGGENERATION 21
159 #define VIRTIO_PCI_COMMON_Q_SELECT 22
160 #define VIRTIO_PCI_COMMON_Q_SIZE 24
161 #define VIRTIO_PCI_COMMON_Q_MSIX 26
162 #define VIRTIO_PCI_COMMON_Q_ENABLE 28
163 #define VIRTIO_PCI_COMMON_Q_NOFF 30
164 #define VIRTIO_PCI_COMMON_Q_DESCLO 32
165 #define VIRTIO_PCI_COMMON_Q_DESCHI 36
166 #define VIRTIO_PCI_COMMON_Q_AVAILLO 40
167 #define VIRTIO_PCI_COMMON_Q_AVAILHI 44
168 #define VIRTIO_PCI_COMMON_Q_USEDLO 48
169 #define VIRTIO_PCI_COMMON_Q_USEDHI 52
171 #endif /* VIRTIO_PCI_NO_MODERN */
173 #endif /* _LINUX_VIRTIO_PCI_H */