2 * Xilinx TFT frame buffer driver
4 * Author: MontaVista Software, Inc.
7 * 2002-2007 (c) MontaVista Software, Inc.
8 * 2007 (c) Secret Lab Technologies, Ltd.
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
17 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
18 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
19 * was based on skeletonfb.c, Skeleton for a frame buffer device by
23 #include <linux/device.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/of_device.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_address.h>
36 #include <linux/xilinxfb.h>
37 #include <linux/slab.h>
43 #define DRIVER_NAME "xilinxfb"
47 * Xilinx calls it "TFT LCD Controller" though it can also be used for
48 * the VGA port on the Xilinx ML40x board. This is a hardware display
49 * controller for a 640x480 resolution TFT or VGA screen.
51 * The interface to the framebuffer is nice and simple. There are two
52 * control registers. The first tells the LCD interface where in memory
53 * the frame buffer is (only the 11 most significant bits are used, so
54 * don't start thinking about scrolling). The second allows the LCD to
55 * be turned on or off as well as rotated 180 degrees.
57 * In case of direct BUS access the second control register will be at
58 * an offset of 4 as compared to the DCR access where the offset is 1
59 * i.e. REG_CTRL. So this is taken care in the function
60 * xilinx_fb_out32 where it left shifts the offset 2 times in case of
66 #define REG_CTRL_ENABLE 0x0001
67 #define REG_CTRL_ROTATE 0x0002
70 * The hardware only handles a single mode: 640x480 24 bit true
71 * color. Each pixel gets a word (32 bits) of memory. Within each word,
72 * the 8 most significant bits are ignored, the next 8 bits are the red
73 * level, the next 8 bits are the green level and the 8 least
74 * significant bits are the blue level. Each row of the LCD uses 1024
75 * words, but only the first 640 pixels are displayed with the other 384
76 * words being ignored. There are 480 rows.
78 #define BYTES_PER_PIXEL 4
79 #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
85 #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
88 * Default xilinxfb configuration
90 static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
98 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
100 static struct fb_fix_screeninfo xilinx_fb_fix = {
102 .type = FB_TYPE_PACKED_PIXELS,
103 .visual = FB_VISUAL_TRUECOLOR,
104 .accel = FB_ACCEL_NONE
107 static struct fb_var_screeninfo xilinx_fb_var = {
108 .bits_per_pixel = BITS_PER_PIXEL,
110 .red = { RED_SHIFT, 8, 0 },
111 .green = { GREEN_SHIFT, 8, 0 },
112 .blue = { BLUE_SHIFT, 8, 0 },
113 .transp = { 0, 0, 0 },
115 .activate = FB_ACTIVATE_NOW
119 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
121 struct xilinxfb_drvdata {
123 struct fb_info info; /* FB driver info record */
125 phys_addr_t regs_phys; /* phys. address of the control
127 void __iomem *regs; /* virt. address of the control
129 #ifdef CONFIG_PPC_DCR
131 unsigned int dcr_len;
133 void *fb_virt; /* virt. address of the frame buffer */
134 dma_addr_t fb_phys; /* phys. address of the frame buffer */
135 int fb_alloced; /* Flag, was the fb memory alloced? */
137 u8 flags; /* features of the driver */
139 u32 reg_ctrl_default;
141 u32 pseudo_palette[PALETTE_ENTRIES_NO];
142 /* Fake palette of 16 colors */
145 #define to_xilinxfb_drvdata(_info) \
146 container_of(_info, struct xilinxfb_drvdata, info)
149 * The XPS TFT Controller can be accessed through BUS or DCR interface.
150 * To perform the read/write on the registers we need to check on
151 * which bus its connected and call the appropriate write API.
153 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
156 if (drvdata->flags & BUS_ACCESS_FLAG)
157 out_be32(drvdata->regs + (offset << 2), val);
158 #ifdef CONFIG_PPC_DCR
160 dcr_write(drvdata->dcr_host, offset, val);
165 xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
166 unsigned transp, struct fb_info *fbi)
168 u32 *palette = fbi->pseudo_palette;
170 if (regno >= PALETTE_ENTRIES_NO)
173 if (fbi->var.grayscale) {
174 /* Convert color to grayscale.
175 * grayscale = 0.30*R + 0.59*G + 0.11*B */
177 (red * 77 + green * 151 + blue * 28 + 127) >> 8;
180 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
182 /* We only handle 8 bits of each color. */
186 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
187 (blue << BLUE_SHIFT);
193 xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
195 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
197 switch (blank_mode) {
198 case FB_BLANK_UNBLANK:
200 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
203 case FB_BLANK_NORMAL:
204 case FB_BLANK_VSYNC_SUSPEND:
205 case FB_BLANK_HSYNC_SUSPEND:
206 case FB_BLANK_POWERDOWN:
208 xilinx_fb_out32(drvdata, REG_CTRL, 0);
213 return 0; /* success */
216 static struct fb_ops xilinxfb_ops =
218 .owner = THIS_MODULE,
219 .fb_setcolreg = xilinx_fb_setcolreg,
220 .fb_blank = xilinx_fb_blank,
221 .fb_fillrect = cfb_fillrect,
222 .fb_copyarea = cfb_copyarea,
223 .fb_imageblit = cfb_imageblit,
226 /* ---------------------------------------------------------------------
227 * Bus independent setup/teardown
230 static int xilinxfb_assign(struct platform_device *pdev,
231 struct xilinxfb_drvdata *drvdata,
232 struct xilinxfb_platform_data *pdata)
235 struct device *dev = &pdev->dev;
236 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
238 if (drvdata->flags & BUS_ACCESS_FLAG) {
239 struct resource *res;
241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
242 drvdata->regs_phys = res->start;
243 drvdata->regs = devm_request_and_ioremap(&pdev->dev, res);
244 if (!drvdata->regs) {
250 /* Allocate the framebuffer memory */
251 if (pdata->fb_phys) {
252 drvdata->fb_phys = pdata->fb_phys;
253 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
255 drvdata->fb_alloced = 1;
256 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
257 &drvdata->fb_phys, GFP_KERNEL);
260 if (!drvdata->fb_virt) {
261 dev_err(dev, "Could not allocate frame buffer memory\n");
263 if (drvdata->flags & BUS_ACCESS_FLAG)
269 /* Clear (turn to black) the framebuffer */
270 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
272 /* Tell the hardware where the frame buffer is */
273 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
275 /* Turn on the display */
276 drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
277 if (pdata->rotate_screen)
278 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
279 xilinx_fb_out32(drvdata, REG_CTRL,
280 drvdata->reg_ctrl_default);
282 /* Fill struct fb_info */
283 drvdata->info.device = dev;
284 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
285 drvdata->info.fbops = &xilinxfb_ops;
286 drvdata->info.fix = xilinx_fb_fix;
287 drvdata->info.fix.smem_start = drvdata->fb_phys;
288 drvdata->info.fix.smem_len = fbsize;
289 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
291 drvdata->info.pseudo_palette = drvdata->pseudo_palette;
292 drvdata->info.flags = FBINFO_DEFAULT;
293 drvdata->info.var = xilinx_fb_var;
294 drvdata->info.var.height = pdata->screen_height_mm;
295 drvdata->info.var.width = pdata->screen_width_mm;
296 drvdata->info.var.xres = pdata->xres;
297 drvdata->info.var.yres = pdata->yres;
298 drvdata->info.var.xres_virtual = pdata->xvirt;
299 drvdata->info.var.yres_virtual = pdata->yvirt;
301 /* Allocate a colour map */
302 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
304 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
309 /* Register new frame buffer */
310 rc = register_framebuffer(&drvdata->info);
312 dev_err(dev, "Could not register frame buffer\n");
316 if (drvdata->flags & BUS_ACCESS_FLAG) {
317 /* Put a banner in the log (for DEBUG) */
318 dev_dbg(dev, "regs: phys=%x, virt=%p\n", drvdata->regs_phys,
321 /* Put a banner in the log (for DEBUG) */
322 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
323 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
325 return 0; /* success */
328 fb_dealloc_cmap(&drvdata->info.cmap);
331 if (drvdata->fb_alloced)
332 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
335 iounmap(drvdata->fb_virt);
337 /* Turn off the display */
338 xilinx_fb_out32(drvdata, REG_CTRL, 0);
341 if (drvdata->flags & BUS_ACCESS_FLAG)
342 devm_iounmap(dev, drvdata->regs);
346 dev_set_drvdata(dev, NULL);
351 static int xilinxfb_release(struct device *dev)
353 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
355 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
356 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
359 unregister_framebuffer(&drvdata->info);
361 fb_dealloc_cmap(&drvdata->info.cmap);
363 if (drvdata->fb_alloced)
364 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
365 drvdata->fb_virt, drvdata->fb_phys);
367 iounmap(drvdata->fb_virt);
369 /* Turn off the display */
370 xilinx_fb_out32(drvdata, REG_CTRL, 0);
372 /* Release the resources, as allocated based on interface */
373 if (drvdata->flags & BUS_ACCESS_FLAG)
374 devm_iounmap(dev, drvdata->regs);
375 #ifdef CONFIG_PPC_DCR
377 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
381 dev_set_drvdata(dev, NULL);
386 /* ---------------------------------------------------------------------
390 static int xilinxfb_of_probe(struct platform_device *op)
394 struct xilinxfb_platform_data pdata;
396 struct xilinxfb_drvdata *drvdata;
398 /* Copy with the default pdata (not a ptr reference!) */
399 pdata = xilinx_fb_default_pdata;
401 /* Allocate the driver data region */
402 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
404 dev_err(&op->dev, "Couldn't allocate device private record\n");
409 * To check whether the core is connected directly to DCR or BUS
410 * interface and initialize the tft_access accordingly.
412 of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if",
416 * Fill the resource structure if its direct BUS interface
417 * otherwise fill the dcr_host structure.
420 drvdata->flags |= BUS_ACCESS_FLAG;
422 #ifdef CONFIG_PPC_DCR
425 start = dcr_resource_start(op->dev.of_node, 0);
426 drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0);
427 drvdata->dcr_host = dcr_map(op->dev.of_node, start, drvdata->dcr_len);
428 if (!DCR_MAP_OK(drvdata->dcr_host)) {
429 dev_err(&op->dev, "invalid DCR address\n");
436 prop = of_get_property(op->dev.of_node, "phys-size", &size);
437 if ((prop) && (size >= sizeof(u32)*2)) {
438 pdata.screen_width_mm = prop[0];
439 pdata.screen_height_mm = prop[1];
442 prop = of_get_property(op->dev.of_node, "resolution", &size);
443 if ((prop) && (size >= sizeof(u32)*2)) {
444 pdata.xres = prop[0];
445 pdata.yres = prop[1];
448 prop = of_get_property(op->dev.of_node, "virtual-resolution", &size);
449 if ((prop) && (size >= sizeof(u32)*2)) {
450 pdata.xvirt = prop[0];
451 pdata.yvirt = prop[1];
454 if (of_find_property(op->dev.of_node, "rotate-display", NULL))
455 pdata.rotate_screen = 1;
457 dev_set_drvdata(&op->dev, drvdata);
458 return xilinxfb_assign(op, drvdata, &pdata);
461 static int xilinxfb_of_remove(struct platform_device *op)
463 return xilinxfb_release(&op->dev);
466 /* Match table for of_platform binding */
467 static struct of_device_id xilinxfb_of_match[] = {
468 { .compatible = "xlnx,xps-tft-1.00.a", },
469 { .compatible = "xlnx,xps-tft-2.00.a", },
470 { .compatible = "xlnx,xps-tft-2.01.a", },
471 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
472 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
475 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
477 static struct platform_driver xilinxfb_of_driver = {
478 .probe = xilinxfb_of_probe,
479 .remove = xilinxfb_of_remove,
482 .owner = THIS_MODULE,
483 .of_match_table = xilinxfb_of_match,
487 module_platform_driver(xilinxfb_of_driver);
489 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
490 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
491 MODULE_LICENSE("GPL");