drivers/video/tidss/tidss_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/
   4  * Nikhil M Jain, n-jain1@ti.com
   5  *
   6  * based on the linux tidss driver, which is
   7  *
   8  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
   9  * Author: Jyri Sarha <jsarha@ti.com>
  10  */
  11
  12 #ifndef __TIDSS_REGS_H
  13 #define __TIDSS_REGS_H
  14
  15 enum dss_common_regs {
  16         NOT_APPLICABLE_OFF = 0,
  17         DSS_REVISION_OFF,
  18         DSS_SYSCONFIG_OFF,
  19         DSS_SYSSTATUS_OFF,
  20         DSS_IRQ_EOI_OFF,
  21         DSS_IRQSTATUS_RAW_OFF,
  22         DSS_IRQSTATUS_OFF,
  23         DSS_IRQENABLE_SET_OFF,
  24         DSS_IRQENABLE_CLR_OFF,
  25         DSS_VID_IRQENABLE_OFF,
  26         DSS_VID_IRQSTATUS_OFF,
  27         DSS_VP_IRQENABLE_OFF,
  28         DSS_VP_IRQSTATUS_OFF,
  29         WB_IRQENABLE_OFF,
  30         WB_IRQSTATUS_OFF,
  31         DSS_GLOBAL_MFLAG_ATTRIBUTE_OFF,
  32         DSS_GLOBAL_OUTPUT_ENABLE_OFF,
  33         DSS_GLOBAL_BUFFER_OFF,
  34         DSS_CBA_CFG_OFF,
  35         DSS_DBG_CONTROL_OFF,
  36         DSS_DBG_STATUS_OFF,
  37         DSS_CLKGATING_DISABLE_OFF,
  38         DSS_SECURE_DISABLE_OFF,
  39         FBDC_REVISION_1_OFF,
  40         FBDC_REVISION_2_OFF,
  41         FBDC_REVISION_3_OFF,
  42         FBDC_REVISION_4_OFF,
  43         FBDC_REVISION_5_OFF,
  44         FBDC_REVISION_6_OFF,
  45         FBDC_COMMON_CONTROL_OFF,
  46         FBDC_CONSTANT_COLOR_0_OFF,
  47         FBDC_CONSTANT_COLOR_1_OFF,
  48         DSS_CONNECTIONS_OFF,
  49         DSS_MSS_VP1_OFF,
  50         DSS_MSS_VP3_OFF,
  51         DSS_COMMON_REG_TABLE_LEN,
  52 };
  53
  54 /*
  55  * dss_common_regmap should be defined as const u16 * and pointing
  56  * to a valid dss common register map for the platform, before the
  57  * macros bellow can be used.
  58  */
  59
  60 #define REG(r) (dss_common_regmap[r ## _OFF])
  61
  62 #define DSS_REVISION                    REG(DSS_REVISION)
  63 #define DSS_SYSCONFIG                   REG(DSS_SYSCONFIG)
  64 #define DSS_SYSSTATUS                   REG(DSS_SYSSTATUS)
  65 #define DSS_IRQ_EOI                     REG(DSS_IRQ_EOI)
  66 #define DSS_IRQSTATUS_RAW               REG(DSS_IRQSTATUS_RAW)
  67 #define DSS_IRQSTATUS                   REG(DSS_IRQSTATUS)
  68 #define DSS_IRQENABLE_SET               REG(DSS_IRQENABLE_SET)
  69 #define DSS_IRQENABLE_CLR               REG(DSS_IRQENABLE_CLR)
  70 #define DSS_VID_IRQENABLE(n)            (REG(DSS_VID_IRQENABLE) + (n) * 4)
  71 #define DSS_VID_IRQSTATUS(n)            (REG(DSS_VID_IRQSTATUS) + (n) * 4)
  72 #define DSS_VP_IRQENABLE(n)             (REG(DSS_VP_IRQENABLE) + (n) * 4)
  73 #define DSS_VP_IRQSTATUS(n)             (REG(DSS_VP_IRQSTATUS) + (n) * 4)
  74 #define WB_IRQENABLE                    REG(WB_IRQENABLE)
  75 #define WB_IRQSTATUS                    REG(WB_IRQSTATUS)
  76
  77 #define DSS_GLOBAL_MFLAG_ATTRIBUTE      REG(DSS_GLOBAL_MFLAG_ATTRIBUTE)
  78 #define DSS_GLOBAL_OUTPUT_ENABLE        REG(DSS_GLOBAL_OUTPUT_ENABLE)
  79 #define DSS_GLOBAL_BUFFER               REG(DSS_GLOBAL_BUFFER)
  80 #define DSS_CBA_CFG                     REG(DSS_CBA_CFG)
  81 #define DSS_DBG_CONTROL         REG(DSS_DBG_CONTROL)
  82 #define DSS_DBG_STATUS          REG(DSS_DBG_STATUS)
  83 #define DSS_CLKGATING_DISABLE           REG(DSS_CLKGATING_DISABLE)
  84 #define DSS_SECURE_DISABLE              REG(DSS_SECURE_DISABLE)
  85
  86 #define FBDC_REVISION_1                 REG(FBDC_REVISION_1)
  87 #define FBDC_REVISION_2                 REG(FBDC_REVISION_2)
  88 #define FBDC_REVISION_3                 REG(FBDC_REVISION_3)
  89 #define FBDC_REVISION_4                 REG(FBDC_REVISION_4)
  90 #define FBDC_REVISION_5                 REG(FBDC_REVISION_5)
  91 #define FBDC_REVISION_6                 REG(FBDC_REVISION_6)
  92 #define FBDC_COMMON_CONTROL             REG(FBDC_COMMON_CONTROL)
  93 #define FBDC_CONSTANT_COLOR_0           REG(FBDC_CONSTANT_COLOR_0)
  94 #define FBDC_CONSTANT_COLOR_1           REG(FBDC_CONSTANT_COLOR_1)
  95 #define DSS_CONNECTIONS         REG(DSS_CONNECTIONS)
  96 #define DSS_MSS_VP1                     REG(DSS_MSS_VP1)
  97 #define DSS_MSS_VP3                     REG(DSS_MSS_VP3)
  98
  99 /* VID */
 100
 101 #define DSS_VID_ACCUH_0         0x0
 102 #define DSS_VID_ACCUH_1         0x4
 103 #define DSS_VID_ACCUH2_0                0x8
 104 #define DSS_VID_ACCUH2_1                0xc
 105 #define DSS_VID_ACCUV_0         0x10
 106 #define DSS_VID_ACCUV_1         0x14
 107 #define DSS_VID_ACCUV2_0                0x18
 108 #define DSS_VID_ACCUV2_1                0x1c
 109 #define DSS_VID_ATTRIBUTES              0x20
 110 #define DSS_VID_ATTRIBUTES2             0x24
 111 #define DSS_VID_BA_0                    0x28
 112 #define DSS_VID_BA_1                    0x2c
 113 #define DSS_VID_BA_UV_0         0x30
 114 #define DSS_VID_BA_UV_1         0x34
 115 #define DSS_VID_BUF_SIZE_STATUS 0x38
 116 #define DSS_VID_BUF_THRESHOLD           0x3c
 117 #define DSS_VID_CSC_COEF(n)             (0x40 + (n) * 4)
 118
 119 #define DSS_VID_FIRH                    0x5c
 120 #define DSS_VID_FIRH2                   0x60
 121 #define DSS_VID_FIRV                    0x64
 122 #define DSS_VID_FIRV2                   0x68
 123
 124 #define DSS_VID_FIR_COEFS_H0            0x6c
 125 #define DSS_VID_FIR_COEF_H0(phase)      (0x6c + (phase) * 4)
 126 #define DSS_VID_FIR_COEFS_H0_C  0x90
 127 #define DSS_VID_FIR_COEF_H0_C(phase)    (0x90 + (phase) * 4)
 128
 129 #define DSS_VID_FIR_COEFS_H12           0xb4
 130 #define DSS_VID_FIR_COEF_H12(phase)     (0xb4 + (phase) * 4)
 131 #define DSS_VID_FIR_COEFS_H12_C 0xf4
 132 #define DSS_VID_FIR_COEF_H12_C(phase)   (0xf4 + (phase) * 4)
 133
 134 #define DSS_VID_FIR_COEFS_V0            0x134
 135 #define DSS_VID_FIR_COEF_V0(phase)      (0x134 + (phase) * 4)
 136 #define DSS_VID_FIR_COEFS_V0_C  0x158
 137 #define DSS_VID_FIR_COEF_V0_C(phase)    (0x158 + (phase) * 4)
 138
 139 #define DSS_VID_FIR_COEFS_V12           0x17c
 140 #define DSS_VID_FIR_COEF_V12(phase)     (0x17c + (phase) * 4)
 141 #define DSS_VID_FIR_COEFS_V12_C 0x1bc
 142 #define DSS_VID_FIR_COEF_V12_C(phase)   (0x1bc + (phase) * 4)
 143
 144 #define DSS_VID_GLOBAL_ALPHA            0x1fc
 145 #define DSS_VID_K2G_IRQENABLE           0x200 /* K2G */
 146 #define DSS_VID_K2G_IRQSTATUS           0x204 /* K2G */
 147 #define DSS_VID_MFLAG_THRESHOLD 0x208
 148 #define DSS_VID_PICTURE_SIZE            0x20c
 149 #define DSS_VID_PIXEL_INC               0x210
 150 #define DSS_VID_K2G_POSITION            0x214 /* K2G */
 151 #define DSS_VID_PRELOAD         0x218
 152 #define DSS_VID_ROW_INC         0x21c
 153 #define DSS_VID_SIZE                    0x220
 154 #define DSS_VID_BA_EXT_0                0x22c
 155 #define DSS_VID_BA_EXT_1                0x230
 156 #define DSS_VID_BA_UV_EXT_0             0x234
 157 #define DSS_VID_BA_UV_EXT_1             0x238
 158 #define DSS_VID_CSC_COEF7               0x23c
 159 #define DSS_VID_ROW_INC_UV              0x248
 160 #define DSS_VID_CLUT                    0x260
 161 #define DSS_VID_SAFETY_ATTRIBUTES       0x2a0
 162 #define DSS_VID_SAFETY_CAPT_SIGNATURE   0x2a4
 163 #define DSS_VID_SAFETY_POSITION 0x2a8
 164 #define DSS_VID_SAFETY_REF_SIGNATURE    0x2ac
 165 #define DSS_VID_SAFETY_SIZE             0x2b0
 166 #define DSS_VID_SAFETY_LFSR_SEED        0x2b4
 167 #define DSS_VID_LUMAKEY         0x2b8
 168 #define DSS_VID_DMA_BUFSIZE             0x2bc /* J721E */
 169
 170 /* OVR */
 171
 172 #define DSS_OVR_CONFIG          0x0
 173 #define DSS_OVR_VIRTVP          0x4 /* J721E */
 174 #define DSS_OVR_DEFAULT_COLOR           0x8
 175 #define DSS_OVR_DEFAULT_COLOR2  0xc
 176 #define DSS_OVR_TRANS_COLOR_MAX 0x10
 177 #define DSS_OVR_TRANS_COLOR_MAX2        0x14
 178 #define DSS_OVR_TRANS_COLOR_MIN 0x18
 179 #define DSS_OVR_TRANS_COLOR_MIN2        0x1c
 180 #define DSS_OVR_ATTRIBUTES(n)           (0x20 + (n) * 4)
 181 #define DSS_OVR_ATTRIBUTES2(n)  (0x34 + (n) * 4) /* J721E */
 182 /* VP */
 183
 184 #define  DSS_VP_CONFIG                          0x0
 185 #define DSS_VP_CONTROL                  0x4
 186 #define DSS_VP_CSC_COEF0                        0x8
 187 #define DSS_VP_CSC_COEF1                        0xc
 188 #define DSS_VP_CSC_COEF2                        0x10
 189 #define DSS_VP_DATA_CYCLE_0                     0x14
 190 #define DSS_VP_DATA_CYCLE_1                     0x18
 191 #define DSS_VP_K2G_GAMMA_TABLE          0x20 /* K2G */
 192 #define DSS_VP_K2G_IRQENABLE                    0x3c /* K2G */
 193 #define DSS_VP_K2G_IRQSTATUS                    0x40 /* K2G */
 194 #define DSS_VP_DATA_CYCLE_2                     0x1c
 195 #define DSS_VP_LINE_NUMBER                      0x44
 196 #define DSS_VP_POL_FREQ                 0x4c
 197 #define DSS_VP_SIZE_SCREEN                      0x50
 198 #define DSS_VP_TIMING_H                 0x54
 199 #define DSS_VP_TIMING_V                 0x58
 200 #define DSS_VP_CSC_COEF3                        0x5c
 201 #define DSS_VP_CSC_COEF4                        0x60
 202 #define DSS_VP_CSC_COEF5                        0x64
 203 #define DSS_VP_CSC_COEF6                        0x68
 204 #define DSS_VP_CSC_COEF7                        0x6c
 205 #define DSS_VP_SAFETY_ATTRIBUTES_0              0x70
 206 #define DSS_VP_SAFETY_ATTRIBUTES_1              0x74
 207 #define DSS_VP_SAFETY_ATTRIBUTES_2              0x78
 208 #define DSS_VP_SAFETY_ATTRIBUTES_3              0x7c
 209 #define DSS_VP_SAFETY_CAPT_SIGNATURE_0  0x90
 210 #define DSS_VP_SAFETY_CAPT_SIGNATURE_1  0x94
 211 #define DSS_VP_SAFETY_CAPT_SIGNATURE_2  0x98
 212 #define DSS_VP_SAFETY_CAPT_SIGNATURE_3  0x9c
 213 #define DSS_VP_SAFETY_POSITION_0                0xb0
 214 #define DSS_VP_SAFETY_POSITION_1                0xb4
 215 #define DSS_VP_SAFETY_POSITION_2                0xb8
 216 #define DSS_VP_SAFETY_POSITION_3                0xbc
 217 #define DSS_VP_SAFETY_REF_SIGNATURE_0           0xd0
 218 #define DSS_VP_SAFETY_REF_SIGNATURE_1           0xd4
 219 #define DSS_VP_SAFETY_REF_SIGNATURE_2           0xd8
 220 #define DSS_VP_SAFETY_REF_SIGNATURE_3           0xdc
 221 #define DSS_VP_SAFETY_SIZE_0                    0xf0
 222 #define DSS_VP_SAFETY_SIZE_1                    0xf4
 223 #define DSS_VP_SAFETY_SIZE_2                    0xf8
 224 #define DSS_VP_SAFETY_SIZE_3                    0xfc
 225 #define DSS_VP_SAFETY_LFSR_SEED         0x110
 226 #define DSS_VP_GAMMA_TABLE                      0x120
 227 #define DSS_VP_DSS_OLDI_CFG                     0x160
 228 #define DSS_VP_DSS_OLDI_STATUS          0x164
 229 #define DSS_VP_DSS_OLDI_LB                      0x168
 230 #define DSS_VP_DSS_MERGE_SPLIT          0x16c /* J721E */
 231 #define DSS_VP_DSS_DMA_THREADSIZE               0x170 /* J721E */
 232 #define DSS_VP_DSS_DMA_THREADSIZE_STATUS        0x174 /* J721E */
 233
 234 /*
 235  * OLDI IO_CTRL register offsets. On AM654 the registers are found
 236  * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from
 237  * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL
 238  * register range.
 239  */
 240 #define OLDI_DAT0_IO_CTRL                       0x00
 241 #define OLDI_DAT1_IO_CTRL                       0x04
 242 #define OLDI_DAT2_IO_CTRL                       0x08
 243 #define OLDI_DAT3_IO_CTRL                       0x0C
 244 #define OLDI_CLK_IO_CTRL                        0x10
 245
 246 /* Only for AM625 OLDI TX */
 247 #define OLDI_PD_CTRL                            0x100
 248 #define OLDI_LB_CTRL                            0x104
 249
 250 #define OLDI_BANDGAP_PWR                        BIT(8)
 251 #define OLDI_PWRDN_TX                           BIT(8)
 252 #define OLDI0_PWRDN_TX                          BIT(0)
 253 #define OLDI1_PWRDN_TX                          BIT(1)
 254
 255 /* Supported plane formats */
 256 #define DSS_FORMAT_ARGB4444 0x0
 257 #define DSS_FORMAT_ABGR4444 0x1
 258 #define DSS_FORMAT_RGBA4444 0x2
 259
 260 #define DSS_FORMAT_RGB565 0x3
 261 #define DSS_FORMAT_BGR565 0x4
 262
 263 #define DSS_FORMAT_ARGB1555 0x5
 264 #define DSS_FORMAT_ABGR1555 0x6
 265
 266 #define DSS_FORMAT_ARGB8888 0x7
 267 #define DSS_FORMAT_ABGR8888 0x8
 268 #define DSS_FORMAT_RGBA8888 0x9
 269 #define DSS_FORMAT_BGRA8888 0xa
 270
 271 #define DSS_FORMAT_RGB888 0xb
 272 #define DSS_FORMAT_BGR888 0xc
 273
 274 #define DSS_FORMAT_ARGB2101010 0xe
 275 #define DSS_FORMAT_ABGR2101010 0xf
 276
 277 #define DSS_FORMAT_XRGB4444 0x20
 278 #define DSS_FORMAT_XBGR4444 0x21
 279 #define DSS_FORMAT_RGBX4444 0x22
 280
 281 #define DSS_FORMAT_XRGB1555 0x25
 282 #define DSS_FORMAT_XBGR1555 0x26
 283
 284 #define DSS_FORMAT_XRGB8888 0x27
 285 #define DSS_FORMAT_XBGR8888 0x28
 286 #define DSS_FORMAT_RGBX8888 0x29
 287 #define DSS_FORMAT_BGRX8888 0x2a
 288
 289 #define DSS_FORMAT_XRGB2101010 0x2e,
 290 #define DSS_FORMAT_XBGR2101010 0x2f,
 291
 292 #endif /* __TIDSS_DSS_REGS_H */