drivers/video/tegra124/sor.c

   1 /*
   2  * Copyright (c) 2011-2013, NVIDIA Corporation.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch-tegra/dc.h>
  14 #include "displayport.h"
  15 #include "sor.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define DEBUG_SOR 0
  20
  21 #define APBDEV_PMC_DPD_SAMPLE                           0x20
  22 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE                0
  23 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE                 1
  24 #define APBDEV_PMC_SEL_DPD_TIM                          0x1c8
  25 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT      0x7f
  26 #define APBDEV_PMC_IO_DPD2_REQ                          0x1c0
  27 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT               25
  28 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF                 (0 << 25)
  29 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON                  (1 << 25)
  30 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT               30
  31 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK        (0x3 << 30)
  32 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE                (0 << 30)
  33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF             (1 << 30)
  34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON              (2 << 30)
  35 #define APBDEV_PMC_IO_DPD2_STATUS                       0x1c4
  36 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT            25
  37 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF              (0 << 25)
  38 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON               (1 << 25)
  39
  40 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
  41 {
  42         return readl((u32 *)sor->base + reg);
  43 }
  44
  45 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
  46                                     u32 val)
  47 {
  48         writel(val, (u32 *)sor->base + reg);
  49 }
  50
  51 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
  52         u32 reg, u32 mask, u32 val)
  53 {
  54         u32 reg_val = tegra_sor_readl(sor, reg);
  55         reg_val &= ~mask;
  56         reg_val |= val;
  57         tegra_sor_writel(sor, reg, reg_val);
  58 }
  59
  60 void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
  61 {
  62         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  63                               DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
  64 }
  65
  66 void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg,
  67                            u32 vs_reg, u32 pc_reg, u8 pc_supported)
  68 {
  69         tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
  70         tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
  71         if (pc_supported) {
  72                 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,
  73                                       pc_reg);
  74         }
  75 }
  76
  77 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
  78                                       u32 mask, u32 exp_val,
  79                                       int poll_interval_us, int timeout_ms)
  80 {
  81         u32 reg_val = 0;
  82         ulong start;
  83
  84         start = get_timer(0);
  85         do {
  86                 reg_val = tegra_sor_readl(sor, reg);
  87                 if (((reg_val & mask) == exp_val))
  88                         return 0;
  89                 udelay(poll_interval_us);
  90         } while (get_timer(start) < timeout_ms);
  91
  92         debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
  93               reg, reg_val, mask, exp_val);
  94
  95         return -ETIMEDOUT;
  96 }
  97
  98 int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
  99 {
 100         u32 reg_val;
 101         u32 orig_val;
 102
 103         orig_val = tegra_sor_readl(sor, PWR);
 104
 105         reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
 106                 PWR_NORMAL_STATE_PD; /* normal state only */
 107
 108         if (reg_val == orig_val)
 109                 return 0;       /* No update needed */
 110
 111         reg_val |= PWR_SETTING_NEW_TRIGGER;
 112         tegra_sor_writel(sor, PWR, reg_val);
 113
 114         /* Poll to confirm it is done */
 115         if (tegra_dc_sor_poll_register(sor, PWR,
 116                                        PWR_SETTING_NEW_DEFAULT_MASK,
 117                                        PWR_SETTING_NEW_DONE,
 118                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 119                 debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
 120                 return -EFAULT;
 121         }
 122
 123         return 0;
 124 }
 125
 126 void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
 127                                  u8 training_pattern,
 128                                  const struct tegra_dp_link_config *link_cfg)
 129 {
 130         u32 reg_val;
 131
 132         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 133
 134         if (ena)
 135                 reg_val |= DP_LINKCTL_ENABLE_YES;
 136         else
 137                 reg_val &= DP_LINKCTL_ENABLE_NO;
 138
 139         reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
 140         reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
 141
 142         if (link_cfg->enhanced_framing)
 143                 reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
 144
 145         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 146
 147         switch (training_pattern) {
 148         case training_pattern_1:
 149                 tegra_sor_writel(sor, DP_TPG, 0x41414141);
 150                 break;
 151         case training_pattern_2:
 152         case training_pattern_3:
 153                 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
 154                         0x43434343 : 0x42424242;
 155                 tegra_sor_writel(sor, DP_TPG, reg_val);
 156                 break;
 157         default:
 158                 tegra_sor_writel(sor, DP_TPG, 0x50505050);
 159                 break;
 160         }
 161 }
 162
 163 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
 164                                               int pu, int is_lvds)
 165 {
 166         u32 reg_val;
 167
 168         /* SOR lane sequencer */
 169         if (pu) {
 170                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 171                         LANE_SEQ_CTL_SEQUENCE_DOWN |
 172                         LANE_SEQ_CTL_NEW_POWER_STATE_PU;
 173         } else {
 174                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 175                         LANE_SEQ_CTL_SEQUENCE_UP |
 176                         LANE_SEQ_CTL_NEW_POWER_STATE_PD;
 177         }
 178
 179         if (is_lvds)
 180                 reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
 181         else
 182                 reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
 183
 184         tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
 185
 186         if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
 187                                        LANE_SEQ_CTL_SETTING_MASK,
 188                                        LANE_SEQ_CTL_SETTING_NEW_DONE,
 189                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 190                 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
 191                 return -1;
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
 198                                       u32 lane_count, int pu)
 199 {
 200         u32 reg_val;
 201
 202         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 203
 204         if (pu) {
 205                 switch (lane_count) {
 206                 case 4:
 207                         reg_val |= (DP_PADCTL_PD_TXD_3_NO |
 208                                 DP_PADCTL_PD_TXD_2_NO);
 209                         /* fall through */
 210                 case 2:
 211                         reg_val |= DP_PADCTL_PD_TXD_1_NO;
 212                 case 1:
 213                         reg_val |= DP_PADCTL_PD_TXD_0_NO;
 214                         break;
 215                 default:
 216                         debug("dp: invalid lane number %d\n", lane_count);
 217                         return -1;
 218                 }
 219
 220                 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 221                 tegra_dc_sor_set_lane_count(sor, lane_count);
 222         }
 223
 224         return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
 225 }
 226
 227 void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
 228                                   int power_up)
 229 {
 230         u32 reg_val;
 231
 232         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 233
 234         if (power_up)
 235                 reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
 236         else
 237                 reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
 238
 239         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 240 }
 241
 242 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 243                                     u32 pwm_dutycycle)
 244 {
 245         tegra_sor_writel(sor, PWM_DIV, pwm_div);
 246         tegra_sor_writel(sor, PWM_CTL,
 247                          (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
 248                          PWM_CTL_SETTING_NEW_TRIGGER);
 249
 250         if (tegra_dc_sor_poll_register(sor, PWM_CTL,
 251                                        PWM_CTL_SETTING_NEW_SHIFT,
 252                                        PWM_CTL_SETTING_NEW_DONE,
 253                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 254                 debug("dp: timeout while waiting for SOR PWM setting\n");
 255         }
 256 }
 257
 258 static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
 259                                 const struct tegra_dp_link_config *link_cfg)
 260 {
 261         u32 reg_val;
 262
 263         tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
 264
 265         tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
 266         reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
 267         reg_val &= ~DP_CONFIG_WATERMARK_MASK;
 268         reg_val |= link_cfg->watermark;
 269         reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
 270         reg_val |= (link_cfg->active_count <<
 271                 DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
 272         reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
 273         reg_val |= (link_cfg->active_frac <<
 274                 DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
 275         if (link_cfg->activepolarity)
 276                 reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 277         else
 278                 reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 279         reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
 280                 DP_CONFIG_RD_RESET_VAL_NEGATIVE);
 281
 282         tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
 283
 284         /* program h/vblank sym */
 285         tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
 286                               DP_AUDIO_HBLANK_SYMBOLS_MASK,
 287                               link_cfg->hblank_sym);
 288
 289         tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
 290                               DP_AUDIO_VBLANK_SYMBOLS_MASK,
 291                               link_cfg->vblank_sym);
 292 }
 293
 294 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 295 {
 296         tegra_sor_writel(sor, SUPER_STATE0, 0);
 297         tegra_sor_writel(sor, SUPER_STATE0, 1);
 298         tegra_sor_writel(sor, SUPER_STATE0, 0);
 299 }
 300
 301 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 302 {
 303         tegra_sor_writel(sor, STATE0, 0);
 304         tegra_sor_writel(sor, STATE0, 1);
 305         tegra_sor_writel(sor, STATE0, 0);
 306 }
 307
 308 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
 309 {
 310         u32 reg_val;
 311         void *pmc_base = sor->pmc_base;
 312
 313         if (up) {
 314                 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
 315                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 316                 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
 317         }
 318
 319         reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 320         reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
 321                         APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
 322
 323         reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
 324                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
 325                         APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
 326                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
 327
 328         writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 329
 330         /* Polling */
 331         u32 temp = 10 * 1000;
 332         do {
 333                 udelay(20);
 334                 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
 335                 if (temp > 20)
 336                         temp -= 20;
 337                 else
 338                         break;
 339         } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
 340
 341         if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
 342                 debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
 343                 return -EIO;
 344         }
 345
 346         if (up) {
 347                 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
 348                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 349         }
 350
 351         return 0;
 352 }
 353
 354 void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
 355 {
 356         u32 reg_val;
 357
 358         reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
 359         if (is_int)
 360                 reg_val |= DP_SPARE_PANEL_INTERNAL;
 361         else
 362                 reg_val &= ~DP_SPARE_PANEL_INTERNAL;
 363
 364         reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
 365                 DP_SPARE_SEQ_ENABLE_YES;
 366         tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
 367 }
 368
 369 void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
 370                                    u8 *lane_count)
 371 {
 372         u32 reg_val;
 373
 374         reg_val = tegra_sor_readl(sor, CLK_CNTRL);
 375         *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
 376                 >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
 377         reg_val = tegra_sor_readl(sor,
 378                 DP_LINKCTL(sor->portnum));
 379
 380         switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
 381         case DP_LINKCTL_LANECOUNT_ZERO:
 382                 *lane_count = 0;
 383                 break;
 384         case DP_LINKCTL_LANECOUNT_ONE:
 385                 *lane_count = 1;
 386                 break;
 387         case DP_LINKCTL_LANECOUNT_TWO:
 388                 *lane_count = 2;
 389                 break;
 390         case DP_LINKCTL_LANECOUNT_FOUR:
 391                 *lane_count = 4;
 392                 break;
 393         default:
 394                 printf("Unknown lane count\n");
 395         }
 396 }
 397
 398 void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
 399 {
 400         tegra_sor_write_field(sor, CLK_CNTRL,
 401                               CLK_CNTRL_DP_LINK_SPEED_MASK,
 402                               link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
 403 }
 404
 405 void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
 406 {
 407         u32 reg_val;
 408
 409         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 410         reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
 411         switch (lane_count) {
 412         case 0:
 413                 break;
 414         case 1:
 415                 reg_val |= DP_LINKCTL_LANECOUNT_ONE;
 416                 break;
 417         case 2:
 418                 reg_val |= DP_LINKCTL_LANECOUNT_TWO;
 419                 break;
 420         case 4:
 421                 reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
 422                 break;
 423         default:
 424                 /* 0 should be handled earlier. */
 425                 printf("dp: Invalid lane count %d\n", lane_count);
 426                 return;
 427         }
 428         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 429 }
 430
 431 /*
 432  * The SOR power sequencer does not work for t124 so SW has to
 433  *  go through the power sequence manually
 434  * Power up steps from spec:
 435  * STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL
 436  * 1    1       1       1       1       1       1       1
 437  * 2    1       1       1       1       1       0       1
 438  * 3    1       1       0       1       1       0       1
 439  * 4    1       0       0       0       0       0       1
 440  * 5    0       0       0       0       0       0       1
 441  */
 442 static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
 443 {
 444         int ret;
 445
 446         if (sor->power_is_up)
 447                 return 0;
 448
 449         /* Set link bw */
 450         tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
 451                                         CLK_CNTRL_DP_LINK_SPEED_LVDS :
 452                                         CLK_CNTRL_DP_LINK_SPEED_G1_62);
 453
 454         /* step 1 */
 455         tegra_sor_write_field(sor, PLL2,
 456                               PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
 457                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
 458                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
 459                               PLL2_AUX7_PORT_POWERDOWN_ENABLE |
 460                               PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
 461                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
 462         tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
 463                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 464                               PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
 465         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 466                               DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
 467                               DP_PADCTL_PAD_CAL_PD_POWERDOWN);
 468
 469         /* step 2 */
 470         ret = tegra_dc_sor_io_set_dpd(sor, 1);
 471         if (ret)
 472                 return ret;
 473         udelay(15);
 474
 475         /* step 3 */
 476         tegra_sor_write_field(sor, PLL2,
 477                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 478                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 479         udelay(25);
 480
 481         /* step 4 */
 482         tegra_sor_write_field(sor, PLL0,
 483                               PLL0_PWR_MASK | /* PDPLL */
 484                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 485                               PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 486         /* PLLCAPD */
 487         tegra_sor_write_field(sor, PLL2,
 488                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 489                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 490         udelay(225);
 491
 492         /* step 5 PDPORT */
 493         tegra_sor_write_field(sor, PLL2,
 494                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 495                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 496
 497         sor->power_is_up = 1;
 498
 499         return 0;
 500 }
 501
 502 #if DEBUG_SOR
 503 static void dump_sor_reg(struct tegra_dc_sor_data *sor)
 504 {
 505 #define DUMP_REG(a) printk(BIOS_INFO, "%-32s  %03x  %08x\n",            \
 506                 #a, a, tegra_sor_readl(sor, a));
 507
 508         DUMP_REG(SUPER_STATE0);
 509         DUMP_REG(SUPER_STATE1);
 510         DUMP_REG(STATE0);
 511         DUMP_REG(STATE1);
 512         DUMP_REG(NV_HEAD_STATE0(0));
 513         DUMP_REG(NV_HEAD_STATE0(1));
 514         DUMP_REG(NV_HEAD_STATE1(0));
 515         DUMP_REG(NV_HEAD_STATE1(1));
 516         DUMP_REG(NV_HEAD_STATE2(0));
 517         DUMP_REG(NV_HEAD_STATE2(1));
 518         DUMP_REG(NV_HEAD_STATE3(0));
 519         DUMP_REG(NV_HEAD_STATE3(1));
 520         DUMP_REG(NV_HEAD_STATE4(0));
 521         DUMP_REG(NV_HEAD_STATE4(1));
 522         DUMP_REG(NV_HEAD_STATE5(0));
 523         DUMP_REG(NV_HEAD_STATE5(1));
 524         DUMP_REG(CRC_CNTRL);
 525         DUMP_REG(CLK_CNTRL);
 526         DUMP_REG(CAP);
 527         DUMP_REG(PWR);
 528         DUMP_REG(TEST);
 529         DUMP_REG(PLL0);
 530         DUMP_REG(PLL1);
 531         DUMP_REG(PLL2);
 532         DUMP_REG(PLL3);
 533         DUMP_REG(CSTM);
 534         DUMP_REG(LVDS);
 535         DUMP_REG(CRCA);
 536         DUMP_REG(CRCB);
 537         DUMP_REG(SEQ_CTL);
 538         DUMP_REG(LANE_SEQ_CTL);
 539         DUMP_REG(SEQ_INST(0));
 540         DUMP_REG(SEQ_INST(1));
 541         DUMP_REG(SEQ_INST(2));
 542         DUMP_REG(SEQ_INST(3));
 543         DUMP_REG(SEQ_INST(4));
 544         DUMP_REG(SEQ_INST(5));
 545         DUMP_REG(SEQ_INST(6));
 546         DUMP_REG(SEQ_INST(7));
 547         DUMP_REG(SEQ_INST(8));
 548         DUMP_REG(PWM_DIV);
 549         DUMP_REG(PWM_CTL);
 550         DUMP_REG(MSCHECK);
 551         DUMP_REG(XBAR_CTRL);
 552         DUMP_REG(DP_LINKCTL(0));
 553         DUMP_REG(DP_LINKCTL(1));
 554         DUMP_REG(DC(0));
 555         DUMP_REG(DC(1));
 556         DUMP_REG(LANE_DRIVE_CURRENT(0));
 557         DUMP_REG(PR(0));
 558         DUMP_REG(LANE4_PREEMPHASIS(0));
 559         DUMP_REG(POSTCURSOR(0));
 560         DUMP_REG(DP_CONFIG(0));
 561         DUMP_REG(DP_CONFIG(1));
 562         DUMP_REG(DP_MN(0));
 563         DUMP_REG(DP_MN(1));
 564         DUMP_REG(DP_PADCTL(0));
 565         DUMP_REG(DP_PADCTL(1));
 566         DUMP_REG(DP_DEBUG(0));
 567         DUMP_REG(DP_DEBUG(1));
 568         DUMP_REG(DP_SPARE(0));
 569         DUMP_REG(DP_SPARE(1));
 570         DUMP_REG(DP_TPG);
 571
 572         return;
 573 }
 574 #endif
 575
 576 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
 577                         int is_lvds,
 578                         const struct tegra_dp_link_config *link_cfg,
 579                         const struct display_timing *timing)
 580 {
 581         const int       head_num = 0;
 582         u32             reg_val  = STATE1_ASY_OWNER_HEAD0 << head_num;
 583         u32             vtotal, htotal;
 584         u32             vsync_end, hsync_end;
 585         u32             vblank_end, hblank_end;
 586         u32             vblank_start, hblank_start;
 587
 588         reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
 589                 STATE1_ASY_PROTOCOL_DP_A;
 590         reg_val |= STATE1_ASY_SUBOWNER_NONE |
 591                 STATE1_ASY_CRCMODE_COMPLETE_RASTER;
 592
 593         reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
 594         reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
 595         reg_val |= (link_cfg->bits_per_pixel > 18) ?
 596                 STATE1_ASY_PIXELDEPTH_BPP_24_444 :
 597                 STATE1_ASY_PIXELDEPTH_BPP_18_444;
 598
 599         tegra_sor_writel(sor, STATE1, reg_val);
 600
 601         /*
 602          * Skipping programming NV_HEAD_STATE0, assuming:
 603          * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
 604          */
 605         vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
 606                 timing->vactive.typ + timing->vfront_porch.typ;
 607         htotal = timing->hsync_len.typ + timing->hback_porch.typ +
 608                 timing->hactive.typ + timing->hfront_porch.typ;
 609
 610         tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
 611                          vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
 612                          htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
 613
 614         vsync_end = timing->vsync_len.typ - 1;
 615         hsync_end = timing->hsync_len.typ - 1;
 616         tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
 617                          vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
 618                          hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
 619
 620         vblank_end = vsync_end + timing->vback_porch.typ;
 621         hblank_end = hsync_end + timing->hback_porch.typ;
 622         tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
 623                          vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
 624                          hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
 625
 626         vblank_start = vblank_end + timing->vactive.typ;
 627         hblank_start = hblank_end + timing->hactive.typ;
 628         tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
 629                          vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
 630                          hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
 631
 632         /* TODO: adding interlace mode support */
 633         tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
 634
 635         tegra_sor_write_field(sor, CSTM,
 636                               CSTM_ROTCLK_DEFAULT_MASK |
 637                               CSTM_LVDS_EN_ENABLE,
 638                               2 << CSTM_ROTCLK_SHIFT |
 639                               is_lvds ? CSTM_LVDS_EN_ENABLE :
 640                               CSTM_LVDS_EN_DISABLE);
 641
 642          tegra_dc_sor_config_pwm(sor, 1024, 1024);
 643 }
 644
 645 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
 646 {
 647         u32 reg_val = readl(&disp_ctrl->cmd.state_access);
 648
 649         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 650         writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
 651
 652         /* Enable DC now - otherwise pure text console may not show. */
 653         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 654                &disp_ctrl->cmd.disp_cmd);
 655         writel(reg_val, &disp_ctrl->cmd.state_access);
 656 }
 657
 658 int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
 659                            const struct tegra_dp_link_config *link_cfg)
 660 {
 661         int ret;
 662
 663         tegra_sor_write_field(sor, CLK_CNTRL,
 664                               CLK_CNTRL_DP_CLK_SEL_MASK,
 665                               CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 666
 667         tegra_sor_write_field(sor, PLL2,
 668                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 669                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 670         udelay(25);
 671
 672         tegra_sor_write_field(sor, PLL3,
 673                               PLL3_PLLVDD_MODE_MASK,
 674                               PLL3_PLLVDD_MODE_V3_3);
 675         tegra_sor_writel(sor, PLL0,
 676                          0xf << PLL0_ICHPMP_SHFIT |
 677                          0x3 << PLL0_VCOCAP_SHIFT |
 678                          PLL0_PLLREG_LEVEL_V45 |
 679                          PLL0_RESISTORSEL_EXT |
 680                          PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 681         tegra_sor_write_field(sor, PLL2,
 682                               PLL2_AUX1_SEQ_MASK |
 683                               PLL2_AUX9_LVDSEN_OVERRIDE |
 684                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 685                               PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
 686                               PLL2_AUX9_LVDSEN_OVERRIDE |
 687                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 688         tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
 689                          PLL1_TMDS_TERM_ENABLE);
 690
 691         if (tegra_dc_sor_poll_register(sor, PLL2,
 692                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 693                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
 694                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 695                 printf("DP failed to lock PLL\n");
 696                 return -EIO;
 697         }
 698
 699         tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
 700                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 701                               PLL2_AUX2_OVERRIDE_POWERDOWN |
 702                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 703
 704         ret = tegra_dc_sor_power_up(sor, 0);
 705         if (ret) {
 706                 debug("DP failed to power up\n");
 707                 return ret;
 708         }
 709
 710         /* re-enable SOR clock */
 711         clock_sor_enable_edp_clock();
 712
 713         /* Power up lanes */
 714         tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
 715
 716         tegra_dc_sor_set_dp_mode(sor, link_cfg);
 717         debug("%s ret\n", __func__);
 718
 719         return 0;
 720 }
 721
 722 int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
 723                         const struct tegra_dp_link_config *link_cfg,
 724                         const struct display_timing *timing)
 725 {
 726         const void *blob = gd->fdt_blob;
 727         struct dc_ctlr *disp_ctrl;
 728         u32 reg_val;
 729         int node;
 730
 731         /* Use the first display controller */
 732         debug("%s\n", __func__);
 733         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
 734         if (node < 0)
 735                 return -ENOENT;
 736         disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
 737
 738         tegra_dc_sor_enable_dc(disp_ctrl);
 739         tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
 740
 741         writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
 742         writel(0x9f, &disp_ctrl->cmd.state_ctrl);
 743
 744         writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 745                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
 746                &disp_ctrl->cmd.disp_pow_ctrl);
 747
 748         reg_val = tegra_sor_readl(sor, TEST);
 749         if (reg_val & TEST_ATTACHED_TRUE)
 750                 return -EEXIST;
 751
 752         tegra_sor_writel(sor, SUPER_STATE1,
 753                          SUPER_STATE1_ATTACHED_NO);
 754
 755         /*
 756          * Enable display2sor clock at least 2 cycles before DC start,
 757          * to clear sor internal valid signal.
 758          */
 759         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 760         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 761         writel(0, &disp_ctrl->disp.disp_win_opt);
 762         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 763
 764         /* Attach head */
 765         tegra_dc_sor_update(sor);
 766         tegra_sor_writel(sor, SUPER_STATE1,
 767                          SUPER_STATE1_ATTACHED_YES);
 768         tegra_sor_writel(sor, SUPER_STATE1,
 769                          SUPER_STATE1_ATTACHED_YES |
 770                          SUPER_STATE1_ASY_HEAD_OP_AWAKE |
 771                          SUPER_STATE1_ASY_ORMODE_NORMAL);
 772         tegra_dc_sor_super_update(sor);
 773
 774         /* Enable dc */
 775         reg_val = readl(&disp_ctrl->cmd.state_access);
 776         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 777         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 778                &disp_ctrl->cmd.disp_cmd);
 779         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 780         writel(reg_val, &disp_ctrl->cmd.state_access);
 781
 782         if (tegra_dc_sor_poll_register(sor, TEST,
 783                                        TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
 784                                        TEST_ACT_HEAD_OPMODE_AWAKE,
 785                                        100,
 786                                        TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
 787                 printf("dc timeout waiting for OPMOD = AWAKE\n");
 788                 return -ETIMEDOUT;
 789         } else {
 790                 debug("%s: sor is attached\n", __func__);
 791         }
 792
 793 #if DEBUG_SOR
 794         dump_sor_reg(sor);
 795 #endif
 796         debug("%s: ret=%d\n", __func__, 0);
 797
 798         return 0;
 799 }
 800
 801 void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
 802                 const struct tegra_dp_link_config *link_cfg)
 803 {
 804         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
 805                          link_cfg->drive_current);
 806         tegra_sor_writel(sor, PR(sor->portnum),
 807                          link_cfg->preemphasis);
 808         tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
 809                          link_cfg->postcursor);
 810         tegra_sor_writel(sor, LVDS, 0);
 811
 812         tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
 813         tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
 814
 815         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 816                               DP_PADCTL_TX_PU_ENABLE |
 817                               DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
 818                               DP_PADCTL_TX_PU_ENABLE |
 819                               2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
 820
 821         /* Precharge */
 822         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
 823         udelay(20);
 824
 825         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
 826 }
 827
 828 int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
 829                                     const struct tegra_dp_link_config *link_cfg)
 830 {
 831         u32 drive_current = 0;
 832         u32 pre_emphasis = 0;
 833
 834         /* Set to a known-good pre-calibrated setting */
 835         switch (link_cfg->link_bw) {
 836         case SOR_LINK_SPEED_G1_62:
 837         case SOR_LINK_SPEED_G2_7:
 838                 drive_current = 0x13131313;
 839                 pre_emphasis = 0;
 840                 break;
 841         case SOR_LINK_SPEED_G5_4:
 842                 debug("T124 does not support 5.4G link clock.\n");
 843         default:
 844                 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
 845                 return -ENOLINK;
 846         }
 847
 848         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);
 849         tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
 850
 851         return 0;
 852 }
 853
 854 void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
 855                         const struct tegra_dp_link_config *link_cfg)
 856 {
 857         u32 pad_ctrl = 0;
 858         int err = 0;
 859
 860         switch (link_cfg->lane_count) {
 861         case 4:
 862                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 863                         DP_PADCTL_PD_TXD_1_NO |
 864                         DP_PADCTL_PD_TXD_2_NO |
 865                         DP_PADCTL_PD_TXD_3_NO;
 866                 break;
 867         case 2:
 868                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 869                         DP_PADCTL_PD_TXD_1_NO |
 870                         DP_PADCTL_PD_TXD_2_YES |
 871                         DP_PADCTL_PD_TXD_3_YES;
 872                 break;
 873         case 1:
 874                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 875                         DP_PADCTL_PD_TXD_1_YES |
 876                         DP_PADCTL_PD_TXD_2_YES |
 877                         DP_PADCTL_PD_TXD_3_YES;
 878                 break;
 879         default:
 880                 printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
 881                 return;
 882         }
 883
 884         pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
 885         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
 886
 887         err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
 888         if (err) {
 889                 debug("Wait for lane power down failed: %d\n", err);
 890                 return;
 891         }
 892 }
 893
 894 int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor,
 895                               const struct tegra_dp_link_config *cfg)
 896 {
 897         u32 val = 0;
 898
 899         switch (cfg->lane_count) {
 900         case 4:
 901                 val |= (DP_PADCTL_PD_TXD_3_NO |
 902                         DP_PADCTL_PD_TXD_2_NO);
 903                 /* fall through */
 904         case 2:
 905                 val |= DP_PADCTL_PD_TXD_1_NO;
 906                 /* fall through */
 907         case 1:
 908                 val |= DP_PADCTL_PD_TXD_0_NO;
 909                 break;
 910         default:
 911                 debug("dp: invalid lane number %d\n", cfg->lane_count);
 912                 return -EINVAL;
 913         }
 914
 915         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 916                               (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
 917                               (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
 918         udelay(100);
 919         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 920                               (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
 921                               0);
 922
 923         return 0;
 924 }
 925
 926 static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)
 927 {
 928         u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);
 929
 930         reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;
 931         writel(reg_val, &disp_ctrl->disp.disp_win_opt);
 932 }
 933
 934 int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
 935 {
 936         int dc_reg_ctx[DC_REG_SAVE_SPACE];
 937         const void *blob = gd->fdt_blob;
 938         struct dc_ctlr *disp_ctrl;
 939         unsigned long dc_int_mask;
 940         int node;
 941         int ret;
 942
 943         debug("%s\n", __func__);
 944         /* Use the first display controller */
 945         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
 946         if (node < 0) {
 947                 ret = -ENOENT;
 948                 goto err;
 949         }
 950         disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
 951
 952         /* Sleep mode */
 953         tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
 954                          SUPER_STATE1_ASY_ORMODE_SAFE |
 955                          SUPER_STATE1_ATTACHED_YES);
 956         tegra_dc_sor_super_update(sor);
 957
 958         tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
 959
 960         if (tegra_dc_sor_poll_register(sor, TEST,
 961                                        TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
 962                                        TEST_ACT_HEAD_OPMODE_SLEEP, 100,
 963                                        TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
 964                 debug("dc timeout waiting for OPMOD = SLEEP\n");
 965                 ret = -ETIMEDOUT;
 966                 goto err;
 967         }
 968
 969         tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
 970                          SUPER_STATE1_ASY_ORMODE_SAFE |
 971                          SUPER_STATE1_ATTACHED_NO);
 972
 973         /* Mask DC interrupts during the 2 dummy frames required for detach */
 974         dc_int_mask = readl(&disp_ctrl->cmd.int_mask);
 975         writel(0, &disp_ctrl->cmd.int_mask);
 976
 977         /* Stop DC->SOR path */
 978         tegra_dc_sor_enable_sor(disp_ctrl, false);
 979         ret = tegra_dc_sor_general_act(disp_ctrl);
 980         if (ret)
 981                 goto err;
 982
 983         /* Stop DC */
 984         writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);
 985         ret = tegra_dc_sor_general_act(disp_ctrl);
 986         if (ret)
 987                 goto err;
 988
 989         tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
 990
 991         writel(dc_int_mask, &disp_ctrl->cmd.int_mask);
 992
 993         return 0;
 994 err:
 995         debug("%s: ret=%d\n", __func__, ret);
 996
 997         return ret;
 998 }
 999
1000 int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
1001 {
1002         const void *blob = gd->fdt_blob;
1003         struct tegra_dc_sor_data *sor;
1004         int node;
1005
1006         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
1007         if (node < 0)
1008                 return -ENOENT;
1009         sor = calloc(1, sizeof(*sor));
1010         if (!sor)
1011                 return -ENOMEM;
1012         sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
1013
1014         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
1015         if (node < 0)
1016                 return -ENOENT;
1017         sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
1018
1019         sor->power_is_up = 0;
1020         sor->portnum = 0;
1021         *sorp = sor;
1022
1023         return 0;
1024 }