drivers/video/tegra124/display.c

   1 /*
   2  * Copyright 2014 Google Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Extracted from Chromium coreboot commit 3f59b13d
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <edid.h>
  12 #include <errno.h>
  13 #include <display.h>
  14 #include <edid.h>
  15 #include <fdtdec.h>
  16 #include <lcd.h>
  17 #include <asm/gpio.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/pwm.h>
  21 #include <asm/arch-tegra/dc.h>
  22 #include "displayport.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* return in 1000ths of a Hertz */
  27 static int tegra_dc_calc_refresh(const struct display_timing *timing)
  28 {
  29         int h_total, v_total, refresh;
  30         int pclk = timing->pixelclock.typ;
  31
  32         h_total = timing->hactive.typ + timing->hfront_porch.typ +
  33                         timing->hback_porch.typ + timing->hsync_len.typ;
  34         v_total = timing->vactive.typ + timing->vfront_porch.typ +
  35                         timing->vback_porch.typ + timing->vsync_len.typ;
  36         if (!pclk || !h_total || !v_total)
  37                 return 0;
  38         refresh = pclk / h_total;
  39         refresh *= 1000;
  40         refresh /= v_total;
  41
  42         return refresh;
  43 }
  44
  45 static void print_mode(const struct display_timing *timing)
  46 {
  47         int refresh = tegra_dc_calc_refresh(timing);
  48
  49         debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
  50               timing->hactive.typ, timing->vactive.typ, refresh / 1000,
  51               refresh % 1000, timing->pixelclock.typ);
  52 }
  53
  54 static int update_display_mode(struct dc_ctlr *disp_ctrl,
  55                                const struct display_timing *timing,
  56                                int href_to_sync, int vref_to_sync)
  57 {
  58         print_mode(timing);
  59
  60         writel(0x1, &disp_ctrl->disp.disp_timing_opt);
  61
  62         writel(vref_to_sync << 16 | href_to_sync,
  63                &disp_ctrl->disp.ref_to_sync);
  64
  65         writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
  66                &disp_ctrl->disp.sync_width);
  67
  68         writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
  69                 timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
  70
  71         writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
  72                 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
  73
  74         writel(timing->hactive.typ | (timing->vactive.typ << 16),
  75                &disp_ctrl->disp.disp_active);
  76
  77         /**
  78          * We want to use PLLD_out0, which is PLLD / 2:
  79          *   PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
  80          *
  81          * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
  82          * has some requirements to have VCO in range 500MHz~1000MHz (see
  83          * clock.c for more detail). To simplify calculation, we set
  84          * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
  85          * may be calculated by clock_display, to allow wider frequency range.
  86          *
  87          * Note ShiftClockDiv is a 7.1 format value.
  88          */
  89         const u32 shift_clock_div = 1;
  90         writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
  91                ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
  92                &disp_ctrl->disp.disp_clk_ctrl);
  93         debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
  94               timing->pixelclock.typ, shift_clock_div);
  95         return 0;
  96 }
  97
  98 static u32 tegra_dc_poll_register(void *reg,
  99         u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
 100 {
 101         u32 temp = timeout_us;
 102         u32 reg_val = 0;
 103
 104         do {
 105                 udelay(poll_interval_us);
 106                 reg_val = readl(reg);
 107                 if (timeout_us > poll_interval_us)
 108                         timeout_us -= poll_interval_us;
 109                 else
 110                         break;
 111         } while ((reg_val & mask) != exp_val);
 112
 113         if ((reg_val & mask) == exp_val)
 114                 return 0;       /* success */
 115
 116         return temp;
 117 }
 118
 119 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
 120 {
 121         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 122
 123         if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
 124                                    GENERAL_ACT_REQ, 0, 100,
 125                                    DC_POLL_TIMEOUT_MS * 1000)) {
 126                 debug("dc timeout waiting for DC to stop\n");
 127                 return -ETIMEDOUT;
 128         }
 129
 130         return 0;
 131 }
 132
 133 static struct display_timing min_mode = {
 134         .hsync_len = { .typ = 1 },
 135         .vsync_len = { .typ = 1 },
 136         .hback_porch = { .typ = 20 },
 137         .vback_porch = { .typ = 0 },
 138         .hactive = { .typ = 16 },
 139         .vactive = { .typ = 16 },
 140         .hfront_porch = { .typ = 1 },
 141         .vfront_porch = { .typ = 2 },
 142 };
 143
 144 /* Disable windows and set minimum raster timings */
 145 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
 146                                            int *dc_reg_ctx)
 147 {
 148         const int href_to_sync = 0, vref_to_sync = 1;
 149         int selected_windows, i;
 150
 151         selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
 152
 153         /* Store and clear window options */
 154         for (i = 0; i < DC_N_WINDOWS; ++i) {
 155                 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
 156                 dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
 157                 writel(0, &disp_ctrl->win.win_opt);
 158                 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
 159         }
 160
 161         writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
 162
 163         /* Store current raster timings and set minimum timings */
 164         dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
 165         writel(href_to_sync | (vref_to_sync << 16),
 166                &disp_ctrl->disp.ref_to_sync);
 167
 168         dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
 169         writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
 170                &disp_ctrl->disp.sync_width);
 171
 172         dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
 173         writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
 174                &disp_ctrl->disp.back_porch);
 175
 176         dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
 177         writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
 178                &disp_ctrl->disp.front_porch);
 179
 180         dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
 181         writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
 182                &disp_ctrl->disp.disp_active);
 183
 184         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 185 }
 186
 187 /* Restore previous windows status and raster timings */
 188 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
 189                                          int *dc_reg_ctx)
 190 {
 191         int selected_windows, i;
 192
 193         selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
 194
 195         for (i = 0; i < DC_N_WINDOWS; ++i) {
 196                 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
 197                 writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
 198                 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
 199         }
 200
 201         writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
 202
 203         writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
 204         writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
 205         writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
 206         writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
 207         writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
 208
 209         writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
 210 }
 211
 212 static int tegra_depth_for_bpp(int bpp)
 213 {
 214         switch (bpp) {
 215         case 32:
 216                 return COLOR_DEPTH_R8G8B8A8;
 217         case 16:
 218                 return COLOR_DEPTH_B5G6R5;
 219         default:
 220                 debug("Unsupported LCD bit depth");
 221                 return -1;
 222         }
 223 }
 224
 225 static int update_window(struct dc_ctlr *disp_ctrl,
 226                          u32 frame_buffer, int fb_bits_per_pixel,
 227                          const struct display_timing *timing)
 228 {
 229         const u32 colour_white = 0xffffff;
 230         int colour_depth;
 231         u32 val;
 232
 233         writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
 234
 235         writel(((timing->vactive.typ << 16) | timing->hactive.typ),
 236                &disp_ctrl->win.size);
 237         writel(((timing->vactive.typ << 16) |
 238                 (timing->hactive.typ * fb_bits_per_pixel / 8)),
 239                 &disp_ctrl->win.prescaled_size);
 240         writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
 241                 32 * 32), &disp_ctrl->win.line_stride);
 242
 243         colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
 244         if (colour_depth == -1)
 245                 return -EINVAL;
 246
 247         writel(colour_depth, &disp_ctrl->win.color_depth);
 248
 249         writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
 250         writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
 251                &disp_ctrl->win.dda_increment);
 252
 253         writel(colour_white, &disp_ctrl->disp.blend_background_color);
 254         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 255                &disp_ctrl->cmd.disp_cmd);
 256
 257         writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 258
 259         val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 260         val |= GENERAL_UPDATE | WIN_A_UPDATE;
 261         writel(val, &disp_ctrl->cmd.state_ctrl);
 262
 263         /* Enable win_a */
 264         val = readl(&disp_ctrl->win.win_opt);
 265         writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
 266
 267         return 0;
 268 }
 269
 270 static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
 271 {
 272         /* do not accept interrupts during initialization */
 273         writel(0x00000000, &disp_ctrl->cmd.int_mask);
 274         writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
 275                &disp_ctrl->cmd.state_access);
 276         writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
 277         writel(0x00000000, &disp_ctrl->win.win_opt);
 278         writel(0x00000000, &disp_ctrl->win.byte_swap);
 279         writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
 280
 281         writel(0x00000000, &disp_ctrl->win.pos);
 282         writel(0x00000000, &disp_ctrl->win.h_initial_dda);
 283         writel(0x00000000, &disp_ctrl->win.v_initial_dda);
 284         writel(0x00000000, &disp_ctrl->win.dda_increment);
 285         writel(0x00000000, &disp_ctrl->win.dv_ctrl);
 286
 287         writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
 288         writel(0x00000000, &disp_ctrl->win.blend_match_select);
 289         writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
 290         writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
 291
 292         writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
 293         writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
 294         writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
 295
 296         writel(0x00000000, &disp_ctrl->com.crc_checksum);
 297         writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
 298         writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
 299         writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
 300         writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
 301         writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
 302
 303         return 0;
 304 }
 305
 306 static void dump_config(int panel_bpp, struct display_timing *timing)
 307 {
 308         printf("timing->hactive.typ = %d\n", timing->hactive.typ);
 309         printf("timing->vactive.typ = %d\n", timing->vactive.typ);
 310         printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
 311
 312         printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
 313         printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
 314         printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
 315
 316         printf("timing->vfront_porch.typ  %d\n", timing->vfront_porch.typ);
 317         printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
 318         printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
 319
 320         printf("panel_bits_per_pixel = %d\n", panel_bpp);
 321 }
 322
 323 static int display_update_config_from_edid(struct udevice *dp_dev,
 324                                            int *panel_bppp,
 325                                            struct display_timing *timing)
 326 {
 327         int ret;
 328
 329         ret = display_read_timing(dp_dev, timing);
 330         if (ret)
 331                 return ret;
 332
 333         return 0;
 334 }
 335
 336 /* Somewhat torturous method */
 337 static int get_backlight_info(const void *blob, struct gpio_desc *vdd,
 338                               struct gpio_desc *enable, int *pwmp)
 339 {
 340         int sor, panel, backlight, power;
 341         const u32 *prop;
 342         int len;
 343         int ret;
 344
 345         *pwmp = 0;
 346         sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
 347         if (sor < 0)
 348                 return -ENOENT;
 349         panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel");
 350         if (panel < 0)
 351                 return -ENOENT;
 352         backlight = fdtdec_lookup_phandle(blob, panel, "backlight");
 353         if (backlight < 0)
 354                 return -ENOENT;
 355         ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0,
 356                                          enable, GPIOD_IS_OUT);
 357         if (ret)
 358                 return ret;
 359         prop = fdt_getprop(blob, backlight, "pwms", &len);
 360         if (!prop || len != 3 * sizeof(u32))
 361                 return -EINVAL;
 362         *pwmp = fdt32_to_cpu(prop[1]);
 363
 364         power = fdtdec_lookup_phandle(blob, backlight, "power-supply");
 365         if (power < 0)
 366                 return -ENOENT;
 367         ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd,
 368                                          GPIOD_IS_OUT);
 369         if (ret)
 370                 goto err;
 371
 372         return 0;
 373
 374 err:
 375         dm_gpio_free(NULL, enable);
 376         return ret;
 377 }
 378
 379 static int display_init(void *lcdbase, int fb_bits_per_pixel,
 380                         struct display_timing *timing)
 381 {
 382         struct dc_ctlr *dc_ctlr;
 383         const void *blob = gd->fdt_blob;
 384         struct udevice *dp_dev;
 385         const int href_to_sync = 1, vref_to_sync = 1;
 386         int panel_bpp = 18;     /* default 18 bits per pixel */
 387         u32 plld_rate;
 388         struct gpio_desc vdd_gpio, enable_gpio;
 389         int pwm;
 390         int node;
 391         int ret;
 392
 393         ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
 394         if (ret)
 395                 return ret;
 396
 397         node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
 398         if (node < 0)
 399                 return -ENOENT;
 400         dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
 401         if (fdtdec_decode_display_timing(blob, node, 0, timing))
 402                 return -EINVAL;
 403
 404         ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
 405         if (ret) {
 406                 debug("%s: Failed to decode EDID, using defaults\n", __func__);
 407                 dump_config(panel_bpp, timing);
 408         }
 409
 410         if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) {
 411                 dm_gpio_set_value(&vdd_gpio, 1);
 412                 debug("%s: backlight vdd setting gpio %08x to %d\n",
 413                       __func__, gpio_get_number(&vdd_gpio), 1);
 414         }
 415
 416         /*
 417          * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
 418          * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
 419          * update_display_mode() for detail.
 420          */
 421         plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
 422         if (plld_rate == 0) {
 423                 printf("dc: clock init failed\n");
 424                 return -EIO;
 425         } else if (plld_rate != timing->pixelclock.typ * 2) {
 426                 debug("dc: plld rounded to %u\n", plld_rate);
 427                 timing->pixelclock.typ = plld_rate / 2;
 428         }
 429
 430         /* Init dc */
 431         ret = tegra_dc_init(dc_ctlr);
 432         if (ret) {
 433                 debug("dc: init failed\n");
 434                 return ret;
 435         }
 436
 437         /* Configure dc mode */
 438         ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
 439         if (ret) {
 440                 debug("dc: failed to configure display mode\n");
 441                 return ret;
 442         }
 443
 444         /* Enable dp */
 445         ret = display_enable(dp_dev, panel_bpp, timing);
 446         if (ret)
 447                 return ret;
 448
 449         ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
 450         if (ret)
 451                 return ret;
 452
 453         /* Set up Tegra PWM to drive the panel backlight */
 454         pwm_enable(pwm, 0, 220, 0x2e);
 455         udelay(10 * 1000);
 456
 457         if (dm_gpio_is_valid(&enable_gpio)) {
 458                 dm_gpio_set_value(&enable_gpio, 1);
 459                 debug("%s: backlight enable setting gpio %08x to %d\n",
 460                       __func__, gpio_get_number(&enable_gpio), 1);
 461         }
 462
 463         return 0;
 464 }
 465
 466 enum {
 467         /* Maximum LCD size we support */
 468         LCD_MAX_WIDTH           = 1920,
 469         LCD_MAX_HEIGHT          = 1200,
 470         LCD_MAX_LOG2_BPP        = 4,            /* 2^4 = 16 bpp */
 471 };
 472
 473 vidinfo_t panel_info = {
 474         /* Insert a value here so that we don't end up in the BSS */
 475         .vl_col = -1,
 476 };
 477
 478 int tegra_lcd_check_next_stage(const void *blob, int wait)
 479 {
 480         return 0;
 481 }
 482
 483 void tegra_lcd_early_init(const void *blob)
 484 {
 485         /*
 486          * Go with the maximum size for now. We will fix this up after
 487          * relocation. These values are only used for memory alocation.
 488          */
 489         panel_info.vl_col = LCD_MAX_WIDTH;
 490         panel_info.vl_row = LCD_MAX_HEIGHT;
 491         panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
 492 }
 493
 494 static int tegra124_lcd_init(void *lcdbase)
 495 {
 496         struct display_timing timing;
 497         int ret;
 498
 499         clock_set_up_plldp();
 500         clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
 501
 502         clock_enable(PERIPH_ID_HOST1X);
 503         clock_enable(PERIPH_ID_DISP1);
 504         clock_enable(PERIPH_ID_PWM);
 505         clock_enable(PERIPH_ID_DPAUX);
 506         clock_enable(PERIPH_ID_SOR0);
 507         udelay(2);
 508
 509         reset_set_enable(PERIPH_ID_HOST1X, 0);
 510         reset_set_enable(PERIPH_ID_DISP1, 0);
 511         reset_set_enable(PERIPH_ID_PWM, 0);
 512         reset_set_enable(PERIPH_ID_DPAUX, 0);
 513         reset_set_enable(PERIPH_ID_SOR0, 0);
 514
 515         ret = display_init(lcdbase, 1 << LCD_BPP, &timing);
 516         if (ret)
 517                 return ret;
 518
 519         panel_info.vl_col = roundup(timing.hactive.typ, 16);
 520         panel_info.vl_row = timing.vactive.typ;
 521
 522         lcd_set_flush_dcache(1);
 523
 524         return 0;
 525 }
 526
 527 void lcd_ctrl_init(void *lcdbase)
 528 {
 529         ulong start;
 530         int ret;
 531
 532         start = get_timer(0);
 533         ret = tegra124_lcd_init(lcdbase);
 534         debug("LCD init took %lu ms\n", get_timer(start));
 535         if (ret)
 536                 printf("%s: Error %d\n", __func__, ret);
 537 }
 538
 539 void lcd_enable(void)
 540 {
 541 }