1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Google Inc.
5 * Extracted from Chromium coreboot commit 3f59b13d
20 #include <asm/arch/clock.h>
21 #include <asm/arch/pwm.h>
22 #include <asm/arch-tegra/dc.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/delay.h>
25 #include "displayport.h"
27 /* return in 1000ths of a Hertz */
28 static int tegra_dc_calc_refresh(const struct display_timing *timing)
30 int h_total, v_total, refresh;
31 int pclk = timing->pixelclock.typ;
33 h_total = timing->hactive.typ + timing->hfront_porch.typ +
34 timing->hback_porch.typ + timing->hsync_len.typ;
35 v_total = timing->vactive.typ + timing->vfront_porch.typ +
36 timing->vback_porch.typ + timing->vsync_len.typ;
37 if (!pclk || !h_total || !v_total)
39 refresh = pclk / h_total;
46 static void print_mode(const struct display_timing *timing)
48 int refresh = tegra_dc_calc_refresh(timing);
50 debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
51 timing->hactive.typ, timing->vactive.typ, refresh / 1000,
52 refresh % 1000, timing->pixelclock.typ);
55 static int update_display_mode(struct dc_ctlr *disp_ctrl,
56 const struct display_timing *timing,
57 int href_to_sync, int vref_to_sync)
61 writel(0x1, &disp_ctrl->disp.disp_timing_opt);
63 writel(vref_to_sync << 16 | href_to_sync,
64 &disp_ctrl->disp.ref_to_sync);
66 writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ,
67 &disp_ctrl->disp.sync_width);
69 writel(((timing->vback_porch.typ - vref_to_sync) << 16) |
70 timing->hback_porch.typ, &disp_ctrl->disp.back_porch);
72 writel(((timing->vfront_porch.typ + vref_to_sync) << 16) |
73 timing->hfront_porch.typ, &disp_ctrl->disp.front_porch);
75 writel(timing->hactive.typ | (timing->vactive.typ << 16),
76 &disp_ctrl->disp.disp_active);
79 * We want to use PLLD_out0, which is PLLD / 2:
80 * PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv.
82 * Currently most panels work inside clock range 50MHz~100MHz, and PLLD
83 * has some requirements to have VCO in range 500MHz~1000MHz (see
84 * clock.c for more detail). To simplify calculation, we set
85 * PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
86 * may be calculated by clock_display, to allow wider frequency range.
88 * Note ShiftClockDiv is a 7.1 format value.
90 const u32 shift_clock_div = 1;
91 writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) |
92 ((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT,
93 &disp_ctrl->disp.disp_clk_ctrl);
94 debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__,
95 timing->pixelclock.typ, shift_clock_div);
99 static u32 tegra_dc_poll_register(void *reg,
100 u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us)
102 u32 temp = timeout_us;
106 udelay(poll_interval_us);
107 reg_val = readl(reg);
108 if (timeout_us > poll_interval_us)
109 timeout_us -= poll_interval_us;
112 } while ((reg_val & mask) != exp_val);
114 if ((reg_val & mask) == exp_val)
115 return 0; /* success */
120 int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl)
122 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
124 if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl,
125 GENERAL_ACT_REQ, 0, 100,
126 DC_POLL_TIMEOUT_MS * 1000)) {
127 debug("dc timeout waiting for DC to stop\n");
134 static struct display_timing min_mode = {
135 .hsync_len = { .typ = 1 },
136 .vsync_len = { .typ = 1 },
137 .hback_porch = { .typ = 20 },
138 .vback_porch = { .typ = 0 },
139 .hactive = { .typ = 16 },
140 .vactive = { .typ = 16 },
141 .hfront_porch = { .typ = 1 },
142 .vfront_porch = { .typ = 2 },
145 /* Disable windows and set minimum raster timings */
146 void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
149 const int href_to_sync = 0, vref_to_sync = 1;
150 int selected_windows, i;
152 selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
154 /* Store and clear window options */
155 for (i = 0; i < DC_N_WINDOWS; ++i) {
156 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
157 dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt);
158 writel(0, &disp_ctrl->win.win_opt);
159 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
162 writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
164 /* Store current raster timings and set minimum timings */
165 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync);
166 writel(href_to_sync | (vref_to_sync << 16),
167 &disp_ctrl->disp.ref_to_sync);
169 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width);
170 writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16),
171 &disp_ctrl->disp.sync_width);
173 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch);
174 writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16),
175 &disp_ctrl->disp.back_porch);
177 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch);
178 writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16),
179 &disp_ctrl->disp.front_porch);
181 dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active);
182 writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16),
183 &disp_ctrl->disp.disp_active);
185 writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
188 /* Restore previous windows status and raster timings */
189 void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
192 int selected_windows, i;
194 selected_windows = readl(&disp_ctrl->cmd.disp_win_header);
196 for (i = 0; i < DC_N_WINDOWS; ++i) {
197 writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header);
198 writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt);
199 writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl);
202 writel(selected_windows, &disp_ctrl->cmd.disp_win_header);
204 writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync);
205 writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width);
206 writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch);
207 writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch);
208 writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active);
210 writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl);
213 static int tegra_depth_for_bpp(int bpp)
217 return COLOR_DEPTH_R8G8B8A8;
219 return COLOR_DEPTH_B5G6R5;
221 debug("Unsupported LCD bit depth");
226 static int update_window(struct dc_ctlr *disp_ctrl,
227 u32 frame_buffer, int fb_bits_per_pixel,
228 const struct display_timing *timing)
230 const u32 colour_white = 0xffffff;
234 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
236 writel(((timing->vactive.typ << 16) | timing->hactive.typ),
237 &disp_ctrl->win.size);
238 writel(((timing->vactive.typ << 16) |
239 (timing->hactive.typ * fb_bits_per_pixel / 8)),
240 &disp_ctrl->win.prescaled_size);
241 writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) /
242 32 * 32), &disp_ctrl->win.line_stride);
244 colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel);
245 if (colour_depth == -1)
248 writel(colour_depth, &disp_ctrl->win.color_depth);
250 writel(frame_buffer, &disp_ctrl->winbuf.start_addr);
251 writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT,
252 &disp_ctrl->win.dda_increment);
254 writel(colour_white, &disp_ctrl->disp.blend_background_color);
255 writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
256 &disp_ctrl->cmd.disp_cmd);
258 writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
260 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
261 val |= GENERAL_UPDATE | WIN_A_UPDATE;
262 writel(val, &disp_ctrl->cmd.state_ctrl);
265 val = readl(&disp_ctrl->win.win_opt);
266 writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
271 static int tegra_dc_init(struct dc_ctlr *disp_ctrl)
273 /* do not accept interrupts during initialization */
274 writel(0x00000000, &disp_ctrl->cmd.int_mask);
275 writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
276 &disp_ctrl->cmd.state_access);
277 writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
278 writel(0x00000000, &disp_ctrl->win.win_opt);
279 writel(0x00000000, &disp_ctrl->win.byte_swap);
280 writel(0x00000000, &disp_ctrl->win.buffer_ctrl);
282 writel(0x00000000, &disp_ctrl->win.pos);
283 writel(0x00000000, &disp_ctrl->win.h_initial_dda);
284 writel(0x00000000, &disp_ctrl->win.v_initial_dda);
285 writel(0x00000000, &disp_ctrl->win.dda_increment);
286 writel(0x00000000, &disp_ctrl->win.dv_ctrl);
288 writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl);
289 writel(0x00000000, &disp_ctrl->win.blend_match_select);
290 writel(0x00000000, &disp_ctrl->win.blend_nomatch_select);
291 writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit);
293 writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi);
294 writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset);
295 writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset);
297 writel(0x00000000, &disp_ctrl->com.crc_checksum);
298 writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]);
299 writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]);
300 writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]);
301 writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]);
302 writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0);
307 static void dump_config(int panel_bpp, struct display_timing *timing)
309 printf("timing->hactive.typ = %d\n", timing->hactive.typ);
310 printf("timing->vactive.typ = %d\n", timing->vactive.typ);
311 printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ);
313 printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ);
314 printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ);
315 printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ);
317 printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ);
318 printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ);
319 printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ);
321 printf("panel_bits_per_pixel = %d\n", panel_bpp);
324 static int display_update_config_from_edid(struct udevice *dp_dev,
326 struct display_timing *timing)
328 return display_read_timing(dp_dev, timing);
331 static int display_init(struct udevice *dev, void *lcdbase,
332 int fb_bits_per_pixel, struct display_timing *timing)
334 struct display_plat *disp_uc_plat;
335 struct dc_ctlr *dc_ctlr;
336 struct udevice *dp_dev;
337 const int href_to_sync = 1, vref_to_sync = 1;
338 int panel_bpp = 18; /* default 18 bits per pixel */
343 * Before we probe the display device (eDP), tell it that this device
344 * is the source of the display data.
346 ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
348 debug("%s: device '%s' display not found (ret=%d)\n", __func__,
353 disp_uc_plat = dev_get_uclass_plat(dp_dev);
354 debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
356 disp_uc_plat->src_dev = dev;
358 ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
360 debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
364 dc_ctlr = (struct dc_ctlr *)dev_read_addr(dev);
365 if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
366 debug("%s: Failed to decode display timing\n", __func__);
370 ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
372 debug("%s: Failed to decode EDID, using defaults\n", __func__);
373 dump_config(panel_bpp, timing);
377 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
378 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
379 * update_display_mode() for detail.
381 plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2);
382 if (plld_rate == 0) {
383 printf("dc: clock init failed\n");
385 } else if (plld_rate != timing->pixelclock.typ * 2) {
386 debug("dc: plld rounded to %u\n", plld_rate);
387 timing->pixelclock.typ = plld_rate / 2;
391 ret = tegra_dc_init(dc_ctlr);
393 debug("dc: init failed\n");
397 /* Configure dc mode */
398 ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync);
400 debug("dc: failed to configure display mode\n");
405 ret = display_enable(dp_dev, panel_bpp, timing);
407 debug("dc: failed to enable display: ret=%d\n", ret);
411 ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
413 debug("dc: failed to update window\n");
416 debug("%s: ready\n", __func__);
422 /* Maximum LCD size we support */
423 LCD_MAX_WIDTH = 1920,
424 LCD_MAX_HEIGHT = 1200,
425 LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
428 static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
429 enum video_log2_bpp l2bpp)
431 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
432 struct display_timing timing;
435 clock_set_up_plldp();
436 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
438 clock_enable(PERIPH_ID_HOST1X);
439 clock_enable(PERIPH_ID_DISP1);
440 clock_enable(PERIPH_ID_PWM);
441 clock_enable(PERIPH_ID_DPAUX);
442 clock_enable(PERIPH_ID_SOR0);
445 reset_set_enable(PERIPH_ID_HOST1X, 0);
446 reset_set_enable(PERIPH_ID_DISP1, 0);
447 reset_set_enable(PERIPH_ID_PWM, 0);
448 reset_set_enable(PERIPH_ID_DPAUX, 0);
449 reset_set_enable(PERIPH_ID_SOR0, 0);
451 ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
455 uc_priv->xsize = roundup(timing.hactive.typ, 16);
456 uc_priv->ysize = timing.vactive.typ;
457 uc_priv->bpix = l2bpp;
459 video_set_flush_dcache(dev, 1);
460 debug("%s: done\n", __func__);
465 static int tegra124_lcd_probe(struct udevice *dev)
467 struct video_uc_plat *plat = dev_get_uclass_plat(dev);
471 start = get_timer(0);
472 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "lcd");
473 ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
474 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
475 debug("LCD init took %lu ms\n", get_timer(start));
477 printf("%s: Error %d\n", __func__, ret);
482 static int tegra124_lcd_bind(struct udevice *dev)
484 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
486 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
487 (1 << VIDEO_BPP16) / 8;
488 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
493 static const struct udevice_id tegra124_lcd_ids[] = {
494 { .compatible = "nvidia,tegra124-dc" },
498 U_BOOT_DRIVER(tegra124_dc) = {
499 .name = "tegra124-dc",
501 .of_match = tegra124_lcd_ids,
502 .bind = tegra124_lcd_bind,
503 .probe = tegra124_lcd_probe,