1208d9128682e083452da34a3ff0d4b8c8e02429
[platform/kernel/u-boot.git] / drivers / video / tegra.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <log.h>
10 #include <panel.h>
11 #include <part.h>
12 #include <pwm.h>
13 #include <video.h>
14 #include <asm/cache.h>
15 #include <asm/system.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18
19 #include <asm/arch/clock.h>
20 #include <asm/arch/funcmux.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/pwm.h>
23 #include <asm/arch/display.h>
24 #include <asm/arch-tegra/timer.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 /* Information about the display controller */
29 struct tegra_lcd_priv {
30         int width;                      /* width in pixels */
31         int height;                     /* height in pixels */
32         enum video_log2_bpp log2_bpp;   /* colour depth */
33         struct display_timing timing;
34         struct udevice *panel;
35         struct disp_ctlr *disp;         /* Display controller to use */
36         fdt_addr_t frame_buffer;        /* Address of frame buffer */
37         unsigned pixel_clock;           /* Pixel clock in Hz */
38 };
39
40 enum {
41         /* Maximum LCD size we support */
42         LCD_MAX_WIDTH           = 1366,
43         LCD_MAX_HEIGHT          = 768,
44         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
45 };
46
47 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
48 {
49         unsigned h_dda, v_dda;
50         unsigned long val;
51
52         val = readl(&dc->cmd.disp_win_header);
53         val |= WINDOW_A_SELECT;
54         writel(val, &dc->cmd.disp_win_header);
55
56         writel(win->fmt, &dc->win.color_depth);
57
58         clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
59                         BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
60
61         val = win->out_x << H_POSITION_SHIFT;
62         val |= win->out_y << V_POSITION_SHIFT;
63         writel(val, &dc->win.pos);
64
65         val = win->out_w << H_SIZE_SHIFT;
66         val |= win->out_h << V_SIZE_SHIFT;
67         writel(val, &dc->win.size);
68
69         val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
70         val |= win->h << V_PRESCALED_SIZE_SHIFT;
71         writel(val, &dc->win.prescaled_size);
72
73         writel(0, &dc->win.h_initial_dda);
74         writel(0, &dc->win.v_initial_dda);
75
76         h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
77         v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
78
79         val = h_dda << H_DDA_INC_SHIFT;
80         val |= v_dda << V_DDA_INC_SHIFT;
81         writel(val, &dc->win.dda_increment);
82
83         writel(win->stride, &dc->win.line_stride);
84         writel(0, &dc->win.buf_stride);
85
86         val = WIN_ENABLE;
87         if (win->bpp < 24)
88                 val |= COLOR_EXPAND;
89         writel(val, &dc->win.win_opt);
90
91         writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
92         writel(win->x, &dc->winbuf.addr_h_offset);
93         writel(win->y, &dc->winbuf.addr_v_offset);
94
95         writel(0xff00, &dc->win.blend_nokey);
96         writel(0xff00, &dc->win.blend_1win);
97
98         val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
99         val |= GENERAL_UPDATE | WIN_A_UPDATE;
100         writel(val, &dc->cmd.state_ctrl);
101 }
102
103 static int update_display_mode(struct dc_disp_reg *disp,
104                                struct tegra_lcd_priv *priv)
105 {
106         struct display_timing *dt = &priv->timing;
107         unsigned long val;
108         unsigned long rate;
109         unsigned long div;
110
111         writel(0x0, &disp->disp_timing_opt);
112
113         writel(1 | 1 << 16, &disp->ref_to_sync);
114         writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
115         writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
116                &disp->back_porch);
117         writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
118                &disp->front_porch);
119         writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
120
121         val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
122         val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
123         writel(val, &disp->data_enable_opt);
124
125         val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
126         val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
127         val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
128         writel(val, &disp->disp_interface_ctrl);
129
130         /*
131          * The pixel clock divider is in 7.1 format (where the bottom bit
132          * represents 0.5). Here we calculate the divider needed to get from
133          * the display clock (typically 600MHz) to the pixel clock. We round
134          * up or down as requried.
135          */
136         rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
137         div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
138         debug("Display clock %lu, divider %lu\n", rate, div);
139
140         writel(0x00010001, &disp->shift_clk_opt);
141
142         val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
143         val |= div << SHIFT_CLK_DIVIDER_SHIFT;
144         writel(val, &disp->disp_clk_ctrl);
145
146         return 0;
147 }
148
149 /* Start up the display and turn on power to PWMs */
150 static void basic_init(struct dc_cmd_reg *cmd)
151 {
152         u32 val;
153
154         writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
155         writel(0x0000011a, &cmd->cont_syncpt_vsync);
156         writel(0x00000000, &cmd->int_type);
157         writel(0x00000000, &cmd->int_polarity);
158         writel(0x00000000, &cmd->int_mask);
159         writel(0x00000000, &cmd->int_enb);
160
161         val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
162         val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
163         val |= PM1_ENABLE;
164         writel(val, &cmd->disp_pow_ctrl);
165
166         val = readl(&cmd->disp_cmd);
167         val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
168         writel(val, &cmd->disp_cmd);
169 }
170
171 static void basic_init_timer(struct dc_disp_reg *disp)
172 {
173         writel(0x00000020, &disp->mem_high_pri);
174         writel(0x00000001, &disp->mem_high_pri_timer);
175 }
176
177 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
178         0x00000000,
179         0x00000000,
180         0x00000000,
181         0x00000000,
182 };
183
184 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
185         0x00000000,
186         0x01000000,
187         0x00000000,
188         0x00000000,
189 };
190
191 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
192         0x00000000,
193         0x00000000,
194         0x00000000,
195         0x00000000,
196 };
197
198 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
199         0x00000000,
200         0x00000000,
201         0x00000000,
202         0x00000000,
203         0x00210222,
204         0x00002200,
205         0x00020000,
206 };
207
208 static void rgb_enable(struct dc_com_reg *com)
209 {
210         int i;
211
212         for (i = 0; i < PIN_REG_COUNT; i++) {
213                 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
214                 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
215                 writel(rgb_data_tab[i], &com->pin_output_data[i]);
216         }
217
218         for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
219                 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
220 }
221
222 static int setup_window(struct disp_ctl_win *win,
223                         struct tegra_lcd_priv *priv)
224 {
225         win->x = 0;
226         win->y = 0;
227         win->w = priv->width;
228         win->h = priv->height;
229         win->out_x = 0;
230         win->out_y = 0;
231         win->out_w = priv->width;
232         win->out_h = priv->height;
233         win->phys_addr = priv->frame_buffer;
234         win->stride = priv->width * (1 << priv->log2_bpp) / 8;
235         debug("%s: depth = %d\n", __func__, priv->log2_bpp);
236         switch (priv->log2_bpp) {
237         case VIDEO_BPP32:
238                 win->fmt = COLOR_DEPTH_R8G8B8A8;
239                 win->bpp = 32;
240                 break;
241         case VIDEO_BPP16:
242                 win->fmt = COLOR_DEPTH_B5G6R5;
243                 win->bpp = 16;
244                 break;
245
246         default:
247                 debug("Unsupported LCD bit depth");
248                 return -1;
249         }
250
251         return 0;
252 }
253
254 /**
255  * Register a new display based on device tree configuration.
256  *
257  * The frame buffer can be positioned by U-Boot or overridden by the fdt.
258  * You should pass in the U-Boot address here, and check the contents of
259  * struct tegra_lcd_priv to see what was actually chosen.
260  *
261  * @param blob                  Device tree blob
262  * @param priv                  Driver's private data
263  * @param default_lcd_base      Default address of LCD frame buffer
264  * @return 0 if ok, -1 on error (unsupported bits per pixel)
265  */
266 static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
267                                void *default_lcd_base)
268 {
269         struct disp_ctl_win window;
270         struct dc_ctlr *dc;
271
272         priv->frame_buffer = (u32)default_lcd_base;
273
274         dc = (struct dc_ctlr *)priv->disp;
275
276         /*
277          * A header file for clock constants was NAKed upstream.
278          * TODO: Put this into the FDT and fdt_lcd struct when we have clock
279          * support there
280          */
281         clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
282                                144 * 1000000);
283         clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
284                                600 * 1000000);
285         basic_init(&dc->cmd);
286         basic_init_timer(&dc->disp);
287         rgb_enable(&dc->com);
288
289         if (priv->pixel_clock)
290                 update_display_mode(&dc->disp, priv);
291
292         if (setup_window(&window, priv))
293                 return -1;
294
295         update_window(dc, &window);
296
297         return 0;
298 }
299
300 static int tegra_lcd_probe(struct udevice *dev)
301 {
302         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
303         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
304         struct tegra_lcd_priv *priv = dev_get_priv(dev);
305         const void *blob = gd->fdt_blob;
306         int ret;
307
308         /* Initialize the Tegra display controller */
309         funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
310         if (tegra_display_probe(blob, priv, (void *)plat->base)) {
311                 printf("%s: Failed to probe display driver\n", __func__);
312                 return -1;
313         }
314
315         pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
316         pinmux_tristate_disable(PMUX_PINGRP_GPU);
317
318         ret = panel_enable_backlight(priv->panel);
319         if (ret) {
320                 debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
321                 return ret;
322         }
323
324         mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
325                                         DCACHE_WRITETHROUGH);
326
327         /* Enable flushing after LCD writes if requested */
328         video_set_flush_dcache(dev, true);
329
330         uc_priv->xsize = priv->width;
331         uc_priv->ysize = priv->height;
332         uc_priv->bpix = priv->log2_bpp;
333         debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
334               plat->size);
335
336         return 0;
337 }
338
339 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
340 {
341         struct tegra_lcd_priv *priv = dev_get_priv(dev);
342         const void *blob = gd->fdt_blob;
343         struct display_timing *timing;
344         int node = dev_of_offset(dev);
345         int panel_node;
346         int rgb;
347         int ret;
348
349         priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
350         if (!priv->disp) {
351                 debug("%s: No display controller address\n", __func__);
352                 return -EINVAL;
353         }
354
355         rgb = fdt_subnode_offset(blob, node, "rgb");
356         if (rgb < 0) {
357                 debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
358                       __func__, dev->name, rgb);
359                 return -EINVAL;
360         }
361
362         ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
363         if (ret) {
364                 debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
365                       __func__, dev->name, ret);
366                 return -EINVAL;
367         }
368         timing = &priv->timing;
369         priv->width = timing->hactive.typ;
370         priv->height = timing->vactive.typ;
371         priv->pixel_clock = timing->pixelclock.typ;
372         priv->log2_bpp = VIDEO_BPP16;
373
374         /*
375          * Sadly the panel phandle is in an rgb subnode so we cannot use
376          * uclass_get_device_by_phandle().
377          */
378         panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
379         if (panel_node < 0) {
380                 debug("%s: Cannot find panel information\n", __func__);
381                 return -EINVAL;
382         }
383         ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
384                                              &priv->panel);
385         if (ret) {
386                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
387                       dev->name, ret);
388                 return ret;
389         }
390
391         return 0;
392 }
393
394 static int tegra_lcd_bind(struct udevice *dev)
395 {
396         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
397         const void *blob = gd->fdt_blob;
398         int node = dev_of_offset(dev);
399         int rgb;
400
401         rgb = fdt_subnode_offset(blob, node, "rgb");
402         if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
403                 return -ENODEV;
404
405         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
406                 (1 << LCD_MAX_LOG2_BPP) / 8;
407
408         return 0;
409 }
410
411 static const struct video_ops tegra_lcd_ops = {
412 };
413
414 static const struct udevice_id tegra_lcd_ids[] = {
415         { .compatible = "nvidia,tegra20-dc" },
416         { }
417 };
418
419 U_BOOT_DRIVER(tegra_lcd) = {
420         .name   = "tegra_lcd",
421         .id     = UCLASS_VIDEO,
422         .of_match = tegra_lcd_ids,
423         .ops    = &tegra_lcd_ops,
424         .bind   = tegra_lcd_bind,
425         .probe  = tegra_lcd_probe,
426         .ofdata_to_platdata     = tegra_lcd_ofdata_to_platdata,
427         .priv_auto_alloc_size   = sizeof(struct tegra_lcd_priv),
428 };