drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <errno.h>
  19 #include <fdtdec.h>
  20 #include <fdt_support.h>
  21 #include <video_fb.h>
  22 #include "videomodes.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sunxi_monitor {
  27         sunxi_monitor_none,
  28         sunxi_monitor_dvi,
  29         sunxi_monitor_hdmi,
  30         sunxi_monitor_lcd,
  31         sunxi_monitor_vga,
  32 };
  33 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  34
  35 struct sunxi_display {
  36         GraphicDevice graphic_device;
  37         bool enabled;
  38         enum sunxi_monitor monitor;
  39         unsigned int depth;
  40 } sunxi_display;
  41
  42 #ifdef CONFIG_VIDEO_HDMI
  43
  44 /*
  45  * Wait up to 200ms for value to be set in given part of reg.
  46  */
  47 static int await_completion(u32 *reg, u32 mask, u32 val)
  48 {
  49         unsigned long tmo = timer_get_us() + 200000;
  50
  51         while ((readl(reg) & mask) != val) {
  52                 if (timer_get_us() > tmo) {
  53                         printf("DDC: timeout reading EDID\n");
  54                         return -ETIME;
  55                 }
  56         }
  57         return 0;
  58 }
  59
  60 static int sunxi_hdmi_hpd_detect(void)
  61 {
  62         struct sunxi_ccm_reg * const ccm =
  63                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  64         struct sunxi_hdmi_reg * const hdmi =
  65                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  66         unsigned long tmo = timer_get_us() + 300000;
  67
  68         /* Set pll3 to 300MHz */
  69         clock_set_pll3(300000000);
  70
  71         /* Set hdmi parent to pll3 */
  72         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  73                         CCM_HDMI_CTRL_PLL3);
  74
  75         /* Set ahb gating to pass */
  76 #ifdef CONFIG_MACH_SUN6I
  77         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  78 #endif
  79         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  80
  81         /* Clock on */
  82         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  83
  84         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  85         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  86
  87         while (timer_get_us() < tmo) {
  88                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  89                         return 1;
  90         }
  91
  92         return 0;
  93 }
  94
  95 static void sunxi_hdmi_shutdown(void)
  96 {
  97         struct sunxi_ccm_reg * const ccm =
  98                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  99         struct sunxi_hdmi_reg * const hdmi =
 100                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 101
 102         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
 103         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 104         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 105 #ifdef CONFIG_MACH_SUN6I
 106         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 107 #endif
 108         clock_set_pll3(0);
 109 }
 110
 111 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 112 {
 113         struct sunxi_hdmi_reg * const hdmi =
 114                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 115
 116         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 117         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 118                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 119                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 120                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 121 #ifndef CONFIG_MACH_SUN6I
 122         writel(n, &hdmi->ddc_byte_count);
 123         writel(cmnd, &hdmi->ddc_cmnd);
 124 #else
 125         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 126 #endif
 127         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 128
 129         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 130 }
 131
 132 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 133 {
 134         struct sunxi_hdmi_reg * const hdmi =
 135                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 136         int i, n;
 137
 138         while (count > 0) {
 139                 if (count > 16)
 140                         n = 16;
 141                 else
 142                         n = count;
 143
 144                 if (sunxi_hdmi_ddc_do_command(
 145                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 146                                 offset, n))
 147                         return -ETIME;
 148
 149                 for (i = 0; i < n; i++)
 150                         *buf++ = readb(&hdmi->ddc_fifo_data);
 151
 152                 offset += n;
 153                 count -= n;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 160 {
 161         int r, retries = 2;
 162
 163         do {
 164                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 165                 if (r)
 166                         continue;
 167                 r = edid_check_checksum(buf);
 168                 if (r) {
 169                         printf("EDID block %d: checksum error%s\n",
 170                                block, retries ? ", retrying" : "");
 171                 }
 172         } while (r && retries--);
 173
 174         return r;
 175 }
 176
 177 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 178 {
 179         struct edid1_info edid1;
 180         struct edid_cea861_info cea681[4];
 181         struct edid_detailed_timing *t =
 182                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 183         struct sunxi_hdmi_reg * const hdmi =
 184                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 185         struct sunxi_ccm_reg * const ccm =
 186                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 187         int i, r, ext_blocks = 0;
 188
 189         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 190         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 191                &hdmi->pad_ctrl1);
 192         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 193                &hdmi->pll_ctrl);
 194         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 195
 196         /* Reset i2c controller */
 197         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 198         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 199                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 200                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 201                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 202         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 203                 return -EIO;
 204
 205         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 206 #ifndef CONFIG_MACH_SUN6I
 207         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 208                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 209 #endif
 210
 211         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 212         if (r == 0) {
 213                 r = edid_check_info(&edid1);
 214                 if (r) {
 215                         printf("EDID: invalid EDID data\n");
 216                         r = -EINVAL;
 217                 }
 218         }
 219         if (r == 0) {
 220                 ext_blocks = edid1.extension_flag;
 221                 if (ext_blocks > 4)
 222                         ext_blocks = 4;
 223                 for (i = 0; i < ext_blocks; i++) {
 224                         if (sunxi_hdmi_edid_get_block(1 + i,
 225                                                 (u8 *)&cea681[i]) != 0) {
 226                                 ext_blocks = i;
 227                                 break;
 228                         }
 229                 }
 230         }
 231
 232         /* Disable DDC engine, no longer needed */
 233         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 234         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 235
 236         if (r)
 237                 return r;
 238
 239         /* We want version 1.3 or 1.2 with detailed timing info */
 240         if (edid1.version != 1 || (edid1.revision < 3 &&
 241                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 242                 printf("EDID: unsupported version %d.%d\n",
 243                        edid1.version, edid1.revision);
 244                 return -EINVAL;
 245         }
 246
 247         /* Take the first usable detailed timing */
 248         for (i = 0; i < 4; i++, t++) {
 249                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 250                 if (r == 0)
 251                         break;
 252         }
 253         if (i == 4) {
 254                 printf("EDID: no usable detailed timing found\n");
 255                 return -ENOENT;
 256         }
 257
 258         /* Check for basic audio support, if found enable hdmi output */
 259         sunxi_display.monitor = sunxi_monitor_dvi;
 260         for (i = 0; i < ext_blocks; i++) {
 261                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 262                     cea681[i].revision < 2)
 263                         continue;
 264
 265                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 266                         sunxi_display.monitor = sunxi_monitor_hdmi;
 267         }
 268
 269         return 0;
 270 }
 271
 272 #endif /* CONFIG_VIDEO_HDMI */
 273
 274 /*
 275  * This is the entity that mixes and matches the different layers and inputs.
 276  * Allwinner calls it the back-end, but i like composer better.
 277  */
 278 static void sunxi_composer_init(void)
 279 {
 280         struct sunxi_ccm_reg * const ccm =
 281                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 282         struct sunxi_de_be_reg * const de_be =
 283                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 284         int i;
 285
 286 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 287         /* Reset off */
 288         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 289 #endif
 290
 291         /* Clocks on */
 292         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 293         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 294         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 295
 296         /* Engine bug, clear registers after reset */
 297         for (i = 0x0800; i < 0x1000; i += 4)
 298                 writel(0, SUNXI_DE_BE0_BASE + i);
 299
 300         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 301 }
 302
 303 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 304                                     unsigned int address)
 305 {
 306         struct sunxi_de_be_reg * const de_be =
 307                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 308
 309         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 310                &de_be->disp_size);
 311         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 312                &de_be->layer0_size);
 313         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 314         writel(address << 3, &de_be->layer0_addr_low32b);
 315         writel(address >> 29, &de_be->layer0_addr_high4b);
 316         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 317
 318         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 319 }
 320
 321 static void sunxi_composer_enable(void)
 322 {
 323         struct sunxi_de_be_reg * const de_be =
 324                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 325
 326         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 327         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 328 }
 329
 330 /*
 331  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 332  */
 333 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
 334                                int *clk_div, int *clk_double)
 335 {
 336         struct sunxi_ccm_reg * const ccm =
 337                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 338         int value, n, m, min_m, max_m, diff;
 339         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 340         int best_double = 0;
 341
 342         if (tcon == 0) {
 343                 min_m = 6;
 344                 max_m = 127;
 345         } else {
 346                 min_m = 1;
 347                 max_m = 15;
 348         }
 349
 350         /*
 351          * Find the lowest divider resulting in a matching clock, if there
 352          * is no match, pick the closest lower clock, as monitors tend to
 353          * not sync to higher frequencies.
 354          */
 355         for (m = min_m; m <= max_m; m++) {
 356                 n = (m * dotclock) / 3000;
 357
 358                 if ((n >= 9) && (n <= 127)) {
 359                         value = (3000 * n) / m;
 360                         diff = dotclock - value;
 361                         if (diff < best_diff) {
 362                                 best_diff = diff;
 363                                 best_m = m;
 364                                 best_n = n;
 365                                 best_double = 0;
 366                         }
 367                 }
 368
 369                 /* These are just duplicates */
 370                 if (!(m & 1))
 371                         continue;
 372
 373                 n = (m * dotclock) / 6000;
 374                 if ((n >= 9) && (n <= 127)) {
 375                         value = (6000 * n) / m;
 376                         diff = dotclock - value;
 377                         if (diff < best_diff) {
 378                                 best_diff = diff;
 379                                 best_m = m;
 380                                 best_n = n;
 381                                 best_double = 1;
 382                         }
 383                 }
 384         }
 385
 386         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 387               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 388               best_double + 1, best_n, best_m);
 389
 390         clock_set_pll3(best_n * 3000000);
 391
 392         if (tcon == 0) {
 393                 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
 394                        (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
 395                                       CCM_LCD_CH0_CTRL_PLL3),
 396                        &ccm->lcd0_ch0_clk_cfg);
 397         } else {
 398                 writel(CCM_LCD_CH1_CTRL_GATE |
 399                        (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
 400                                       CCM_LCD_CH1_CTRL_PLL3) |
 401                        CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 402         }
 403
 404         *clk_div = best_m;
 405         *clk_double = best_double;
 406 }
 407
 408 static void sunxi_lcdc_init(void)
 409 {
 410         struct sunxi_ccm_reg * const ccm =
 411                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 412         struct sunxi_lcdc_reg * const lcdc =
 413                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 414
 415         /* Reset off */
 416 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 417         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 418 #else
 419         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 420 #endif
 421
 422         /* Clock on */
 423         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 424
 425         /* Init lcdc */
 426         writel(0, &lcdc->ctrl); /* Disable tcon */
 427         writel(0, &lcdc->int0); /* Disable all interrupts */
 428
 429         /* Disable tcon0 dot clock */
 430         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 431
 432         /* Set all io lines to tristate */
 433         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 434         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 435 }
 436
 437 static void sunxi_lcdc_enable(void)
 438 {
 439         struct sunxi_lcdc_reg * const lcdc =
 440                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 441
 442         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 443 }
 444
 445 static void sunxi_lcdc_panel_enable(void)
 446 {
 447         int pin;
 448
 449         /*
 450          * Start with backlight disabled to avoid the screen flashing to
 451          * white while the lcd inits.
 452          */
 453         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 454         if (pin != -1) {
 455                 gpio_request(pin, "lcd_backlight_enable");
 456                 gpio_direction_output(pin, 0);
 457         }
 458
 459         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 460         if (pin != -1) {
 461                 gpio_request(pin, "lcd_backlight_pwm");
 462                 /* backlight pwm is inverted, set to 1 to disable backlight */
 463                 gpio_direction_output(pin, 1);
 464         }
 465
 466         /* Give the backlight some time to turn off and power up the panel. */
 467         mdelay(40);
 468         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
 469         if (pin != -1) {
 470                 gpio_request(pin, "lcd_power");
 471                 gpio_direction_output(pin, 1);
 472         }
 473 }
 474
 475 static void sunxi_lcdc_backlight_enable(void)
 476 {
 477         int pin;
 478
 479         /*
 480          * We want to have scanned out at least one frame before enabling the
 481          * backlight to avoid the screen flashing to white when we enable it.
 482          */
 483         mdelay(40);
 484
 485         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 486         if (pin != -1)
 487                 gpio_direction_output(pin, 1);
 488
 489         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 490         if (pin != -1) {
 491                 /* backlight pwm is inverted, set to 0 to enable backlight */
 492                 gpio_direction_output(pin, 0);
 493         }
 494 }
 495
 496 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
 497 {
 498         int delay;
 499
 500         delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
 501         return (delay > 30) ? 30 : delay;
 502 }
 503
 504 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 505 {
 506         struct sunxi_lcdc_reg * const lcdc =
 507                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 508         int bp, clk_delay, clk_div, clk_double, pin, total, val;
 509
 510         for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 511                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
 512
 513         sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 514
 515         /* Use tcon0 */
 516         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 517                         SUNXI_LCDC_CTRL_IO_MAP_TCON0);
 518
 519         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 520         writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
 521                SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
 522
 523         writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
 524                SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
 525
 526         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 527                &lcdc->tcon0_timing_active);
 528
 529         bp = mode->hsync_len + mode->left_margin;
 530         total = mode->xres + mode->right_margin + bp;
 531         writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
 532                SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
 533
 534         bp = mode->vsync_len + mode->upper_margin;
 535         total = mode->yres + mode->lower_margin + bp;
 536         writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
 537                SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
 538
 539         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 540                &lcdc->tcon0_timing_sync);
 541
 542         /* We only support hv-sync parallel lcd-s for now */
 543         writel(0, &lcdc->tcon0_hv_intf);
 544         writel(0, &lcdc->tcon0_cpu_intf);
 545
 546         if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
 547                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
 548                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
 549                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
 550                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
 551                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
 552                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
 553                 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
 554                 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
 555                 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
 556                 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
 557                 writel(((sunxi_display.depth == 18) ?
 558                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
 559                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
 560                        &lcdc->tcon0_frm_ctrl);
 561         }
 562
 563         val = 0;
 564         if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 565                 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 566         if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
 567                 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 568         writel(val, &lcdc->tcon0_io_polarity);
 569
 570         writel(0, &lcdc->tcon0_io_tristate);
 571 }
 572
 573 #ifdef CONFIG_VIDEO_HDMI
 574
 575 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 576                                       int *clk_div, int *clk_double)
 577 {
 578         struct sunxi_lcdc_reg * const lcdc =
 579                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 580         int bp, total;
 581
 582         /* Use tcon1 */
 583         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 584                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 585
 586         /* Enabled, 0x1e start delay */
 587         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 588                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 589
 590         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 591                &lcdc->tcon1_timing_source);
 592         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 593                &lcdc->tcon1_timing_scale);
 594         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 595                &lcdc->tcon1_timing_out);
 596
 597         bp = mode->hsync_len + mode->left_margin;
 598         total = mode->xres + mode->right_margin + bp;
 599         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 600                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 601
 602         bp = mode->vsync_len + mode->upper_margin;
 603         total = mode->yres + mode->lower_margin + bp;
 604         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 605                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 606
 607         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 608                &lcdc->tcon1_timing_sync);
 609
 610         sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 611 }
 612
 613 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 614 {
 615         struct sunxi_hdmi_reg * const hdmi =
 616                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 617         u8 checksum = 0;
 618         u8 avi_info_frame[17] = {
 619                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 620                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 621                 0x00
 622         };
 623         u8 vendor_info_frame[19] = {
 624                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 625                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 626                 0x00, 0x00, 0x00
 627         };
 628         int i;
 629
 630         if (mode->pixclock_khz <= 27000)
 631                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 632         else
 633                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 634
 635         if (mode->xres * 100 / mode->yres < 156)
 636                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 637         else
 638                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 639
 640         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 641                 checksum += avi_info_frame[i];
 642
 643         avi_info_frame[3] = 0x100 - checksum;
 644
 645         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 646                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 647
 648         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 649         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 650
 651         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 652                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 653
 654         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 655         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 656
 657         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 658 }
 659
 660 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 661                                 int clk_div, int clk_double)
 662 {
 663         struct sunxi_hdmi_reg * const hdmi =
 664                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 665         int x, y;
 666
 667         /* Write clear interrupt status bits */
 668         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 669
 670         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 671                 sunxi_hdmi_setup_info_frames(mode);
 672
 673         /* Set input sync enable */
 674         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 675
 676         /* Init various registers, select pll3 as clock source */
 677         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 678         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 679         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 680         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 681         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 682
 683         /* Setup clk div and doubler */
 684         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 685                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 686         if (!clk_double)
 687                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 688
 689         /* Setup timing registers */
 690         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 691                &hdmi->video_size);
 692
 693         x = mode->hsync_len + mode->left_margin;
 694         y = mode->vsync_len + mode->upper_margin;
 695         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 696
 697         x = mode->right_margin;
 698         y = mode->lower_margin;
 699         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 700
 701         x = mode->hsync_len;
 702         y = mode->vsync_len;
 703         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 704
 705         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 706                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 707
 708         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 709                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 710 }
 711
 712 static void sunxi_hdmi_enable(void)
 713 {
 714         struct sunxi_hdmi_reg * const hdmi =
 715                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 716
 717         udelay(100);
 718         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 719 }
 720
 721 #endif /* CONFIG_VIDEO_HDMI */
 722
 723 static void sunxi_drc_init(void)
 724 {
 725 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 726         struct sunxi_ccm_reg * const ccm =
 727                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 728
 729         /* On sun6i the drc must be clocked even when in pass-through mode */
 730         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 731         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 732 #endif
 733 }
 734
 735 static void sunxi_engines_init(void)
 736 {
 737         sunxi_composer_init();
 738         sunxi_lcdc_init();
 739         sunxi_drc_init();
 740 }
 741
 742 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 743                            unsigned int address)
 744 {
 745         switch (sunxi_display.monitor) {
 746         case sunxi_monitor_none:
 747                 break;
 748         case sunxi_monitor_dvi:
 749         case sunxi_monitor_hdmi: {
 750 #ifdef CONFIG_VIDEO_HDMI
 751                 int clk_div, clk_double;
 752                 sunxi_composer_mode_set(mode, address);
 753                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double);
 754                 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 755                 sunxi_composer_enable();
 756                 sunxi_lcdc_enable();
 757                 sunxi_hdmi_enable();
 758 #endif
 759                 }
 760                 break;
 761         case sunxi_monitor_lcd:
 762                 sunxi_lcdc_panel_enable();
 763                 sunxi_composer_mode_set(mode, address);
 764                 sunxi_lcdc_tcon0_mode_set(mode);
 765                 sunxi_composer_enable();
 766                 sunxi_lcdc_enable();
 767                 sunxi_lcdc_backlight_enable();
 768                 break;
 769         case sunxi_monitor_vga:
 770 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 771                 sunxi_composer_mode_set(mode, address);
 772                 sunxi_lcdc_tcon0_mode_set(mode);
 773                 sunxi_composer_enable();
 774                 sunxi_lcdc_enable();
 775 #endif
 776                 break;
 777         }
 778 }
 779
 780 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 781 {
 782         switch (monitor) {
 783         case sunxi_monitor_none:        return "none";
 784         case sunxi_monitor_dvi:         return "dvi";
 785         case sunxi_monitor_hdmi:        return "hdmi";
 786         case sunxi_monitor_lcd:         return "lcd";
 787         case sunxi_monitor_vga:         return "vga";
 788         }
 789         return NULL; /* never reached */
 790 }
 791
 792 void *video_hw_init(void)
 793 {
 794         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 795         const struct ctfb_res_modes *mode;
 796         struct ctfb_res_modes custom;
 797         const char *options;
 798 #ifdef CONFIG_VIDEO_HDMI
 799         int ret, hpd, edid;
 800 #endif
 801         char mon[16];
 802         char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
 803         int i;
 804
 805         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 806
 807         printf("Reserved %dkB of RAM for Framebuffer.\n",
 808                CONFIG_SUNXI_FB_SIZE >> 10);
 809         gd->fb_base = gd->ram_top;
 810
 811         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 812                                  &sunxi_display.depth, &options);
 813 #ifdef CONFIG_VIDEO_HDMI
 814         hpd = video_get_option_int(options, "hpd", 1);
 815         edid = video_get_option_int(options, "edid", 1);
 816         sunxi_display.monitor = sunxi_monitor_dvi;
 817 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 818         sunxi_display.monitor = sunxi_monitor_vga;
 819 #else
 820         sunxi_display.monitor = sunxi_monitor_lcd;
 821 #endif
 822         video_get_option_string(options, "monitor", mon, sizeof(mon),
 823                                 sunxi_get_mon_desc(sunxi_display.monitor));
 824         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 825                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 826                         sunxi_display.monitor = i;
 827                         break;
 828                 }
 829         }
 830         if (i > SUNXI_MONITOR_LAST)
 831                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 832                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 833
 834         switch (sunxi_display.monitor) {
 835         case sunxi_monitor_none:
 836                 return NULL;
 837         case sunxi_monitor_dvi:
 838         case sunxi_monitor_hdmi:
 839 #ifndef CONFIG_VIDEO_HDMI
 840                 printf("HDMI/DVI not supported on this board\n");
 841                 return NULL;
 842 #else
 843                 /* Always call hdp_detect, as it also enables clocks, etc. */
 844                 ret = sunxi_hdmi_hpd_detect();
 845                 if (ret) {
 846                         printf("HDMI connected: ");
 847                         if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
 848                                 mode = &custom;
 849                         break;
 850                 }
 851                 if (!hpd)
 852                         break; /* User has requested to ignore hpd */
 853
 854                 sunxi_hdmi_shutdown();
 855
 856                 if (lcd_mode[0] == 0)
 857                         return NULL; /* No LCD, bail */
 858
 859                 /* Fall back / through to LCD */
 860                 sunxi_display.monitor = sunxi_monitor_lcd;
 861 #endif
 862         case sunxi_monitor_lcd:
 863                 if (lcd_mode[0]) {
 864                         sunxi_display.depth = video_get_params(&custom, lcd_mode);
 865                         mode = &custom;
 866                         break;
 867                 }
 868                 printf("LCD not supported on this board\n");
 869                 return NULL;
 870         case sunxi_monitor_vga:
 871 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 872                 sunxi_display.depth = 18;
 873                 break;
 874 #else
 875                 printf("VGA not supported on this board\n");
 876                 return NULL;
 877 #endif
 878         }
 879
 880         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 881                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 882                 mode = &res_mode_init[RES_MODE_1024x768];
 883         } else {
 884                 printf("Setting up a %dx%d %s console\n", mode->xres,
 885                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
 886         }
 887
 888         sunxi_display.enabled = true;
 889         sunxi_engines_init();
 890         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 891
 892         /*
 893          * These are the only members of this structure that are used. All the
 894          * others are driver specific. There is nothing to decribe pitch or
 895          * stride, but we are lucky with our hw.
 896          */
 897         graphic_device->frameAdrs = gd->fb_base;
 898         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 899         graphic_device->gdfBytesPP = 4;
 900         graphic_device->winSizeX = mode->xres;
 901         graphic_device->winSizeY = mode->yres;
 902
 903         return graphic_device;
 904 }
 905
 906 /*
 907  * Simplefb support.
 908  */
 909 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 910 int sunxi_simplefb_setup(void *blob)
 911 {
 912         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 913         int offset, ret;
 914         const char *pipeline = NULL;
 915
 916         if (!sunxi_display.enabled)
 917                 return 0;
 918
 919         switch (sunxi_display.monitor) {
 920         case sunxi_monitor_none:
 921                 return 0;
 922         case sunxi_monitor_dvi:
 923         case sunxi_monitor_hdmi:
 924                 pipeline = "de_be0-lcd0-hdmi";
 925                 break;
 926         case sunxi_monitor_lcd:
 927                 pipeline = "de_be0-lcd0";
 928                 break;
 929         case sunxi_monitor_vga:
 930                 pipeline = "de_be0-lcd0";
 931                 break;
 932         }
 933
 934         /* Find a prefilled simpefb node, matching out pipeline config */
 935         offset = fdt_node_offset_by_compatible(blob, -1,
 936                                                "allwinner,simple-framebuffer");
 937         while (offset >= 0) {
 938                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 939                                       pipeline);
 940                 if (ret == 0)
 941                         break;
 942                 offset = fdt_node_offset_by_compatible(blob, offset,
 943                                                "allwinner,simple-framebuffer");
 944         }
 945         if (offset < 0) {
 946                 eprintf("Cannot setup simplefb: node not found\n");
 947                 return 0; /* Keep older kernels working */
 948         }
 949
 950         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 951                         graphic_device->winSizeX, graphic_device->winSizeY,
 952                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 953                         "x8r8g8b8");
 954         if (ret)
 955                 eprintf("Cannot setup simplefb: Error setting properties\n");
 956
 957         return ret;
 958 }
 959 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */