drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <linux/fb.h>
  17 #include <video_fb.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct sunxi_display {
  22         GraphicDevice graphic_device;
  23         bool enabled;
  24 } sunxi_display;
  25
  26 static int sunxi_hdmi_hpd_detect(void)
  27 {
  28         struct sunxi_ccm_reg * const ccm =
  29                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  30         struct sunxi_hdmi_reg * const hdmi =
  31                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  32
  33         /* Set pll3 to 300MHz */
  34         clock_set_pll3(300000000);
  35
  36         /* Set hdmi parent to pll3 */
  37         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  38                         CCM_HDMI_CTRL_PLL3);
  39
  40         /* Set ahb gating to pass */
  41         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  42
  43         /* Clock on */
  44         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  45
  46         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  47         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  48
  49         udelay(1000);
  50
  51         if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  52                 return 1;
  53
  54         /* No need to keep these running */
  55         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  56         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  57         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  58         clock_set_pll3(0);
  59
  60         return 0;
  61 }
  62
  63 /*
  64  * This is the entity that mixes and matches the different layers and inputs.
  65  * Allwinner calls it the back-end, but i like composer better.
  66  */
  67 static void sunxi_composer_init(void)
  68 {
  69         struct sunxi_ccm_reg * const ccm =
  70                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  71         struct sunxi_de_be_reg * const de_be =
  72                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  73         int i;
  74
  75         /* Clocks on */
  76         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
  77         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
  78         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
  79
  80         /* Engine bug, clear registers after reset */
  81         for (i = 0x0800; i < 0x1000; i += 4)
  82                 writel(0, SUNXI_DE_BE0_BASE + i);
  83
  84         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
  85 }
  86
  87 static void sunxi_composer_mode_set(struct fb_videomode *mode,
  88                                     unsigned int address)
  89 {
  90         struct sunxi_de_be_reg * const de_be =
  91                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  92
  93         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  94                &de_be->disp_size);
  95         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
  96                &de_be->layer0_size);
  97         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
  98         writel(address << 3, &de_be->layer0_addr_low32b);
  99         writel(address >> 29, &de_be->layer0_addr_high4b);
 100         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 101
 102         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 103 }
 104
 105 /*
 106  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 107  */
 108 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 109 {
 110         struct sunxi_ccm_reg * const ccm =
 111                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 112         int value, n, m, diff;
 113         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 114         int best_double = 0;
 115
 116         /*
 117          * Find the lowest divider resulting in a matching clock, if there
 118          * is no match, pick the closest lower clock, as monitors tend to
 119          * not sync to higher frequencies.
 120          */
 121         for (m = 15; m > 0; m--) {
 122                 n = (m * dotclock) / 3000;
 123
 124                 if ((n >= 9) && (n <= 127)) {
 125                         value = (3000 * n) / m;
 126                         diff = dotclock - value;
 127                         if (diff < best_diff) {
 128                                 best_diff = diff;
 129                                 best_m = m;
 130                                 best_n = n;
 131                                 best_double = 0;
 132                         }
 133                 }
 134
 135                 /* These are just duplicates */
 136                 if (!(m & 1))
 137                         continue;
 138
 139                 n = (m * dotclock) / 6000;
 140                 if ((n >= 9) && (n <= 127)) {
 141                         value = (6000 * n) / m;
 142                         diff = dotclock - value;
 143                         if (diff < best_diff) {
 144                                 best_diff = diff;
 145                                 best_m = m;
 146                                 best_n = n;
 147                                 best_double = 1;
 148                         }
 149                 }
 150         }
 151
 152         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 153               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 154               best_double + 1, best_n, best_m);
 155
 156         clock_set_pll3(best_n * 3000000);
 157
 158         writel(CCM_LCD_CH1_CTRL_GATE |
 159             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 160             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 161
 162         *clk_div = best_m;
 163         *clk_double = best_double;
 164 }
 165
 166 static void sunxi_lcdc_init(void)
 167 {
 168         struct sunxi_ccm_reg * const ccm =
 169                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 170         struct sunxi_lcdc_reg * const lcdc =
 171                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 172
 173         /* Reset off */
 174         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 175
 176         /* Clock on */
 177         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 178
 179         /* Init lcdc */
 180         writel(0, &lcdc->ctrl); /* Disable tcon */
 181         writel(0, &lcdc->int0); /* Disable all interrupts */
 182
 183         /* Disable tcon0 dot clock */
 184         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 185
 186         /* Set all io lines to tristate */
 187         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 188         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 189 }
 190
 191 static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
 192                                 int *clk_div, int *clk_double)
 193 {
 194         struct sunxi_lcdc_reg * const lcdc =
 195                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 196         int bp, total;
 197
 198         /* Use tcon1 */
 199         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 200                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 201
 202         /* Enabled, 0x1e start delay */
 203         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 204                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 205
 206         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 207                &lcdc->tcon1_timing_source);
 208         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 209                &lcdc->tcon1_timing_scale);
 210         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 211                &lcdc->tcon1_timing_out);
 212
 213         bp = mode->hsync_len + mode->left_margin;
 214         total = mode->xres + mode->right_margin + bp;
 215         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 216                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 217
 218         bp = mode->vsync_len + mode->upper_margin;
 219         total = mode->yres + mode->lower_margin + bp;
 220         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 221                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 222
 223         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 224                &lcdc->tcon1_timing_sync);
 225
 226         sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
 227 }
 228
 229 static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
 230                                 int clk_div, int clk_double)
 231 {
 232         struct sunxi_hdmi_reg * const hdmi =
 233                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 234         int x, y;
 235
 236         /* Write clear interrupt status bits */
 237         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 238
 239         /* Init various registers, select pll3 as clock source */
 240         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 241         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 242         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 243         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 244         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 245
 246         /* Setup clk div and doubler */
 247         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 248                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 249         if (!clk_double)
 250                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 251
 252         /* Setup timing registers */
 253         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 254                &hdmi->video_size);
 255
 256         x = mode->hsync_len + mode->left_margin;
 257         y = mode->vsync_len + mode->upper_margin;
 258         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 259
 260         x = mode->right_margin;
 261         y = mode->lower_margin;
 262         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 263
 264         x = mode->hsync_len;
 265         y = mode->vsync_len;
 266         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 267
 268         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 269                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 270
 271         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 272                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 273 }
 274
 275 static void sunxi_engines_init(void)
 276 {
 277         sunxi_composer_init();
 278         sunxi_lcdc_init();
 279 }
 280
 281 static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
 282 {
 283         struct sunxi_de_be_reg * const de_be =
 284                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 285         struct sunxi_lcdc_reg * const lcdc =
 286                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 287         struct sunxi_hdmi_reg * const hdmi =
 288                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 289         int clk_div, clk_double;
 290         int retries = 3;
 291
 292 retry:
 293         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 294         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 295         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 296
 297         sunxi_composer_mode_set(mode, address);
 298         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 299         sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 300
 301         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 302         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 303
 304         udelay(1000000 / mode->refresh + 500);
 305
 306         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 307
 308         udelay(1000000 / mode->refresh + 500);
 309
 310         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 311
 312         udelay(1000000 / mode->refresh + 500);
 313
 314         /*
 315          * Sometimes the display pipeline does not sync up properly, if
 316          * this happens the hdmi fifo underrun or overrun bits are set.
 317          */
 318         if (readl(&hdmi->irq) &
 319             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 320                 if (retries--)
 321                         goto retry;
 322                 printf("HDMI fifo under or overrun\n");
 323         }
 324 }
 325
 326 void *video_hw_init(void)
 327 {
 328         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 329         /*
 330          * Vesa standard 1024x768@60
 331          * 65.0  1024 1048 1184 1344  768 771 777 806  -hsync -vsync
 332          */
 333         struct fb_videomode mode = {
 334                 .name = "1024x768",
 335                 .refresh = 60,
 336                 .xres = 1024,
 337                 .yres = 768,
 338                 .pixclock = 65000,
 339                 .left_margin = 160,
 340                 .right_margin = 24,
 341                 .upper_margin = 29,
 342                 .lower_margin = 3,
 343                 .hsync_len = 136,
 344                 .vsync_len = 6,
 345                 .sync = 0,
 346                 .vmode = 0,
 347                 .flag = 0,
 348         };
 349         int ret;
 350
 351         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 352
 353         printf("Reserved %dkB of RAM for Framebuffer.\n",
 354                CONFIG_SUNXI_FB_SIZE >> 10);
 355         gd->fb_base = gd->ram_top;
 356
 357         ret = sunxi_hdmi_hpd_detect();
 358         if (!ret)
 359                 return NULL;
 360
 361         printf("HDMI connected.\n");
 362         sunxi_display.enabled = true;
 363
 364         printf("Setting up a %s console.\n", mode.name);
 365         sunxi_engines_init();
 366         sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 367
 368         /*
 369          * These are the only members of this structure that are used. All the
 370          * others are driver specific. There is nothing to decribe pitch or
 371          * stride, but we are lucky with our hw.
 372          */
 373         graphic_device->frameAdrs = gd->fb_base;
 374         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 375         graphic_device->gdfBytesPP = 4;
 376         graphic_device->winSizeX = mode.xres;
 377         graphic_device->winSizeY = mode.yres;
 378
 379         return graphic_device;
 380 }