drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <errno.h>
  19 #include <fdtdec.h>
  20 #include <fdt_support.h>
  21 #include <video_fb.h>
  22 #include "videomodes.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sunxi_monitor {
  27         sunxi_monitor_none,
  28         sunxi_monitor_dvi,
  29         sunxi_monitor_hdmi,
  30         sunxi_monitor_lcd,
  31         sunxi_monitor_vga,
  32 };
  33 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  34
  35 struct sunxi_display {
  36         GraphicDevice graphic_device;
  37         enum sunxi_monitor monitor;
  38         unsigned int depth;
  39 } sunxi_display;
  40
  41 #ifdef CONFIG_VIDEO_HDMI
  42
  43 /*
  44  * Wait up to 200ms for value to be set in given part of reg.
  45  */
  46 static int await_completion(u32 *reg, u32 mask, u32 val)
  47 {
  48         unsigned long tmo = timer_get_us() + 200000;
  49
  50         while ((readl(reg) & mask) != val) {
  51                 if (timer_get_us() > tmo) {
  52                         printf("DDC: timeout reading EDID\n");
  53                         return -ETIME;
  54                 }
  55         }
  56         return 0;
  57 }
  58
  59 static int sunxi_hdmi_hpd_detect(void)
  60 {
  61         struct sunxi_ccm_reg * const ccm =
  62                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  63         struct sunxi_hdmi_reg * const hdmi =
  64                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  65         unsigned long tmo = timer_get_us() + 300000;
  66
  67         /* Set pll3 to 300MHz */
  68         clock_set_pll3(300000000);
  69
  70         /* Set hdmi parent to pll3 */
  71         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  72                         CCM_HDMI_CTRL_PLL3);
  73
  74         /* Set ahb gating to pass */
  75 #ifdef CONFIG_MACH_SUN6I
  76         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  77 #endif
  78         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  79
  80         /* Clock on */
  81         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  82
  83         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  84         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  85
  86         while (timer_get_us() < tmo) {
  87                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  88                         return 1;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static void sunxi_hdmi_shutdown(void)
  95 {
  96         struct sunxi_ccm_reg * const ccm =
  97                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  98         struct sunxi_hdmi_reg * const hdmi =
  99                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 100
 101         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
 102         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 103         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 104 #ifdef CONFIG_MACH_SUN6I
 105         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 106 #endif
 107         clock_set_pll3(0);
 108 }
 109
 110 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 111 {
 112         struct sunxi_hdmi_reg * const hdmi =
 113                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 114
 115         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 116         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 117                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 118                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 119                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 120 #ifndef CONFIG_MACH_SUN6I
 121         writel(n, &hdmi->ddc_byte_count);
 122         writel(cmnd, &hdmi->ddc_cmnd);
 123 #else
 124         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 125 #endif
 126         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 127
 128         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 129 }
 130
 131 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 132 {
 133         struct sunxi_hdmi_reg * const hdmi =
 134                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 135         int i, n;
 136
 137         while (count > 0) {
 138                 if (count > 16)
 139                         n = 16;
 140                 else
 141                         n = count;
 142
 143                 if (sunxi_hdmi_ddc_do_command(
 144                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 145                                 offset, n))
 146                         return -ETIME;
 147
 148                 for (i = 0; i < n; i++)
 149                         *buf++ = readb(&hdmi->ddc_fifo_data);
 150
 151                 offset += n;
 152                 count -= n;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 159 {
 160         int r, retries = 2;
 161
 162         do {
 163                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 164                 if (r)
 165                         continue;
 166                 r = edid_check_checksum(buf);
 167                 if (r) {
 168                         printf("EDID block %d: checksum error%s\n",
 169                                block, retries ? ", retrying" : "");
 170                 }
 171         } while (r && retries--);
 172
 173         return r;
 174 }
 175
 176 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 177 {
 178         struct edid1_info edid1;
 179         struct edid_cea861_info cea681[4];
 180         struct edid_detailed_timing *t =
 181                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 182         struct sunxi_hdmi_reg * const hdmi =
 183                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 184         struct sunxi_ccm_reg * const ccm =
 185                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 186         int i, r, ext_blocks = 0;
 187
 188         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 189         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 190                &hdmi->pad_ctrl1);
 191         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 192                &hdmi->pll_ctrl);
 193         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 194
 195         /* Reset i2c controller */
 196         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 197         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 198                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 199                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 200                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 201         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 202                 return -EIO;
 203
 204         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 205 #ifndef CONFIG_MACH_SUN6I
 206         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 207                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 208 #endif
 209
 210         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 211         if (r == 0) {
 212                 r = edid_check_info(&edid1);
 213                 if (r) {
 214                         printf("EDID: invalid EDID data\n");
 215                         r = -EINVAL;
 216                 }
 217         }
 218         if (r == 0) {
 219                 ext_blocks = edid1.extension_flag;
 220                 if (ext_blocks > 4)
 221                         ext_blocks = 4;
 222                 for (i = 0; i < ext_blocks; i++) {
 223                         if (sunxi_hdmi_edid_get_block(1 + i,
 224                                                 (u8 *)&cea681[i]) != 0) {
 225                                 ext_blocks = i;
 226                                 break;
 227                         }
 228                 }
 229         }
 230
 231         /* Disable DDC engine, no longer needed */
 232         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 233         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 234
 235         if (r)
 236                 return r;
 237
 238         /* We want version 1.3 or 1.2 with detailed timing info */
 239         if (edid1.version != 1 || (edid1.revision < 3 &&
 240                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 241                 printf("EDID: unsupported version %d.%d\n",
 242                        edid1.version, edid1.revision);
 243                 return -EINVAL;
 244         }
 245
 246         /* Take the first usable detailed timing */
 247         for (i = 0; i < 4; i++, t++) {
 248                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 249                 if (r == 0)
 250                         break;
 251         }
 252         if (i == 4) {
 253                 printf("EDID: no usable detailed timing found\n");
 254                 return -ENOENT;
 255         }
 256
 257         /* Check for basic audio support, if found enable hdmi output */
 258         sunxi_display.monitor = sunxi_monitor_dvi;
 259         for (i = 0; i < ext_blocks; i++) {
 260                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 261                     cea681[i].revision < 2)
 262                         continue;
 263
 264                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 265                         sunxi_display.monitor = sunxi_monitor_hdmi;
 266         }
 267
 268         return 0;
 269 }
 270
 271 #endif /* CONFIG_VIDEO_HDMI */
 272
 273 /*
 274  * This is the entity that mixes and matches the different layers and inputs.
 275  * Allwinner calls it the back-end, but i like composer better.
 276  */
 277 static void sunxi_composer_init(void)
 278 {
 279         struct sunxi_ccm_reg * const ccm =
 280                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 281         struct sunxi_de_be_reg * const de_be =
 282                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 283         int i;
 284
 285 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 286         /* Reset off */
 287         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 288 #endif
 289
 290         /* Clocks on */
 291         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 292         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 293         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 294
 295         /* Engine bug, clear registers after reset */
 296         for (i = 0x0800; i < 0x1000; i += 4)
 297                 writel(0, SUNXI_DE_BE0_BASE + i);
 298
 299         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 300 }
 301
 302 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 303                                     unsigned int address)
 304 {
 305         struct sunxi_de_be_reg * const de_be =
 306                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 307
 308         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 309                &de_be->disp_size);
 310         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 311                &de_be->layer0_size);
 312         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 313         writel(address << 3, &de_be->layer0_addr_low32b);
 314         writel(address >> 29, &de_be->layer0_addr_high4b);
 315         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 316
 317         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 318 }
 319
 320 static void sunxi_composer_enable(void)
 321 {
 322         struct sunxi_de_be_reg * const de_be =
 323                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 324
 325         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 326         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 327 }
 328
 329 /*
 330  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 331  */
 332 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
 333                                int *clk_div, int *clk_double)
 334 {
 335         struct sunxi_ccm_reg * const ccm =
 336                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 337         int value, n, m, min_m, max_m, diff;
 338         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 339         int best_double = 0;
 340
 341         if (tcon == 0) {
 342                 min_m = 6;
 343                 max_m = 127;
 344         } else {
 345                 min_m = 1;
 346                 max_m = 15;
 347         }
 348
 349         /*
 350          * Find the lowest divider resulting in a matching clock, if there
 351          * is no match, pick the closest lower clock, as monitors tend to
 352          * not sync to higher frequencies.
 353          */
 354         for (m = min_m; m <= max_m; m++) {
 355                 n = (m * dotclock) / 3000;
 356
 357                 if ((n >= 9) && (n <= 127)) {
 358                         value = (3000 * n) / m;
 359                         diff = dotclock - value;
 360                         if (diff < best_diff) {
 361                                 best_diff = diff;
 362                                 best_m = m;
 363                                 best_n = n;
 364                                 best_double = 0;
 365                         }
 366                 }
 367
 368                 /* These are just duplicates */
 369                 if (!(m & 1))
 370                         continue;
 371
 372                 n = (m * dotclock) / 6000;
 373                 if ((n >= 9) && (n <= 127)) {
 374                         value = (6000 * n) / m;
 375                         diff = dotclock - value;
 376                         if (diff < best_diff) {
 377                                 best_diff = diff;
 378                                 best_m = m;
 379                                 best_n = n;
 380                                 best_double = 1;
 381                         }
 382                 }
 383         }
 384
 385         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 386               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 387               best_double + 1, best_n, best_m);
 388
 389         clock_set_pll3(best_n * 3000000);
 390
 391         if (tcon == 0) {
 392                 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
 393                        (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
 394                                       CCM_LCD_CH0_CTRL_PLL3),
 395                        &ccm->lcd0_ch0_clk_cfg);
 396         } else {
 397                 writel(CCM_LCD_CH1_CTRL_GATE |
 398                        (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
 399                                       CCM_LCD_CH1_CTRL_PLL3) |
 400                        CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 401         }
 402
 403         *clk_div = best_m;
 404         *clk_double = best_double;
 405 }
 406
 407 static void sunxi_lcdc_init(void)
 408 {
 409         struct sunxi_ccm_reg * const ccm =
 410                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 411         struct sunxi_lcdc_reg * const lcdc =
 412                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 413
 414         /* Reset off */
 415 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 416         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 417 #else
 418         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 419 #endif
 420
 421         /* Clock on */
 422         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 423
 424         /* Init lcdc */
 425         writel(0, &lcdc->ctrl); /* Disable tcon */
 426         writel(0, &lcdc->int0); /* Disable all interrupts */
 427
 428         /* Disable tcon0 dot clock */
 429         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 430
 431         /* Set all io lines to tristate */
 432         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 433         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 434 }
 435
 436 static void sunxi_lcdc_enable(void)
 437 {
 438         struct sunxi_lcdc_reg * const lcdc =
 439                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 440
 441         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 442 }
 443
 444 static void sunxi_lcdc_panel_enable(void)
 445 {
 446         int pin;
 447
 448         /*
 449          * Start with backlight disabled to avoid the screen flashing to
 450          * white while the lcd inits.
 451          */
 452         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 453         if (pin != -1) {
 454                 gpio_request(pin, "lcd_backlight_enable");
 455                 gpio_direction_output(pin, 0);
 456         }
 457
 458         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 459         if (pin != -1) {
 460                 gpio_request(pin, "lcd_backlight_pwm");
 461                 /* backlight pwm is inverted, set to 1 to disable backlight */
 462                 gpio_direction_output(pin, 1);
 463         }
 464
 465         /* Give the backlight some time to turn off and power up the panel. */
 466         mdelay(40);
 467         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
 468         if (pin != -1) {
 469                 gpio_request(pin, "lcd_power");
 470                 gpio_direction_output(pin, 1);
 471         }
 472 }
 473
 474 static void sunxi_lcdc_backlight_enable(void)
 475 {
 476         int pin;
 477
 478         /*
 479          * We want to have scanned out at least one frame before enabling the
 480          * backlight to avoid the screen flashing to white when we enable it.
 481          */
 482         mdelay(40);
 483
 484         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 485         if (pin != -1)
 486                 gpio_direction_output(pin, 1);
 487
 488         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 489         if (pin != -1) {
 490                 /* backlight pwm is inverted, set to 0 to enable backlight */
 491                 gpio_direction_output(pin, 0);
 492         }
 493 }
 494
 495 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
 496 {
 497         int delay;
 498
 499         delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
 500         return (delay > 30) ? 30 : delay;
 501 }
 502
 503 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 504 {
 505         struct sunxi_lcdc_reg * const lcdc =
 506                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 507         int bp, clk_delay, clk_div, clk_double, pin, total, val;
 508
 509         for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 510                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
 511
 512         sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 513
 514         /* Use tcon0 */
 515         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 516                         SUNXI_LCDC_CTRL_IO_MAP_TCON0);
 517
 518         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 519         writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
 520                SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
 521
 522         writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
 523                SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
 524
 525         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 526                &lcdc->tcon0_timing_active);
 527
 528         bp = mode->hsync_len + mode->left_margin;
 529         total = mode->xres + mode->right_margin + bp;
 530         writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
 531                SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
 532
 533         bp = mode->vsync_len + mode->upper_margin;
 534         total = mode->yres + mode->lower_margin + bp;
 535         writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
 536                SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
 537
 538         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 539                &lcdc->tcon0_timing_sync);
 540
 541         /* We only support hv-sync parallel lcd-s for now */
 542         writel(0, &lcdc->tcon0_hv_intf);
 543         writel(0, &lcdc->tcon0_cpu_intf);
 544
 545         if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
 546                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
 547                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
 548                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
 549                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
 550                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
 551                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
 552                 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
 553                 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
 554                 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
 555                 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
 556                 writel(((sunxi_display.depth == 18) ?
 557                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
 558                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
 559                        &lcdc->tcon0_frm_ctrl);
 560         }
 561
 562         val = 0;
 563         if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 564                 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 565         if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
 566                 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 567         writel(val, &lcdc->tcon0_io_polarity);
 568
 569         writel(0, &lcdc->tcon0_io_tristate);
 570 }
 571
 572 #ifdef CONFIG_VIDEO_HDMI
 573
 574 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 575                                       int *clk_div, int *clk_double,
 576                                       bool use_portd_hvsync)
 577 {
 578         struct sunxi_lcdc_reg * const lcdc =
 579                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 580         int bp, clk_delay, total, val;
 581
 582         /* Use tcon1 */
 583         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 584                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 585
 586         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 587         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 588                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
 589
 590         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 591                &lcdc->tcon1_timing_source);
 592         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 593                &lcdc->tcon1_timing_scale);
 594         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 595                &lcdc->tcon1_timing_out);
 596
 597         bp = mode->hsync_len + mode->left_margin;
 598         total = mode->xres + mode->right_margin + bp;
 599         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 600                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 601
 602         bp = mode->vsync_len + mode->upper_margin;
 603         total = mode->yres + mode->lower_margin + bp;
 604         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 605                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 606
 607         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 608                &lcdc->tcon1_timing_sync);
 609
 610         if (use_portd_hvsync) {
 611                 sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
 612                 sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
 613
 614                 val = 0;
 615                 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 616                         val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 617                 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 618                         val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 619                 writel(val, &lcdc->tcon1_io_polarity);
 620
 621                 clrbits_le32(&lcdc->tcon1_io_tristate,
 622                              SUNXI_LCDC_TCON_VSYNC_MASK |
 623                              SUNXI_LCDC_TCON_HSYNC_MASK);
 624         }
 625         sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 626 }
 627
 628 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 629 {
 630         struct sunxi_hdmi_reg * const hdmi =
 631                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 632         u8 checksum = 0;
 633         u8 avi_info_frame[17] = {
 634                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 635                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 636                 0x00
 637         };
 638         u8 vendor_info_frame[19] = {
 639                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 640                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 641                 0x00, 0x00, 0x00
 642         };
 643         int i;
 644
 645         if (mode->pixclock_khz <= 27000)
 646                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 647         else
 648                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 649
 650         if (mode->xres * 100 / mode->yres < 156)
 651                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 652         else
 653                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 654
 655         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 656                 checksum += avi_info_frame[i];
 657
 658         avi_info_frame[3] = 0x100 - checksum;
 659
 660         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 661                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 662
 663         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 664         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 665
 666         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 667                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 668
 669         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 670         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 671
 672         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 673 }
 674
 675 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 676                                 int clk_div, int clk_double)
 677 {
 678         struct sunxi_hdmi_reg * const hdmi =
 679                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 680         int x, y;
 681
 682         /* Write clear interrupt status bits */
 683         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 684
 685         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 686                 sunxi_hdmi_setup_info_frames(mode);
 687
 688         /* Set input sync enable */
 689         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 690
 691         /* Init various registers, select pll3 as clock source */
 692         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 693         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 694         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 695         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 696         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 697
 698         /* Setup clk div and doubler */
 699         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 700                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 701         if (!clk_double)
 702                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 703
 704         /* Setup timing registers */
 705         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 706                &hdmi->video_size);
 707
 708         x = mode->hsync_len + mode->left_margin;
 709         y = mode->vsync_len + mode->upper_margin;
 710         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 711
 712         x = mode->right_margin;
 713         y = mode->lower_margin;
 714         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 715
 716         x = mode->hsync_len;
 717         y = mode->vsync_len;
 718         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 719
 720         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 721                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 722
 723         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 724                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 725 }
 726
 727 static void sunxi_hdmi_enable(void)
 728 {
 729         struct sunxi_hdmi_reg * const hdmi =
 730                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 731
 732         udelay(100);
 733         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 734 }
 735
 736 #endif /* CONFIG_VIDEO_HDMI */
 737
 738 static void sunxi_drc_init(void)
 739 {
 740 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 741         struct sunxi_ccm_reg * const ccm =
 742                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 743
 744         /* On sun6i the drc must be clocked even when in pass-through mode */
 745         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 746         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 747 #endif
 748 }
 749
 750 static void sunxi_engines_init(void)
 751 {
 752         sunxi_composer_init();
 753         sunxi_lcdc_init();
 754         sunxi_drc_init();
 755 }
 756
 757 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 758                            unsigned int address)
 759 {
 760         switch (sunxi_display.monitor) {
 761         case sunxi_monitor_none:
 762                 break;
 763         case sunxi_monitor_dvi:
 764         case sunxi_monitor_hdmi: {
 765 #ifdef CONFIG_VIDEO_HDMI
 766                 int clk_div, clk_double;
 767                 sunxi_composer_mode_set(mode, address);
 768                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
 769                 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 770                 sunxi_composer_enable();
 771                 sunxi_lcdc_enable();
 772                 sunxi_hdmi_enable();
 773 #endif
 774                 }
 775                 break;
 776         case sunxi_monitor_lcd:
 777                 sunxi_lcdc_panel_enable();
 778                 sunxi_composer_mode_set(mode, address);
 779                 sunxi_lcdc_tcon0_mode_set(mode);
 780                 sunxi_composer_enable();
 781                 sunxi_lcdc_enable();
 782                 sunxi_lcdc_backlight_enable();
 783                 break;
 784         case sunxi_monitor_vga:
 785 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 786                 sunxi_composer_mode_set(mode, address);
 787                 sunxi_lcdc_tcon0_mode_set(mode);
 788                 sunxi_composer_enable();
 789                 sunxi_lcdc_enable();
 790 #endif
 791                 break;
 792         }
 793 }
 794
 795 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 796 {
 797         switch (monitor) {
 798         case sunxi_monitor_none:        return "none";
 799         case sunxi_monitor_dvi:         return "dvi";
 800         case sunxi_monitor_hdmi:        return "hdmi";
 801         case sunxi_monitor_lcd:         return "lcd";
 802         case sunxi_monitor_vga:         return "vga";
 803         }
 804         return NULL; /* never reached */
 805 }
 806
 807 void *video_hw_init(void)
 808 {
 809         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 810         const struct ctfb_res_modes *mode;
 811         struct ctfb_res_modes custom;
 812         const char *options;
 813 #ifdef CONFIG_VIDEO_HDMI
 814         int ret, hpd, edid;
 815 #endif
 816         char mon[16];
 817         char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
 818         int i;
 819
 820         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 821
 822         printf("Reserved %dkB of RAM for Framebuffer.\n",
 823                CONFIG_SUNXI_FB_SIZE >> 10);
 824         gd->fb_base = gd->ram_top;
 825
 826         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 827                                  &sunxi_display.depth, &options);
 828 #ifdef CONFIG_VIDEO_HDMI
 829         hpd = video_get_option_int(options, "hpd", 1);
 830         edid = video_get_option_int(options, "edid", 1);
 831         sunxi_display.monitor = sunxi_monitor_dvi;
 832 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 833         sunxi_display.monitor = sunxi_monitor_vga;
 834 #else
 835         sunxi_display.monitor = sunxi_monitor_lcd;
 836 #endif
 837         video_get_option_string(options, "monitor", mon, sizeof(mon),
 838                                 sunxi_get_mon_desc(sunxi_display.monitor));
 839         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 840                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 841                         sunxi_display.monitor = i;
 842                         break;
 843                 }
 844         }
 845         if (i > SUNXI_MONITOR_LAST)
 846                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 847                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 848
 849 #ifdef CONFIG_VIDEO_HDMI
 850         /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
 851         if (sunxi_display.monitor == sunxi_monitor_dvi ||
 852             sunxi_display.monitor == sunxi_monitor_hdmi) {
 853                 /* Always call hdp_detect, as it also enables clocks, etc. */
 854                 ret = sunxi_hdmi_hpd_detect();
 855                 if (ret) {
 856                         printf("HDMI connected: ");
 857                         if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
 858                                 mode = &custom;
 859                 } else if (hpd) {
 860                         sunxi_hdmi_shutdown();
 861                         /* Fallback to lcd / vga / none */
 862                         if (lcd_mode[0]) {
 863                                 sunxi_display.monitor = sunxi_monitor_lcd;
 864                         } else {
 865 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 866                                 sunxi_display.monitor = sunxi_monitor_vga;
 867 #else
 868                                 sunxi_display.monitor = sunxi_monitor_none;
 869 #endif
 870                         }
 871                 } /* else continue with hdmi/dvi without a cable connected */
 872         }
 873 #endif
 874
 875         switch (sunxi_display.monitor) {
 876         case sunxi_monitor_none:
 877                 return NULL;
 878         case sunxi_monitor_dvi:
 879         case sunxi_monitor_hdmi:
 880 #ifdef CONFIG_VIDEO_HDMI
 881                 break;
 882 #else
 883                 printf("HDMI/DVI not supported on this board\n");
 884                 sunxi_display.monitor = sunxi_monitor_none;
 885                 return NULL;
 886 #endif
 887         case sunxi_monitor_lcd:
 888                 if (lcd_mode[0]) {
 889                         sunxi_display.depth = video_get_params(&custom, lcd_mode);
 890                         mode = &custom;
 891                         break;
 892                 }
 893                 printf("LCD not supported on this board\n");
 894                 sunxi_display.monitor = sunxi_monitor_none;
 895                 return NULL;
 896         case sunxi_monitor_vga:
 897 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 898                 sunxi_display.depth = 18;
 899                 break;
 900 #else
 901                 printf("VGA not supported on this board\n");
 902                 sunxi_display.monitor = sunxi_monitor_none;
 903                 return NULL;
 904 #endif
 905         }
 906
 907         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 908                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 909                 mode = &res_mode_init[RES_MODE_1024x768];
 910         } else {
 911                 printf("Setting up a %dx%d %s console\n", mode->xres,
 912                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
 913         }
 914
 915         sunxi_engines_init();
 916         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 917
 918         /*
 919          * These are the only members of this structure that are used. All the
 920          * others are driver specific. There is nothing to decribe pitch or
 921          * stride, but we are lucky with our hw.
 922          */
 923         graphic_device->frameAdrs = gd->fb_base;
 924         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 925         graphic_device->gdfBytesPP = 4;
 926         graphic_device->winSizeX = mode->xres;
 927         graphic_device->winSizeY = mode->yres;
 928
 929         return graphic_device;
 930 }
 931
 932 /*
 933  * Simplefb support.
 934  */
 935 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 936 int sunxi_simplefb_setup(void *blob)
 937 {
 938         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 939         int offset, ret;
 940         const char *pipeline = NULL;
 941
 942         switch (sunxi_display.monitor) {
 943         case sunxi_monitor_none:
 944                 return 0;
 945         case sunxi_monitor_dvi:
 946         case sunxi_monitor_hdmi:
 947                 pipeline = "de_be0-lcd0-hdmi";
 948                 break;
 949         case sunxi_monitor_lcd:
 950                 pipeline = "de_be0-lcd0";
 951                 break;
 952         case sunxi_monitor_vga:
 953                 pipeline = "de_be0-lcd0";
 954                 break;
 955         }
 956
 957         /* Find a prefilled simpefb node, matching out pipeline config */
 958         offset = fdt_node_offset_by_compatible(blob, -1,
 959                                                "allwinner,simple-framebuffer");
 960         while (offset >= 0) {
 961                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 962                                       pipeline);
 963                 if (ret == 0)
 964                         break;
 965                 offset = fdt_node_offset_by_compatible(blob, offset,
 966                                                "allwinner,simple-framebuffer");
 967         }
 968         if (offset < 0) {
 969                 eprintf("Cannot setup simplefb: node not found\n");
 970                 return 0; /* Keep older kernels working */
 971         }
 972
 973         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 974                         graphic_device->winSizeX, graphic_device->winSizeY,
 975                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 976                         "x8r8g8b8");
 977         if (ret)
 978                 eprintf("Cannot setup simplefb: Error setting properties\n");
 979
 980         return ret;
 981 }
 982 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */