1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner DW HDMI bridge
5 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/lcdc.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <power/regulator.h>
24 struct sunxi_dw_hdmi_priv {
26 struct reset_ctl_bulk resets;
27 struct clk_bulk clocks;
31 struct sunxi_hdmi_phy {
46 #define HDMI_PHY_OFFS 0x10000
48 static int sunxi_dw_hdmi_get_divider(uint clock)
51 * Due to missing documentaion of HDMI PHY, we know correct
52 * settings only for following four PHY dividers. Select one
53 * based on clock speed.
55 if (clock <= 27000000)
57 else if (clock <= 74250000)
59 else if (clock <= 148500000)
65 static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
67 struct sunxi_hdmi_phy * const phy =
68 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
73 * HDMI PHY settings are taken as-is from Allwinner BSP code.
74 * There is no documentation.
76 writel(0, &phy->ctrl);
77 setbits_le32(&phy->ctrl, BIT(0));
79 setbits_le32(&phy->ctrl, BIT(16));
80 setbits_le32(&phy->ctrl, BIT(1));
82 setbits_le32(&phy->ctrl, BIT(2));
84 setbits_le32(&phy->ctrl, BIT(3));
86 setbits_le32(&phy->ctrl, BIT(19));
88 setbits_le32(&phy->ctrl, BIT(18));
89 setbits_le32(&phy->ctrl, 7 << 4);
91 /* Note that Allwinner code doesn't fail in case of timeout */
92 tmo = timer_get_us() + 2000;
93 while ((readl(&phy->status) & 0x80) == 0) {
94 if (timer_get_us() > tmo) {
95 printf("Warning: HDMI PHY init timeout!\n");
100 setbits_le32(&phy->ctrl, 0xf << 8);
101 setbits_le32(&phy->ctrl, BIT(7));
103 writel(0x39dc5040, &phy->pll);
104 writel(0x80084343, &phy->clk);
106 writel(1, &phy->unk3);
107 setbits_le32(&phy->pll, BIT(25));
109 tmp = (readl(&phy->status) & 0x1f800) >> 11;
110 setbits_le32(&phy->pll, BIT(31) | BIT(30));
111 setbits_le32(&phy->pll, tmp);
112 writel(0x01FF0F7F, &phy->ctrl);
113 writel(0x80639000, &phy->unk1);
114 writel(0x0F81C405, &phy->unk2);
116 /* enable read access to HDMI controller */
117 writel(0x54524545, &phy->read_en);
118 /* descramble register offsets */
119 writel(0x42494E47, &phy->unscramble);
122 static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
124 struct sunxi_hdmi_phy * const phy =
125 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
126 int div = sunxi_dw_hdmi_get_divider(clock);
130 * Unfortunately, we don't know much about those magic
131 * numbers. They are taken from Allwinner BSP driver.
135 writel(0x30dc5fc0, &phy->pll);
136 writel(0x800863C0 | (phy_div - 1), &phy->clk);
138 writel(0x00000001, &phy->unk3);
139 setbits_le32(&phy->pll, BIT(25));
141 tmp = (readl(&phy->status) & 0x1f800) >> 11;
142 setbits_le32(&phy->pll, BIT(31) | BIT(30));
144 setbits_le32(&phy->pll, tmp + 2);
146 setbits_le32(&phy->pll, 0x3f);
148 writel(0x01FFFF7F, &phy->ctrl);
149 writel(0x8063b000, &phy->unk1);
150 writel(0x0F8246B5, &phy->unk2);
153 writel(0x39dc5040, &phy->pll);
154 writel(0x80084380 | (phy_div - 1), &phy->clk);
156 writel(0x00000001, &phy->unk3);
157 setbits_le32(&phy->pll, BIT(25));
159 tmp = (readl(&phy->status) & 0x1f800) >> 11;
160 setbits_le32(&phy->pll, BIT(31) | BIT(30));
161 setbits_le32(&phy->pll, tmp);
162 writel(0x01FFFF7F, &phy->ctrl);
163 writel(0x8063a800, &phy->unk1);
164 writel(0x0F81C485, &phy->unk2);
167 writel(0x39dc5040, &phy->pll);
168 writel(0x80084340 | (phy_div - 1), &phy->clk);
170 writel(0x00000001, &phy->unk3);
171 setbits_le32(&phy->pll, BIT(25));
173 tmp = (readl(&phy->status) & 0x1f800) >> 11;
174 setbits_le32(&phy->pll, BIT(31) | BIT(30));
175 setbits_le32(&phy->pll, tmp);
176 writel(0x01FFFF7F, &phy->ctrl);
177 writel(0x8063b000, &phy->unk1);
178 writel(0x0F81C405, &phy->unk2);
181 writel(0x39dc5040, &phy->pll);
182 writel(0x80084300 | (phy_div - 1), &phy->clk);
184 writel(0x00000001, &phy->unk3);
185 setbits_le32(&phy->pll, BIT(25));
187 tmp = (readl(&phy->status) & 0x1f800) >> 11;
188 setbits_le32(&phy->pll, BIT(31) | BIT(30));
189 setbits_le32(&phy->pll, tmp);
190 writel(0x01FFFF7F, &phy->ctrl);
191 writel(0x8063b000, &phy->unk1);
192 writel(0x0F81C405, &phy->unk2);
197 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
199 int value, n, m, div, diff;
200 int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
203 * Find the lowest divider resulting in a matching clock. If there
204 * is no match, pick the closest lower clock, as monitors tend to
205 * not sync to higher frequencies.
207 for (div = 1; div <= 16; div++) {
208 int target = clk_khz * div;
215 for (m = 1; m <= 16; m++) {
216 n = (m * target) / 24000;
218 if (n >= 1 && n <= 128) {
219 value = (24000 * n) / m / div;
220 diff = clk_khz - value;
221 if (diff < best_diff) {
233 clock_set_pll3_factors(best_m, best_n);
234 debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
235 clk_khz, (clock_get_pll3() / 1000) / best_div,
236 best_n, best_m, best_div);
239 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
242 struct sunxi_ccm_reg * const ccm =
243 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
244 int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
245 struct sunxi_lcdc_reg *lcdc;
248 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
251 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
254 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
255 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
258 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
261 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
264 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
265 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
270 lcdc_tcon1_mode_set(lcdc, edid, false, false);
271 lcdc_enable(lcdc, bpp);
274 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
278 sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
279 sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
284 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
286 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
288 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
291 static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
292 const struct display_timing *timing)
294 return timing->pixelclock.typ <= 297000000;
297 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
298 const struct display_timing *edid)
300 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
301 struct sunxi_hdmi_phy * const phy =
302 (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
303 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
306 ret = dw_hdmi_enable(&priv->hdmi, edid);
310 sunxi_dw_hdmi_lcdc_init(uc_plat->source_id, edid, panel_bpp);
312 if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
313 setbits_le32(&phy->pol, 0x200);
315 if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
316 setbits_le32(&phy->pol, 0x100);
318 setbits_le32(&phy->ctrl, 0xf << 12);
321 * This is last hdmi access before boot, so scramble addresses
322 * again or othwerwise BSP driver won't work. Dummy read is
323 * needed or otherwise last write doesn't get written correctly.
325 (void)readb(priv->hdmi.ioaddr);
326 writel(0, &phy->unscramble);
331 static int sunxi_dw_hdmi_probe(struct udevice *dev)
333 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
334 struct sunxi_ccm_reg * const ccm =
335 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
339 regulator_set_enable(priv->hvcc, true);
341 /* Set pll3 to 297 MHz */
342 clock_set_pll3(297000000);
344 /* Set hdmi parent to pll3 */
345 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
348 /* This reset is referenced from the PHY devicetree node. */
349 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
351 ret = reset_deassert_bulk(&priv->resets);
355 ret = clk_enable_bulk(&priv->clocks);
359 sunxi_dw_hdmi_phy_init(&priv->hdmi);
361 ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
363 debug("hdmi can not get hpd signal\n");
367 dw_hdmi_init(&priv->hdmi);
372 static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
374 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
375 struct dw_hdmi *hdmi = &priv->hdmi;
378 hdmi->ioaddr = (ulong)dev_read_addr(dev);
379 hdmi->i2c_clk_high = 0xd8;
380 hdmi->i2c_clk_low = 0xfe;
381 hdmi->reg_io_width = 1;
382 hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
384 ret = reset_get_bulk(dev, &priv->resets);
388 ret = clk_get_bulk(dev, &priv->clocks);
392 ret = device_get_supply_regulator(dev, "hvcc-supply", &priv->hvcc);
399 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
400 .read_edid = sunxi_dw_hdmi_read_edid,
401 .enable = sunxi_dw_hdmi_enable,
402 .mode_valid = sunxi_dw_hdmi_mode_valid,
405 static const struct udevice_id sunxi_dw_hdmi_ids[] = {
406 { .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
410 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
411 .name = "sunxi_dw_hdmi",
412 .id = UCLASS_DISPLAY,
413 .of_match = sunxi_dw_hdmi_ids,
414 .probe = sunxi_dw_hdmi_probe,
415 .of_to_plat = sunxi_dw_hdmi_of_to_plat,
416 .priv_auto = sizeof(struct sunxi_dw_hdmi_priv),
417 .ops = &sunxi_dw_hdmi_ops,