1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner DW HDMI bridge
5 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/lcdc.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
23 struct sunxi_dw_hdmi_priv {
25 struct reset_ctl_bulk resets;
26 struct clk_bulk clocks;
29 struct sunxi_hdmi_phy {
44 #define HDMI_PHY_OFFS 0x10000
46 static int sunxi_dw_hdmi_get_divider(uint clock)
49 * Due to missing documentaion of HDMI PHY, we know correct
50 * settings only for following four PHY dividers. Select one
51 * based on clock speed.
53 if (clock <= 27000000)
55 else if (clock <= 74250000)
57 else if (clock <= 148500000)
63 static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
65 struct sunxi_hdmi_phy * const phy =
66 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
71 * HDMI PHY settings are taken as-is from Allwinner BSP code.
72 * There is no documentation.
74 writel(0, &phy->ctrl);
75 setbits_le32(&phy->ctrl, BIT(0));
77 setbits_le32(&phy->ctrl, BIT(16));
78 setbits_le32(&phy->ctrl, BIT(1));
80 setbits_le32(&phy->ctrl, BIT(2));
82 setbits_le32(&phy->ctrl, BIT(3));
84 setbits_le32(&phy->ctrl, BIT(19));
86 setbits_le32(&phy->ctrl, BIT(18));
87 setbits_le32(&phy->ctrl, 7 << 4);
89 /* Note that Allwinner code doesn't fail in case of timeout */
90 tmo = timer_get_us() + 2000;
91 while ((readl(&phy->status) & 0x80) == 0) {
92 if (timer_get_us() > tmo) {
93 printf("Warning: HDMI PHY init timeout!\n");
98 setbits_le32(&phy->ctrl, 0xf << 8);
99 setbits_le32(&phy->ctrl, BIT(7));
101 writel(0x39dc5040, &phy->pll);
102 writel(0x80084343, &phy->clk);
104 writel(1, &phy->unk3);
105 setbits_le32(&phy->pll, BIT(25));
107 tmp = (readl(&phy->status) & 0x1f800) >> 11;
108 setbits_le32(&phy->pll, BIT(31) | BIT(30));
109 setbits_le32(&phy->pll, tmp);
110 writel(0x01FF0F7F, &phy->ctrl);
111 writel(0x80639000, &phy->unk1);
112 writel(0x0F81C405, &phy->unk2);
114 /* enable read access to HDMI controller */
115 writel(0x54524545, &phy->read_en);
116 /* descramble register offsets */
117 writel(0x42494E47, &phy->unscramble);
120 static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
122 struct sunxi_hdmi_phy * const phy =
123 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
124 int div = sunxi_dw_hdmi_get_divider(clock);
128 * Unfortunately, we don't know much about those magic
129 * numbers. They are taken from Allwinner BSP driver.
133 writel(0x30dc5fc0, &phy->pll);
134 writel(0x800863C0 | (phy_div - 1), &phy->clk);
136 writel(0x00000001, &phy->unk3);
137 setbits_le32(&phy->pll, BIT(25));
139 tmp = (readl(&phy->status) & 0x1f800) >> 11;
140 setbits_le32(&phy->pll, BIT(31) | BIT(30));
142 setbits_le32(&phy->pll, tmp + 2);
144 setbits_le32(&phy->pll, 0x3f);
146 writel(0x01FFFF7F, &phy->ctrl);
147 writel(0x8063b000, &phy->unk1);
148 writel(0x0F8246B5, &phy->unk2);
151 writel(0x39dc5040, &phy->pll);
152 writel(0x80084380 | (phy_div - 1), &phy->clk);
154 writel(0x00000001, &phy->unk3);
155 setbits_le32(&phy->pll, BIT(25));
157 tmp = (readl(&phy->status) & 0x1f800) >> 11;
158 setbits_le32(&phy->pll, BIT(31) | BIT(30));
159 setbits_le32(&phy->pll, tmp);
160 writel(0x01FFFF7F, &phy->ctrl);
161 writel(0x8063a800, &phy->unk1);
162 writel(0x0F81C485, &phy->unk2);
165 writel(0x39dc5040, &phy->pll);
166 writel(0x80084340 | (phy_div - 1), &phy->clk);
168 writel(0x00000001, &phy->unk3);
169 setbits_le32(&phy->pll, BIT(25));
171 tmp = (readl(&phy->status) & 0x1f800) >> 11;
172 setbits_le32(&phy->pll, BIT(31) | BIT(30));
173 setbits_le32(&phy->pll, tmp);
174 writel(0x01FFFF7F, &phy->ctrl);
175 writel(0x8063b000, &phy->unk1);
176 writel(0x0F81C405, &phy->unk2);
179 writel(0x39dc5040, &phy->pll);
180 writel(0x80084300 | (phy_div - 1), &phy->clk);
182 writel(0x00000001, &phy->unk3);
183 setbits_le32(&phy->pll, BIT(25));
185 tmp = (readl(&phy->status) & 0x1f800) >> 11;
186 setbits_le32(&phy->pll, BIT(31) | BIT(30));
187 setbits_le32(&phy->pll, tmp);
188 writel(0x01FFFF7F, &phy->ctrl);
189 writel(0x8063b000, &phy->unk1);
190 writel(0x0F81C405, &phy->unk2);
195 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
197 int value, n, m, div, diff;
198 int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
201 * Find the lowest divider resulting in a matching clock. If there
202 * is no match, pick the closest lower clock, as monitors tend to
203 * not sync to higher frequencies.
205 for (div = 1; div <= 16; div++) {
206 int target = clk_khz * div;
213 for (m = 1; m <= 16; m++) {
214 n = (m * target) / 24000;
216 if (n >= 1 && n <= 128) {
217 value = (24000 * n) / m / div;
218 diff = clk_khz - value;
219 if (diff < best_diff) {
231 clock_set_pll3_factors(best_m, best_n);
232 debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
233 clk_khz, (clock_get_pll3() / 1000) / best_div,
234 best_n, best_m, best_div);
237 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
240 struct sunxi_ccm_reg * const ccm =
241 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
242 int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
243 struct sunxi_lcdc_reg *lcdc;
246 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
249 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
252 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
253 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
256 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
259 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
262 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
263 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
268 lcdc_tcon1_mode_set(lcdc, edid, false, false);
269 lcdc_enable(lcdc, bpp);
272 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
276 sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
277 sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
282 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
284 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
286 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
289 static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
290 const struct display_timing *timing)
292 return timing->pixelclock.typ <= 297000000;
295 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
296 const struct display_timing *edid)
298 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
299 struct sunxi_hdmi_phy * const phy =
300 (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
301 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
304 ret = dw_hdmi_enable(&priv->hdmi, edid);
308 sunxi_dw_hdmi_lcdc_init(uc_plat->source_id, edid, panel_bpp);
310 if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
311 setbits_le32(&phy->pol, 0x200);
313 if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
314 setbits_le32(&phy->pol, 0x100);
316 setbits_le32(&phy->ctrl, 0xf << 12);
319 * This is last hdmi access before boot, so scramble addresses
320 * again or othwerwise BSP driver won't work. Dummy read is
321 * needed or otherwise last write doesn't get written correctly.
323 (void)readb(priv->hdmi.ioaddr);
324 writel(0, &phy->unscramble);
329 static int sunxi_dw_hdmi_probe(struct udevice *dev)
331 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
332 struct sunxi_ccm_reg * const ccm =
333 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
336 /* Set pll3 to 297 MHz */
337 clock_set_pll3(297000000);
339 /* Set hdmi parent to pll3 */
340 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
343 /* This reset is referenced from the PHY devicetree node. */
344 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
346 ret = reset_deassert_bulk(&priv->resets);
350 ret = clk_enable_bulk(&priv->clocks);
354 sunxi_dw_hdmi_phy_init(&priv->hdmi);
356 ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
358 debug("hdmi can not get hpd signal\n");
362 dw_hdmi_init(&priv->hdmi);
367 static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
369 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
370 struct dw_hdmi *hdmi = &priv->hdmi;
373 hdmi->ioaddr = (ulong)dev_read_addr(dev);
374 hdmi->i2c_clk_high = 0xd8;
375 hdmi->i2c_clk_low = 0xfe;
376 hdmi->reg_io_width = 1;
377 hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
379 ret = reset_get_bulk(dev, &priv->resets);
383 ret = clk_get_bulk(dev, &priv->clocks);
390 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
391 .read_edid = sunxi_dw_hdmi_read_edid,
392 .enable = sunxi_dw_hdmi_enable,
393 .mode_valid = sunxi_dw_hdmi_mode_valid,
396 static const struct udevice_id sunxi_dw_hdmi_ids[] = {
397 { .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
401 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
402 .name = "sunxi_dw_hdmi",
403 .id = UCLASS_DISPLAY,
404 .of_match = sunxi_dw_hdmi_ids,
405 .probe = sunxi_dw_hdmi_probe,
406 .of_to_plat = sunxi_dw_hdmi_of_to_plat,
407 .priv_auto = sizeof(struct sunxi_dw_hdmi_priv),
408 .ops = &sunxi_dw_hdmi_ops,