drivers/video/sunxi/sunxi_dw_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Allwinner DW HDMI bridge
   4  *
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <dw_hdmi.h>
  13 #include <edid.h>
  14 #include <log.h>
  15 #include <reset.h>
  16 #include <time.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/lcdc.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22
  23 struct sunxi_dw_hdmi_priv {
  24         struct dw_hdmi hdmi;
  25         struct reset_ctl_bulk resets;
  26         struct clk_bulk clocks;
  27 };
  28
  29 struct sunxi_hdmi_phy {
  30         u32 pol;
  31         u32 res1[3];
  32         u32 read_en;
  33         u32 unscramble;
  34         u32 res2[2];
  35         u32 ctrl;
  36         u32 unk1;
  37         u32 unk2;
  38         u32 pll;
  39         u32 clk;
  40         u32 unk3;
  41         u32 status;
  42 };
  43
  44 #define HDMI_PHY_OFFS 0x10000
  45
  46 static int sunxi_dw_hdmi_get_divider(uint clock)
  47 {
  48         /*
  49          * Due to missing documentaion of HDMI PHY, we know correct
  50          * settings only for following four PHY dividers. Select one
  51          * based on clock speed.
  52          */
  53         if (clock <= 27000000)
  54                 return 11;
  55         else if (clock <= 74250000)
  56                 return 4;
  57         else if (clock <= 148500000)
  58                 return 2;
  59         else
  60                 return 1;
  61 }
  62
  63 static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
  64 {
  65         struct sunxi_hdmi_phy * const phy =
  66                 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
  67         unsigned long tmo;
  68         u32 tmp;
  69
  70         /*
  71          * HDMI PHY settings are taken as-is from Allwinner BSP code.
  72          * There is no documentation.
  73          */
  74         writel(0, &phy->ctrl);
  75         setbits_le32(&phy->ctrl, BIT(0));
  76         udelay(5);
  77         setbits_le32(&phy->ctrl, BIT(16));
  78         setbits_le32(&phy->ctrl, BIT(1));
  79         udelay(10);
  80         setbits_le32(&phy->ctrl, BIT(2));
  81         udelay(5);
  82         setbits_le32(&phy->ctrl, BIT(3));
  83         udelay(40);
  84         setbits_le32(&phy->ctrl, BIT(19));
  85         udelay(100);
  86         setbits_le32(&phy->ctrl, BIT(18));
  87         setbits_le32(&phy->ctrl, 7 << 4);
  88
  89         /* Note that Allwinner code doesn't fail in case of timeout */
  90         tmo = timer_get_us() + 2000;
  91         while ((readl(&phy->status) & 0x80) == 0) {
  92                 if (timer_get_us() > tmo) {
  93                         printf("Warning: HDMI PHY init timeout!\n");
  94                         break;
  95                 }
  96         }
  97
  98         setbits_le32(&phy->ctrl, 0xf << 8);
  99         setbits_le32(&phy->ctrl, BIT(7));
 100
 101         writel(0x39dc5040, &phy->pll);
 102         writel(0x80084343, &phy->clk);
 103         udelay(10000);
 104         writel(1, &phy->unk3);
 105         setbits_le32(&phy->pll, BIT(25));
 106         udelay(100000);
 107         tmp = (readl(&phy->status) & 0x1f800) >> 11;
 108         setbits_le32(&phy->pll, BIT(31) | BIT(30));
 109         setbits_le32(&phy->pll, tmp);
 110         writel(0x01FF0F7F, &phy->ctrl);
 111         writel(0x80639000, &phy->unk1);
 112         writel(0x0F81C405, &phy->unk2);
 113
 114         /* enable read access to HDMI controller */
 115         writel(0x54524545, &phy->read_en);
 116         /* descramble register offsets */
 117         writel(0x42494E47, &phy->unscramble);
 118 }
 119
 120 static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
 121 {
 122         struct sunxi_hdmi_phy * const phy =
 123                 (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 124         int div = sunxi_dw_hdmi_get_divider(clock);
 125         u32 tmp;
 126
 127         /*
 128          * Unfortunately, we don't know much about those magic
 129          * numbers. They are taken from Allwinner BSP driver.
 130          */
 131         switch (div) {
 132         case 1:
 133                 writel(0x30dc5fc0, &phy->pll);
 134                 writel(0x800863C0 | (phy_div - 1), &phy->clk);
 135                 mdelay(10);
 136                 writel(0x00000001, &phy->unk3);
 137                 setbits_le32(&phy->pll, BIT(25));
 138                 mdelay(200);
 139                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 140                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 141                 if (tmp < 0x3d)
 142                         setbits_le32(&phy->pll, tmp + 2);
 143                 else
 144                         setbits_le32(&phy->pll, 0x3f);
 145                 mdelay(100);
 146                 writel(0x01FFFF7F, &phy->ctrl);
 147                 writel(0x8063b000, &phy->unk1);
 148                 writel(0x0F8246B5, &phy->unk2);
 149                 break;
 150         case 2:
 151                 writel(0x39dc5040, &phy->pll);
 152                 writel(0x80084380 | (phy_div - 1), &phy->clk);
 153                 mdelay(10);
 154                 writel(0x00000001, &phy->unk3);
 155                 setbits_le32(&phy->pll, BIT(25));
 156                 mdelay(100);
 157                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 158                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 159                 setbits_le32(&phy->pll, tmp);
 160                 writel(0x01FFFF7F, &phy->ctrl);
 161                 writel(0x8063a800, &phy->unk1);
 162                 writel(0x0F81C485, &phy->unk2);
 163                 break;
 164         case 4:
 165                 writel(0x39dc5040, &phy->pll);
 166                 writel(0x80084340 | (phy_div - 1), &phy->clk);
 167                 mdelay(10);
 168                 writel(0x00000001, &phy->unk3);
 169                 setbits_le32(&phy->pll, BIT(25));
 170                 mdelay(100);
 171                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 172                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 173                 setbits_le32(&phy->pll, tmp);
 174                 writel(0x01FFFF7F, &phy->ctrl);
 175                 writel(0x8063b000, &phy->unk1);
 176                 writel(0x0F81C405, &phy->unk2);
 177                 break;
 178         case 11:
 179                 writel(0x39dc5040, &phy->pll);
 180                 writel(0x80084300 | (phy_div - 1), &phy->clk);
 181                 mdelay(10);
 182                 writel(0x00000001, &phy->unk3);
 183                 setbits_le32(&phy->pll, BIT(25));
 184                 mdelay(100);
 185                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 186                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 187                 setbits_le32(&phy->pll, tmp);
 188                 writel(0x01FFFF7F, &phy->ctrl);
 189                 writel(0x8063b000, &phy->unk1);
 190                 writel(0x0F81C405, &phy->unk2);
 191                 break;
 192         }
 193 }
 194
 195 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
 196 {
 197         int value, n, m, div, diff;
 198         int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
 199
 200         /*
 201          * Find the lowest divider resulting in a matching clock. If there
 202          * is no match, pick the closest lower clock, as monitors tend to
 203          * not sync to higher frequencies.
 204          */
 205         for (div = 1; div <= 16; div++) {
 206                 int target = clk_khz * div;
 207
 208                 if (target < 192000)
 209                         continue;
 210                 if (target > 912000)
 211                         continue;
 212
 213                 for (m = 1; m <= 16; m++) {
 214                         n = (m * target) / 24000;
 215
 216                         if (n >= 1 && n <= 128) {
 217                                 value = (24000 * n) / m / div;
 218                                 diff = clk_khz - value;
 219                                 if (diff < best_diff) {
 220                                         best_diff = diff;
 221                                         best_m = m;
 222                                         best_n = n;
 223                                         best_div = div;
 224                                 }
 225                         }
 226                 }
 227         }
 228
 229         *phy_div = best_div;
 230
 231         clock_set_pll3_factors(best_m, best_n);
 232         debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
 233               clk_khz, (clock_get_pll3() / 1000) / best_div,
 234               best_n, best_m, best_div);
 235 }
 236
 237 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
 238                                     int bpp)
 239 {
 240         struct sunxi_ccm_reg * const ccm =
 241                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 242         int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
 243         struct sunxi_lcdc_reg *lcdc;
 244
 245         if (mux == 0) {
 246                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 247
 248                 /* Reset off */
 249                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 250
 251                 /* Clock on */
 252                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 253                 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
 254                        &ccm->lcd0_clk_cfg);
 255         } else {
 256                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
 257
 258                 /* Reset off */
 259                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
 260
 261                 /* Clock on */
 262                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
 263                 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
 264                        &ccm->lcd1_clk_cfg);
 265         }
 266
 267         lcdc_init(lcdc);
 268         lcdc_tcon1_mode_set(lcdc, edid, false, false);
 269         lcdc_enable(lcdc, bpp);
 270 }
 271
 272 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 273 {
 274         int phy_div;
 275
 276         sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
 277         sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
 278
 279         return 0;
 280 }
 281
 282 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 283 {
 284         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 285
 286         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 287 }
 288
 289 static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
 290                                      const struct display_timing *timing)
 291 {
 292         return timing->pixelclock.typ <= 297000000;
 293 }
 294
 295 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 296                                 const struct display_timing *edid)
 297 {
 298         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 299         struct sunxi_hdmi_phy * const phy =
 300                 (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
 301         struct display_plat *uc_plat = dev_get_uclass_plat(dev);
 302         int ret;
 303
 304         ret = dw_hdmi_enable(&priv->hdmi, edid);
 305         if (ret)
 306                 return ret;
 307
 308         sunxi_dw_hdmi_lcdc_init(uc_plat->source_id, edid, panel_bpp);
 309
 310         if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
 311                 setbits_le32(&phy->pol, 0x200);
 312
 313         if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
 314                 setbits_le32(&phy->pol, 0x100);
 315
 316         setbits_le32(&phy->ctrl, 0xf << 12);
 317
 318         /*
 319          * This is last hdmi access before boot, so scramble addresses
 320          * again or othwerwise BSP driver won't work. Dummy read is
 321          * needed or otherwise last write doesn't get written correctly.
 322          */
 323         (void)readb(priv->hdmi.ioaddr);
 324         writel(0, &phy->unscramble);
 325
 326         return 0;
 327 }
 328
 329 static int sunxi_dw_hdmi_probe(struct udevice *dev)
 330 {
 331         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 332         struct sunxi_ccm_reg * const ccm =
 333                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 334         int ret;
 335
 336         /* Set pll3 to 297 MHz */
 337         clock_set_pll3(297000000);
 338
 339         /* Set hdmi parent to pll3 */
 340         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
 341                         CCM_HDMI_CTRL_PLL3);
 342
 343         /* This reset is referenced from the PHY devicetree node. */
 344         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
 345
 346         ret = reset_deassert_bulk(&priv->resets);
 347         if (ret)
 348                 return ret;
 349
 350         ret = clk_enable_bulk(&priv->clocks);
 351         if (ret)
 352                 return ret;
 353
 354         sunxi_dw_hdmi_phy_init(&priv->hdmi);
 355
 356         ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
 357         if (ret < 0) {
 358                 debug("hdmi can not get hpd signal\n");
 359                 return -1;
 360         }
 361
 362         dw_hdmi_init(&priv->hdmi);
 363
 364         return 0;
 365 }
 366
 367 static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
 368 {
 369         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 370         struct dw_hdmi *hdmi = &priv->hdmi;
 371         int ret;
 372
 373         hdmi->ioaddr = (ulong)dev_read_addr(dev);
 374         hdmi->i2c_clk_high = 0xd8;
 375         hdmi->i2c_clk_low = 0xfe;
 376         hdmi->reg_io_width = 1;
 377         hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
 378
 379         ret = reset_get_bulk(dev, &priv->resets);
 380         if (ret)
 381                 return ret;
 382
 383         ret = clk_get_bulk(dev, &priv->clocks);
 384         if (ret)
 385                 return ret;
 386
 387         return 0;
 388 }
 389
 390 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 391         .read_edid = sunxi_dw_hdmi_read_edid,
 392         .enable = sunxi_dw_hdmi_enable,
 393         .mode_valid = sunxi_dw_hdmi_mode_valid,
 394 };
 395
 396 static const struct udevice_id sunxi_dw_hdmi_ids[] = {
 397         { .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
 398         { }
 399 };
 400
 401 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 402         .name           = "sunxi_dw_hdmi",
 403         .id             = UCLASS_DISPLAY,
 404         .of_match       = sunxi_dw_hdmi_ids,
 405         .probe          = sunxi_dw_hdmi_probe,
 406         .of_to_plat     = sunxi_dw_hdmi_of_to_plat,
 407         .priv_auto      = sizeof(struct sunxi_dw_hdmi_priv),
 408         .ops            = &sunxi_dw_hdmi_ops,
 409 };