93383eba9c39f8167af8a5c0e312f4c42085bd92
[platform/kernel/u-boot.git] / drivers / video / sunxi / sunxi_de2.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Allwinner DE2 display driver
4  *
5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
6  */
7
8 #include <common.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <edid.h>
12 #include <efi_loader.h>
13 #include <fdtdec.h>
14 #include <fdt_support.h>
15 #include <part.h>
16 #include <video.h>
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/display2.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include "simplefb_common.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 enum {
28         /* Maximum LCD size we support */
29         LCD_MAX_WIDTH           = 3840,
30         LCD_MAX_HEIGHT          = 2160,
31         LCD_MAX_LOG2_BPP        = VIDEO_BPP32,
32 };
33
34 static void sunxi_de2_composer_init(void)
35 {
36         struct sunxi_ccm_reg * const ccm =
37                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
38
39 #ifdef CONFIG_MACH_SUN50I
40         u32 reg_value;
41
42         /* set SRAM for video use (A64 only) */
43         reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
44         reg_value &= ~(0x01 << 24);
45         writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
46 #endif
47
48         clock_set_pll10(432000000);
49
50         /* Set DE parent to pll10 */
51         clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
52                         CCM_DE2_CTRL_PLL10);
53
54         /* Set ahb gating to pass */
55         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
56         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
57
58         /* Clock on */
59         setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
60 }
61
62 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
63                                int bpp, ulong address, bool is_composite)
64 {
65         ulong de_mux_base = (mux == 0) ?
66                             SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
67         struct de_clk * const de_clk_regs =
68                 (struct de_clk *)(SUNXI_DE2_BASE);
69         struct de_glb * const de_glb_regs =
70                 (struct de_glb *)(de_mux_base +
71                                   SUNXI_DE2_MUX_GLB_REGS);
72         struct de_bld * const de_bld_regs =
73                 (struct de_bld *)(de_mux_base +
74                                   SUNXI_DE2_MUX_BLD_REGS);
75         struct de_ui * const de_ui_regs =
76                 (struct de_ui *)(de_mux_base +
77                                  SUNXI_DE2_MUX_CHAN_REGS +
78                                  SUNXI_DE2_MUX_CHAN_SZ * 1);
79         struct de_csc * const de_csc_regs =
80                 (struct de_csc *)(de_mux_base +
81                                   SUNXI_DE2_MUX_DCSC_REGS);
82         u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
83         int channel;
84         u32 format;
85
86         /* enable clock */
87 #ifdef CONFIG_MACH_SUN8I_H3
88         setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
89 #else
90         setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
91 #endif
92         setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
93         setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
94
95         clrbits_le32(&de_clk_regs->sel_cfg, 1);
96
97         writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
98         writel(0, &de_glb_regs->status);
99         writel(1, &de_glb_regs->dbuff);
100         writel(size, &de_glb_regs->size);
101
102         for (channel = 0; channel < 4; channel++) {
103                 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
104                                     SUNXI_DE2_MUX_CHAN_SZ * channel);
105                 memset(ch, 0, (channel == 0) ?
106                         sizeof(struct de_vi) : sizeof(struct de_ui));
107         }
108         memset(de_bld_regs, 0, sizeof(struct de_bld));
109
110         writel(0x00000101, &de_bld_regs->fcolor_ctl);
111
112         writel(1, &de_bld_regs->route);
113
114         writel(0, &de_bld_regs->premultiply);
115         writel(0xff000000, &de_bld_regs->bkcolor);
116
117         writel(0x03010301, &de_bld_regs->bld_mode[0]);
118
119         writel(size, &de_bld_regs->output_size);
120         writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
121                &de_bld_regs->out_ctl);
122         writel(0, &de_bld_regs->ck_ctl);
123
124         writel(0xff000000, &de_bld_regs->attr[0].fcolor);
125         writel(size, &de_bld_regs->attr[0].insize);
126
127         /* Disable all other units */
128         writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
129         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
130         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
131         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
132         writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
133         writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
134         writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
135         writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
136         writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
137         writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
138
139         if (is_composite) {
140                 /* set CSC coefficients */
141                 writel(0x107, &de_csc_regs->coef11);
142                 writel(0x204, &de_csc_regs->coef12);
143                 writel(0x64, &de_csc_regs->coef13);
144                 writel(0x4200, &de_csc_regs->coef14);
145                 writel(0x1f68, &de_csc_regs->coef21);
146                 writel(0x1ed6, &de_csc_regs->coef22);
147                 writel(0x1c2, &de_csc_regs->coef23);
148                 writel(0x20200, &de_csc_regs->coef24);
149                 writel(0x1c2, &de_csc_regs->coef31);
150                 writel(0x1e87, &de_csc_regs->coef32);
151                 writel(0x1fb7, &de_csc_regs->coef33);
152                 writel(0x20200, &de_csc_regs->coef34);
153
154                 /* enable CSC unit */
155                 writel(1, &de_csc_regs->csc_ctl);
156         } else {
157                 writel(0, &de_csc_regs->csc_ctl);
158         }
159
160         switch (bpp) {
161         case 16:
162                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
163                 break;
164         case 32:
165         default:
166                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
167                 break;
168         }
169
170         writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
171         writel(size, &de_ui_regs->cfg[0].size);
172         writel(0, &de_ui_regs->cfg[0].coord);
173         writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
174         writel(address, &de_ui_regs->cfg[0].top_laddr);
175         writel(size, &de_ui_regs->ovl_size);
176
177         /* apply settings */
178         writel(1, &de_glb_regs->dbuff);
179 }
180
181 static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
182                           enum video_log2_bpp l2bpp,
183                           struct udevice *disp, int mux, bool is_composite)
184 {
185         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
186         struct display_timing timing;
187         struct display_plat *disp_uc_plat;
188         int ret;
189
190         disp_uc_plat = dev_get_uclass_platdata(disp);
191         debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
192         if (display_in_use(disp)) {
193                 debug("   - device in use\n");
194                 return -EBUSY;
195         }
196
197         disp_uc_plat->source_id = mux;
198
199         ret = device_probe(disp);
200         if (ret) {
201                 debug("%s: device '%s' display won't probe (ret=%d)\n",
202                       __func__, dev->name, ret);
203                 return ret;
204         }
205
206         ret = display_read_timing(disp, &timing);
207         if (ret) {
208                 debug("%s: Failed to read timings\n", __func__);
209                 return ret;
210         }
211
212         sunxi_de2_composer_init();
213         sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
214
215         ret = display_enable(disp, 1 << l2bpp, &timing);
216         if (ret) {
217                 debug("%s: Failed to enable display\n", __func__);
218                 return ret;
219         }
220
221         uc_priv->xsize = timing.hactive.typ;
222         uc_priv->ysize = timing.vactive.typ;
223         uc_priv->bpix = l2bpp;
224         debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
225
226 #ifdef CONFIG_EFI_LOADER
227         efi_add_memory_map(fbbase,
228                            timing.hactive.typ * timing.vactive.typ *
229                            (1 << l2bpp) / 8,
230                            EFI_RESERVED_MEMORY_TYPE);
231 #endif
232
233         return 0;
234 }
235
236 static int sunxi_de2_probe(struct udevice *dev)
237 {
238         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
239         struct udevice *disp;
240         int ret;
241
242         /* Before relocation we don't need to do anything */
243         if (!(gd->flags & GD_FLG_RELOC))
244                 return 0;
245
246         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
247                                          "sunxi_lcd", &disp);
248         if (!ret) {
249                 int mux;
250
251                 mux = 0;
252
253                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
254                                      false);
255                 if (!ret) {
256                         video_set_flush_dcache(dev, 1);
257                         return 0;
258                 }
259         }
260
261         debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
262
263         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
264                                          "sunxi_dw_hdmi", &disp);
265         if (!ret) {
266                 int mux;
267                 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
268                         mux = 0;
269                 else
270                         mux = 1;
271
272                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
273                                      false);
274                 if (!ret) {
275                         video_set_flush_dcache(dev, 1);
276                         return 0;
277                 }
278         }
279
280         debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
281
282         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
283                                         "sunxi_tve", &disp);
284         if (ret) {
285                 debug("%s: tv not found (ret=%d)\n", __func__, ret);
286                 return ret;
287         }
288
289         ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
290         if (ret)
291                 return ret;
292
293         video_set_flush_dcache(dev, 1);
294
295         return 0;
296 }
297
298 static int sunxi_de2_bind(struct udevice *dev)
299 {
300         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
301
302         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
303                 (1 << LCD_MAX_LOG2_BPP) / 8;
304
305         return 0;
306 }
307
308 static const struct video_ops sunxi_de2_ops = {
309 };
310
311 U_BOOT_DRIVER(sunxi_de2) = {
312         .name   = "sunxi_de2",
313         .id     = UCLASS_VIDEO,
314         .ops    = &sunxi_de2_ops,
315         .bind   = sunxi_de2_bind,
316         .probe  = sunxi_de2_probe,
317         .flags  = DM_FLAG_PRE_RELOC,
318 };
319
320 U_BOOT_DEVICE(sunxi_de2) = {
321         .name = "sunxi_de2"
322 };
323
324 /*
325  * Simplefb support.
326  */
327 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
328 int sunxi_simplefb_setup(void *blob)
329 {
330         struct udevice *de2, *hdmi, *lcd;
331         struct video_priv *de2_priv;
332         struct video_uc_platdata *de2_plat;
333         int mux;
334         int offset, ret;
335         u64 start, size;
336         const char *pipeline = NULL;
337
338         debug("Setting up simplefb\n");
339
340         if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
341                 mux = 0;
342         else
343                 mux = 1;
344
345         /* Skip simplefb setting if DE2 / HDMI is not present */
346         ret = uclass_find_device_by_name(UCLASS_VIDEO,
347                                          "sunxi_de2", &de2);
348         if (ret) {
349                 debug("DE2 not present\n");
350                 return 0;
351         } else if (!device_active(de2)) {
352                 debug("DE2 present but not probed\n");
353                 return 0;
354         }
355
356         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
357                                          "sunxi_dw_hdmi", &hdmi);
358         if (ret) {
359                 debug("HDMI not present\n");
360         } else if (device_active(hdmi)) {
361                 if (mux == 0)
362                         pipeline = "mixer0-lcd0-hdmi";
363                 else
364                         pipeline = "mixer1-lcd1-hdmi";
365         } else {
366                 debug("HDMI present but not probed\n");
367         }
368
369         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
370                                          "sunxi_lcd", &lcd);
371         if (ret)
372                 debug("LCD not present\n");
373         else if (device_active(lcd))
374                 pipeline = "mixer0-lcd0";
375         else
376                 debug("LCD present but not probed\n");
377
378         if (!pipeline) {
379                 debug("No active display present\n");
380                 return 0;
381         }
382
383         de2_priv = dev_get_uclass_priv(de2);
384         de2_plat = dev_get_uclass_platdata(de2);
385
386         offset = sunxi_simplefb_fdt_match(blob, pipeline);
387         if (offset < 0) {
388                 eprintf("Cannot setup simplefb: node not found\n");
389                 return 0; /* Keep older kernels working */
390         }
391
392         start = gd->bd->bi_dram[0].start;
393         size = de2_plat->base - start;
394         ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
395         if (ret) {
396                 eprintf("Cannot setup simplefb: Error reserving memory\n");
397                 return ret;
398         }
399
400         ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
401                         de2_priv->xsize, de2_priv->ysize,
402                         VNBYTES(de2_priv->bpix) * de2_priv->xsize,
403                         "x8r8g8b8");
404         if (ret)
405                 eprintf("Cannot setup simplefb: Error setting properties\n");
406
407         return ret;
408 }
409 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */