2 * @file mipi_dsih_local.h
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3 * @brief instance context structure and enumerator definitions:
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4 * errors, events, color coding, video modes and driver state
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10 The Synopsys Software Driver and documentation (hereinafter "Software")
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11 is an unsupported proprietary work of Synopsys, Inc. unless otherwise
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12 expressly agreed to in writing between Synopsys and you.
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14 The Software IS NOT an item of Licensed Software or Licensed Product under
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15 any End User Software License Agreement or Agreement for Licensed Product
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16 with Synopsys or any supplement thereto. Permission is hereby granted,
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17 free of charge, to any person obtaining a copy of this software annotated
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18 with this license and the Software, to deal in the Software without
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19 restriction, including without limitation the rights to use, copy, modify,
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20 merge, publish, distribute, sublicense, and/or sell copies of the Software,
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21 and to permit persons to whom the Software is furnished to do so, subject
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22 to the following conditions:
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24 The above copyright notice and this permission notice shall be included in
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25 all copies or substantial portions of the Software.
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33 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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35 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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36 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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40 #ifndef MIPI_DSIH_LOCAL_H_
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41 #define MIPI_DSIH_LOCAL_H_
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43 //#include <stdint.h>
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45 #include "../sprdfb_chip_common.h"
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47 //typedef unsigned char uint8_t;
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48 //typedef unsigned short uint16_t;
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49 //typedef unsigned int uint32_t;
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51 #define DSIH_PIXEL_TOLERANCE 2
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52 #define DSIH_FIFO_ACTIVE_WAIT 500 /* no of tries to access the fifo*/
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53 #define DSIH_PHY_ACTIVE_WAIT (50000)
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54 #define ONE_MS_ACTIVE_WAIT (50000) /* 50MHz processor */
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55 #define DEFAULT_BYTE_CLOCK (432000) /* a value to start PHY PLL - random */
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56 #define MAX_NULL_SIZE (1023)
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57 #define FIFO_DEPTH (1096)
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58 #define WORD_LENGTH (4) /* bytes (32bit registers) */
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59 /** Define D-PHY type */
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60 #ifdef SPRD_MIPI_DPHY_GEN1
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61 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP 4 Lanes Gen 1 1GHz */
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62 #define DWC_MIPI_DPHY_BIDIR_TSMC40LP
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64 #ifdef SPRD_MIPI_DPHY_GEN2
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65 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP / GF28LP 4 Lanes Gen 2 1.5GHz */
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68 /** 4 Lanes Gen 2 1.5GHz testchips */
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70 /** TQL 2 Lane test chip */
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71 /* #define DPHY2Btql */
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74 * Errors generated by the DSI Host controller driver
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79 ERR_DSI_COLOR_CODING,
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80 ERR_DSI_OUT_OF_BOUND,
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82 ERR_DSI_INVALID_INSTANCE,
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84 ERR_DSI_CORE_INCOMPATIBLE,
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86 ERR_DSI_INVALID_COMMAND,
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87 ERR_DSI_INVALID_EVENT,
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88 ERR_DSI_INVALID_HANDLE,
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89 ERR_DSI_PHY_POWERUP,
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90 ERR_DSI_PHY_INVALID,
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91 ERR_DSI_PHY_FREQ_OUT_OF_BOUND,
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93 ERR_DSI_PHY_PLL_NOT_LOCKED,
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103 VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
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104 VIDEO_NON_BURST_WITH_SYNC_EVENTS,
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105 VIDEO_BURST_WITH_SYNC_PULSES
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109 * Color coding type (depth and pixel configuration)
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113 COLOR_CODE_16BIT_CONFIG1 = 0,
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114 COLOR_CODE_16BIT_CONFIG2 = 1,
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115 COLOR_CODE_16BIT_CONFIG3 = 2,
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116 COLOR_CODE_18BIT_CONFIG1 = 3,
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117 COLOR_CODE_18BIT_CONFIG2 = 4,
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118 COLOR_CODE_24BIT = 5,
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119 COLOR_CODE_20BIT_YCC422_LOOSELY = 6,
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120 COLOR_CODE_24BIT_YCC422 = 7,
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121 COLOR_CODE_16BIT_YCC422 = 8,
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122 COLOR_CODE_30BIT = 9,
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123 COLOR_CODE_36BIT = 10,
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124 COLOR_CODE_12BIT_YCC420 = 11,
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127 dsih_color_coding_t;
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129 * Events generated by the DSI Host controller
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136 ACK_ESCAPE_CMD_ERR,
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137 ACK_LP_TX_SYNC_ERR,
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138 ACK_HS_RX_TIMEOUT_ERR,
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139 ACK_FALSE_CONTROL_ERR,
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140 ACK_RSVD_DEVICE_ERR_7,
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141 ACK_ECC_SINGLE_BIT_ERR,
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142 ACK_ECC_MULTI_BIT_ERR,
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144 ACK_DSI_TYPE_NOT_RECOGNIZED_ERR,
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145 ACK_VC_ID_INVALID_ERR,
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146 ACK_INVALID_TX_LENGTH_ERR,
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147 ACK_RSVD_DEVICE_ERR_14,
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148 ACK_DSI_PROTOCOL_ERR,
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150 DPHY_ESC_ENTRY_ERR,
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151 DPHY_SYNC_ESC_LP_ERR,
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152 DPHY_CONTROL_LANE0_ERR,
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153 DPHY_CONTENTION_LP0_ERR,
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154 DPHY_CONTENTION_LP1_ERR,
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163 DPI_PLD_FIFO_FULL_ERR,
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164 GEN_TX_CMD_FIFO_FULL_ERR,
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165 GEN_TX_PLD_FIFO_FULL_ERR,
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166 GEN_TX_PLD_FIFO_EMPTY_ERR,
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167 GEN_RX_PLD_FIFO_EMPTY_ERR,
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168 GEN_RX_PLD_FIFO_FULL_ERR,
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170 DBI_TX_CMD_FIFO_FULL_ERR,
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171 DBI_TX_PLD_FIFO_FULL_ERR,
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172 DBI_RX_PLD_FIFO_EMPTY_ERR,
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173 DBI_RX_PLD_FIFO_FULL_ERR,
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174 DBI_ILLEGAL_CMD_ERR,
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179 * DSI Host state machine states
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180 * Holds the mapping of D-PHY to the OS, logging I/O, and hardware access layer.
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184 NOT_INITIALIZED = 0,
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193 * Holds the mapping of API to the OS, logging I/O, and hardware access layer
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194 * and HW module information.
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196 typedef struct dphy_t
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198 /** Physical base address of PHY module - REQUIRED */
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200 /** Reference frequency provided to PHY module [KHz] - REQUIRED */
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201 uint32_t reference_freq;
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202 /** D-PHY driver state - used internally by driver */
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203 dsih_state_t status;
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204 /** Function handle of any board function that needs to be called
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205 * in order to set up the environment for the D-PHY before it is
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207 void (*bsp_pre_config)(struct dphy_t *instance, void* param);
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208 /** Register read access function handle - REQUIRED */
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209 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
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210 /** Register write access function handle - REQUIRED */
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211 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
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212 /** Log errors function handle */
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213 void (*log_error)(const char * string);
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214 /** Log information function handle */
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215 void (*log_info)(const char *fmt, ...);
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220 * MIPI DSI Host Controller
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221 * Holds important information for the functioning of the DSI Host Controller API
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222 * Holds the mapping of API to the OS, logging I/O, and hardware access layer.
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223 * It also holds important information set by the user about the HW considerations
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224 * and internal state variables.
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226 typedef struct dsih_ctrl_t
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228 /** Physical base address of controller - REQUIRED */
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230 /** D-PHY instance associated with the DSI host controller - REQUIRED */
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231 dphy_t phy_instance;
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232 /**D-PHY frequency*/
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234 /** Number of lanes physically connected to controller - REQUIRED */
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236 /** Maximum number of byte clock cycles needed by the PHY to perform
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237 * the Bus Turn Around operation - REQUIRED */
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238 uint16_t max_bta_cycles;
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239 /** Describe the color mode pin (dpicolorm) whether it is active high or low - REQUIRED */
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240 int color_mode_polarity;
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241 /** Describe the shut down pin (dpishutdn) whether it is active high or low - REQUIRED */
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242 int shut_down_polarity;
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243 /** initialised or not */
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244 dsih_state_t status;
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245 /** Register read access function handle - REQUIRED */
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246 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
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247 /** Register write access function handle - REQUIRED */
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248 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
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249 /** Log errors function handle */
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250 void (*log_error)(const char * string);
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251 /** Log information function handle */
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252 void (*log_info)(const char *fmt, ...);
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253 /** Event registry holds handlers of the callbacks of registered events */
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254 void (*event_registry[DSI_MAX_EVENT])(struct dsih_ctrl_t *instance, void *handler);
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258 * Video configurations
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259 * Holds information about the video stream to be sent through the DPI interface.
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263 /** Number of lanes used to send current video */
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264 uint8_t no_of_lanes;
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265 /** Virtual channel number to send this video stream */
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266 uint8_t virtual_channel;
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267 /** Video mode, whether burst with sync pulses, or packets with either sync pulses or events */
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268 dsih_video_mode_t video_mode;
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269 /** Maximum number of byte clock cycles needed by the PHY to transition
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270 * the data lanes from high speed to low power - REQUIRED */
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271 uint8_t max_hs_to_lp_cycles;
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272 /** Maximum number of byte clock cycles needed by the PHY to transition
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273 * the data lanes from low power to high speed - REQUIRED */
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274 uint8_t max_lp_to_hs_cycles;
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275 /** Maximum number of byte clock cycles needed by the PHY to transition
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276 * the clock lane from high speed to low power - REQUIRED */
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277 uint8_t max_clk_hs_to_lp_cycles;
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278 /** Maximum number of byte clock cycles needed by the PHY to transition
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279 * the clock lane from low power to high speed - REQUIRED */
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280 uint8_t max_clk_lp_to_hs_cycles;
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281 /** Enable non coninuous clock for energy saving
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282 * - Clock lane will go to LS while not transmitting video */
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283 int non_continuous_clock;
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284 /** Enable receiving of ack packets */
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285 int receive_ack_packets;
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286 /** Byte (lane) clock [KHz] */
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287 uint32_t byte_clock;
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288 /** Pixel (DPI) Clock [KHz]*/
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289 uint32_t pixel_clock;
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290 /** Colour coding - BPP and Pixel configuration */
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291 dsih_color_coding_t color_coding;
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292 /** Is 18-bit loosely packets (valid only when BPP == 18) */
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294 /** Data enable signal (dpidaten) whether it is active high or low */
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295 int data_en_polarity;
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296 /** Horizontal synchronisation signal (dpihsync) whether it is active high or low */
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298 /** Horizontal resolution or Active Pixels */
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299 uint16_t h_active_pixels; /* hadr */
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300 /** Horizontal Sync Pixels - min 4 for best performance */
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301 uint16_t h_sync_pixels;
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302 /** Horizontal back porch pixels */
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303 uint16_t h_back_porch_pixels; /* hbp */
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304 /** Total Horizontal pixels */
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305 uint16_t h_total_pixels; /* h_total */
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306 /** Vertical synchronisation signal (dpivsync) whether it is active high or low */
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308 /** Vertical active lines (resolution) */
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309 uint16_t v_active_lines; /* vadr */
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310 /** Vertical sync lines */
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311 uint16_t v_sync_lines;
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312 /** Vertical back porch lines */
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313 uint16_t v_back_porch_lines; /* vbp */
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314 /** Total no of vertical lines */
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315 uint16_t v_total_lines; /* v_total */
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321 /** virtual channel */
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322 uint8_t virtual_channel;
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323 /** Commands to be sent in high speed or low power */
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325 /** Colour coding - BPP and Pixel configuration */
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326 dsih_color_coding_t color_coding;
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327 /** Top horizontal pixel position in the display */
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329 /** Horizontal resolution or Active Pixels */
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330 uint16_t h_active_pixels; /* hadr */
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331 /** Left most line position in the display */
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333 /** Vertical active lines (resolution) */
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334 uint16_t v_active_lines; /* vadr */
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335 /** Whether Tearing effect should be requested */
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337 /** packet size of write memory command -
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338 * 0 is default (optimum usage of RAM) */
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339 uint16_t packet_size;
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341 dsih_cmd_mode_video_t;
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343 * Register configurations
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347 /** Register offset */
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349 /** Register data [in or out] */
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354 #endif /* MIPI_DSIH_LOCAL_H_ */
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