2 * @file mipi_dsih_dphy.c
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3 * @brief D-PHY driver
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8 #include "mipi_dsih_dphy.h"
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9 #define PRECISION_FACTOR (1000)
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10 /* Reference clock frequency divided by Input Frequency Division Ratio LIMITS */
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11 #define DPHY_DIV_UPPER_LIMIT (40000)
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13 #define DPHY_DIV_LOWER_LIMIT (5000)
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15 #define DPHY_DIV_LOWER_LIMIT (1000)
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18 #if ((defined DWC_MIPI_DPHY_BIDIR_TSMC40LP) || (defined GEN_2))
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19 #define MIN_OUTPUT_FREQ (80)
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20 #elif defined DPHY2Btql
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21 #define MIN_OUTPUT_FREQ (200)
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26 * Initialise D-PHY module and power up
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27 * @param phy pointer to structure which holds information about the d-phy
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29 * @return error code
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31 dsih_error_t mipi_dsih_dphy_open(dphy_t * phy)
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35 return ERR_DSI_PHY_INVALID;
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37 else if ((phy->core_read_function == 0) || (phy->core_write_function == 0))
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39 return ERR_DSI_INVALID_IO;
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41 else if (phy->status == INITIALIZED)
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43 return ERR_DSI_PHY_INVALID;
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45 phy->status = NOT_INITIALIZED;
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47 mipi_dsih_dphy_reset(phy, 0);
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48 mipi_dsih_dphy_stop_wait_time(phy, 0x1C);
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49 mipi_dsih_dphy_no_of_lanes(phy, 1);
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50 mipi_dsih_dphy_clock_en(phy, 1);
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51 mipi_dsih_dphy_shutdown(phy, 1);
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52 mipi_dsih_dphy_reset(phy, 1);
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54 phy->status = INITIALIZED;
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58 * Configure D-PHY and PLL module to desired operation mode
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59 * @param phy pointer to structure which holds information about the d-phy
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61 * @param no_of_lanes active
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62 * @param output_freq desired high speed frequency
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63 * @return error code
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66 dsih_error_t mipi_dsih_dphy_configure(dphy_t * phy, uint8_t no_of_lanes, uint32_t output_freq)
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68 uint32_t loop_divider = 0; /* (M) */
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69 uint32_t input_divider = 1; /* (N) */
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70 uint8_t data[4]; /* maximum data for now are 4 bytes per test mode*/
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71 uint8_t no_of_bytes = 0;
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73 uint8_t n=0;/* iterator */
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74 uint8_t range = 0; /* ranges iterator */
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78 uint32_t loop_div; /* upper limit of loop divider range */
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79 uint8_t cp_current; /* icpctrl */
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80 uint8_t lpf_resistor; /* lpfctrl */
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84 { /* gen 2 associates the charge pump current and LPF resistor with the
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85 output frequency ranges (and thus we simplify here to use the
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86 counter/pointer of the following structure) */
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87 { 90, 0x02, 0x02}, { 100, 0x02, 0x02}, { 110, 0x02, 0x02},
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88 { 130, 0x02, 0x01}, { 140, 0x02, 0x01}, { 150, 0x02, 0x01},
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89 { 170, 0x09, 0x00}, { 180, 0x09, 0x01}, { 200, 0x09, 0x01},
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90 { 220, 0x09, 0x04}, { 240, 0x09, 0x04}, { 250, 0x09, 0x04},
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91 { 270, 0x06, 0x04}, { 300, 0x06, 0x04}, { 330, 0x09, 0x04},
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92 { 360, 0x09, 0x04}, { 400, 0x09, 0x04}, { 450, 0x06, 0x04},
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93 { 500, 0x06, 0x04}, { 550, 0x06, 0x04}, { 600, 0x06, 0x04},
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94 { 650, 0x0A, 0x04}, { 700, 0x0A, 0x04}, { 750, 0x0A, 0x04},
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95 { 800, 0x0A, 0x04}, { 850, 0x0A, 0x04}, { 900, 0x0A, 0x04},
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96 { 950, 0x0B, 0x08}, {1000, 0x0B, 0x08}, {1050, 0x0B, 0x08},
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97 {1100, 0x0B, 0x08}, {1150, 0x0B, 0x08}, {1200, 0x0B, 0x08},
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98 {1250, 0x0B, 0x08}, {1300, 0x0B, 0x08}, {1350, 0x0B, 0x08},
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99 {1400, 0x0B, 0x08}, {1450, 0x0B, 0x08}, {1500, 0x0B, 0x08}
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101 uint32_t delta = 0;
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102 uint32_t tmp_loop_divider = 0;
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107 uint32_t freq; /* upper margin of frequency range */
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108 uint8_t hs_freq; /* hsfreqrange */
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109 uint8_t vco_range; /* vcorange */
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113 { 90, 0x00, 0x00}, { 100, 0x10, 0x00}, { 110, 0x20, 0x00},
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114 { 130, 0x01, 0x00}, { 140, 0x11, 0x00}, { 150, 0x21, 0x00},
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115 { 170, 0x02, 0x00}, { 180, 0x12, 0x00}, { 200, 0x22, 0x00},
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116 { 220, 0x03, 0x01}, { 240, 0x13, 0x01}, { 250, 0x23, 0x01},
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117 { 270, 0x04, 0x01}, { 300, 0x14, 0x01}, { 330, 0x05, 0x02},
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118 { 360, 0x15, 0x02}, { 400, 0x25, 0x02}, { 450, 0x06, 0x02},
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119 { 500, 0x16, 0x02}, { 550, 0x07, 0x03}, { 600, 0x17, 0x03},
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120 { 650, 0x08, 0x03}, { 700, 0x18, 0x03}, { 750, 0x09, 0x04},
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121 { 800, 0x19, 0x04}, { 850, 0x29, 0x04}, { 900, 0x39, 0x04},
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122 { 950, 0x0A, 0x05}, {1000, 0x1A, 0x05}, {1050, 0x2A, 0x05},
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123 {1100, 0x3A, 0x05}, {1150, 0x0B, 0x06}, {1200, 0x1B, 0x06},
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124 {1250, 0x2B, 0x06}, {1300, 0x3B, 0x06}, {1350, 0x0C, 0x07},
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125 {1400, 0x1C, 0x07}, {1450, 0x2C, 0x07}, {1500, 0x3C, 0x07}
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130 return ERR_DSI_INVALID_INSTANCE;
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132 if (phy->status < INITIALIZED)
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134 return ERR_DSI_INVALID_INSTANCE;
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136 if (output_freq < MIN_OUTPUT_FREQ)
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138 return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
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141 loop_divider = ((output_freq * (phy->reference_freq / DPHY_DIV_LOWER_LIMIT)) / phy->reference_freq);
\r
142 /* here delta will account for the rounding */
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143 delta = ((loop_divider * phy->reference_freq) / (phy->reference_freq / DPHY_DIV_LOWER_LIMIT)) - output_freq;
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144 for (input_divider = 1 + (phy->reference_freq / DPHY_DIV_UPPER_LIMIT); ((phy->reference_freq / input_divider) >= DPHY_DIV_LOWER_LIMIT) && (!flag); input_divider++)
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146 tmp_loop_divider = ((output_freq * input_divider) / (phy->reference_freq));
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147 if ((tmp_loop_divider % 2) == 0)
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149 if (output_freq == (tmp_loop_divider * (phy->reference_freq / input_divider)))
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150 { /* exact values found */
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152 loop_divider = tmp_loop_divider;
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153 delta = output_freq - (tmp_loop_divider * (phy->reference_freq / input_divider));
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156 else if ((output_freq - (tmp_loop_divider * (phy->reference_freq / input_divider))) < delta)
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157 { /* values found with smaller delta */
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158 loop_divider = tmp_loop_divider;
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159 delta = output_freq - (tmp_loop_divider * (phy->reference_freq / input_divider));
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165 tmp_loop_divider += 1;
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166 if (output_freq == (tmp_loop_divider * (phy->reference_freq / input_divider)))
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167 { /* exact values found */
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169 loop_divider = tmp_loop_divider;
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170 delta = (tmp_loop_divider * (phy->reference_freq / input_divider)) - output_freq;
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173 else if (((tmp_loop_divider * (phy->reference_freq / input_divider)) - output_freq) < delta)
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174 { /* values found with smaller delta */
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175 loop_divider = tmp_loop_divider;
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176 delta = (tmp_loop_divider * (phy->reference_freq / input_divider)) - output_freq;
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183 input_divider = step + (loop_divider * phy->reference_freq) / output_freq;
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184 // phy->log_info("D-PHY: Approximated Frequency: %d KHz", (loop_divider * (phy->reference_freq / input_divider)));
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186 #ifdef CONFIG_FB_DYNAMIC_FREQ_SCALING
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187 if (phy->phy_keep_work != true)
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190 /* get the PHY in power down mode (shutdownz=0) and reset it (rstz=0) to
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191 avoid transient periods in PHY operation during re-configuration procedures. */
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192 mipi_dsih_dphy_reset(phy, 0);
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193 mipi_dsih_dphy_clock_en(phy, 0);
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194 mipi_dsih_dphy_shutdown(phy, 0);
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195 /* provide an initial active-high test clear pulse in TESTCLR */
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196 mipi_dsih_dphy_test_clear(phy, 1);
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197 mipi_dsih_dphy_test_clear(phy, 0);
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198 for(n=0;n<100;n++){
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203 for (range = 0; (range < (sizeof(ranges)/sizeof(ranges[0]))) && ((output_freq / 1000) > ranges[range].freq); range++)
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207 if (range >= (sizeof(ranges)/sizeof(ranges[0])))
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209 return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
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211 /* set up board depending on environment if any */
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212 if (phy->bsp_pre_config != 0)
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214 phy->bsp_pre_config(phy, 0);
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217 /* Jessica add - begin*/
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218 data[0] = 0x83;//0x44;//0x44;//0x40; //0x40: ok for 200 clock lane lpx /*about 52ns*/
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219 mipi_dsih_dphy_write(phy, 0x60, data, 1);
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220 // data[0] = 0x0; //0xA6;//0xC6;//0xC6;//0x86; //0x48: ok for 200 prepare time
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221 // mipi_dsih_dphy_write(phy, 0x61, data, 1);
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223 // data[0] = 0x0;//0x6a;//0x6a;//0x4a; //0x4a: ok for 200 zero time
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224 // mipi_dsih_dphy_write(phy, 0x62, data, 1);
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226 data[0] = 0x83;//0x44;//0x40;//0x40; // 0x40: ok for 200 data lane lpx /*about 52ns*/
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227 mipi_dsih_dphy_write(phy, 0x70, data, 1);
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229 // data[0] = 0x0;// 0x84;//0x96;//0x96;//0x86; //0x48: ok for 200 prepare time
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230 // mipi_dsih_dphy_write(phy, 0x71, data, 1);
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232 // data[0] = 0x0;//0x44;//0x44;//0x40; //0x4a: ok for 200 zero time
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233 // mipi_dsih_dphy_write(phy, 0x72, data, 1);
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236 //mipi_dsih_dphy_write(phy, 0x73, data, 1);
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239 //mipi_dsih_dphy_write(phy, 0x74, data, 1);
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241 /* Jessica add - end*/
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244 mipi_dsih_dphy_write(phy, 0x16, data, 1);
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246 /* setup digital part */
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247 /* hs frequency range [7]|[6:1]|[0]*/
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248 data[0] = (0 << 7) | (ranges[range].hs_freq << 1) | 0;
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249 //data[0] = (0 << 7) | (0x23 << 1) | 0;
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250 /*From ASIC, we need unmask this code to make the frequency correct*/
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251 mipi_dsih_dphy_write(phy, 0x44, data, 1); //Jessica remove for more accurate frequency
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253 /* vco range [7]|[6:3]|[2:1]|[0] */
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254 data[0] = (1 << 7) | (ranges[range].vco_range << 3) | (0 << 1) | 0;
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255 mipi_dsih_dphy_write(phy, 0x10, data, 1); //Jessica
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257 /* for all Gen2 testchips, bypass LP TX enable idle low power */
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259 mipi_dsih_dphy_write(phy, 0x32, data, 1);
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260 mipi_dsih_dphy_write(phy, 0x42, data, 1);
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261 mipi_dsih_dphy_write(phy, 0x52, data, 1);
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262 mipi_dsih_dphy_write(phy, 0x82, data, 1);
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263 mipi_dsih_dphy_write(phy, 0x92, data, 1);
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265 if ((loop_divider % 2) != 0)
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266 { /* only odd integers are allowed (1 will be subtracted upon writing,
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271 /* gen 2 associates the charge pump current and LPF resistor with the
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272 output frequency ranges (and thus we simplify here to use the
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273 counter/pointer of the following structure) */
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275 data[0] = (0x00 << 6) | (0x01 << 5) | (0x01 << 4);
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277 mipi_dsih_dphy_write(phy, 0x19, data, 1); //Jessica
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279 /* PLL Lock bypass|charge pump current [7:4]|[3:0] */
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280 data[0] = (0x00 << 4) | (loop_bandwidth[i].cp_current << 0);
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281 mipi_dsih_dphy_write(phy, 0x11, data, 1); //Jessica
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282 /* bypass CP default|bypass LPF default| LPF resistor [7]|[6]|[5:0] */
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283 data[0] = (0x01 << 7) | (0x01 << 6) |(loop_bandwidth[i].lpf_resistor << 0);
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284 mipi_dsih_dphy_write(phy, 0x12, data, 1);
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285 /* PLL input divider ratio [7:0] */
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286 data[0] = input_divider - 1;
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287 mipi_dsih_dphy_write(phy, 0x17, data, 1); //Jessica
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289 data[0] = 0x04; //short the delay time before BTA
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290 mipi_dsih_dphy_write(phy, 0x07, data, 1);
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293 // mipi_dsih_dphy_write(phy, 0xB0, data, 1);
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296 mipi_dsih_dphy_write(phy, 0x22, data, 1);
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297 // data[1] = mipi_dsih_dphy_test_data_out(phy);
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298 // printk("sprdfb:mipi dphy config-->0x22 write:%x,read:%x \n",data[0],data[1]);
\r
300 no_of_bytes = 2; /* pll loop divider (code 0x18) takes only 2 bytes (10 bits in data) */
\r
301 for (i = 0; i < no_of_bytes; i++)
\r
303 data[i] = ((uint8_t)((((loop_divider - 1) >> (5 * i)) & 0x1F) | (i << 7) ));
\r
304 /* 7 is dependent on no_of_bytes
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305 make sure 5 bits only of value are written at a time */
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307 /* PLL loop divider ratio - SET no|reserved|feedback divider [7]|[6:5]|[4:0] */
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308 mipi_dsih_dphy_write(phy, 0x18, data, no_of_bytes);
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309 mipi_dsih_dphy_no_of_lanes(phy, no_of_lanes);
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310 #ifdef CONFIG_FB_DYNAMIC_FREQ_SCALING
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311 if (phy->phy_keep_work != true)
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314 mipi_dsih_dphy_stop_wait_time(phy, 0x1C);
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315 mipi_dsih_dphy_clock_en(phy, 1);
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316 for(n=0;n<100;n++){
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319 mipi_dsih_dphy_shutdown(phy, 1);
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320 for(n=0;n<100;n++){
\r
323 mipi_dsih_dphy_reset(phy, 1);
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328 dsih_error_t mipi_dsih_dphy_configure(dphy_t * phy, uint8_t no_of_lanes, uint32_t output_freq)
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330 uint32_t loop_divider = 0; /* (M) */
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331 uint32_t input_divider = 1; /* (N) */
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332 uint8_t data[4]; /* maximum data for now are 4 bytes per test mode*/
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333 uint8_t no_of_bytes = 0;
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334 uint8_t i = 0; /* iterator */
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335 uint8_t n=0;/* iterator */
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336 uint8_t range = 0; /* ranges iterator */
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338 #ifdef DWC_MIPI_DPHY_BIDIR_TSMC40LP
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341 uint32_t freq; /* upper margin of frequency range */
\r
342 uint8_t hs_freq; /* hsfreqrange */
\r
343 uint8_t vco_range; /* vcorange */
\r
347 {90, 0x00, 0x01}, {100, 0x10, 0x01}, {110, 0x20, 0x01},
\r
348 {125, 0x01, 0x01}, {140, 0x11, 0x01}, {150, 0x21, 0x01},
\r
349 {160, 0x02, 0x01}, {180, 0x12, 0x03}, {200, 0x22, 0x03},
\r
350 {210, 0x03, 0x03}, {240, 0x13, 0x03}, {250, 0x23, 0x03},
\r
351 {270, 0x04, 0x07}, {300, 0x14, 0x07}, {330, 0x24, 0x07},
\r
352 {360, 0x15, 0x07}, {400, 0x25, 0x07}, {450, 0x06, 0x07},
\r
353 {500, 0x16, 0x07}, {550, 0x07, 0x0f}, {600, 0x17, 0x0f},
\r
354 {650, 0x08, 0x0f}, {700, 0x18, 0x0f}, {750, 0x09, 0x0f},
\r
355 {800, 0x19, 0x0f}, {850, 0x0A, 0x0f}, {900, 0x1A, 0x0f},
\r
356 {950, 0x2A, 0x0f}, {1000, 0x3A, 0x0f}
\r
360 uint32_t loop_div; /* upper limit of loop divider range */
\r
361 uint8_t cp_current; /* icpctrl */
\r
362 uint8_t lpf_resistor; /* lpfctrl */
\r
366 {32, 0x06, 0x10}, {64, 0x06, 0x10}, {128, 0x0C, 0x08},
\r
367 {256, 0x04, 0x04}, {512, 0x00, 0x01}, {768, 0x01, 0x01},
\r
370 #elif defined DPHY2Btql
\r
373 uint32_t loop_div; /* upper limit of loop divider range */
\r
374 uint8_t cp_current; /* icpctrl */
\r
375 uint8_t lpf_resistor; /* lpfctrl */
\r
379 {32, 0x0B, 0x00}, {64, 0x0A, 0x00}, {128, 0x09, 0x01},
\r
380 {256, 0x08, 0x03}, {512, 0x08, 0x07}, {768, 0x08, 0x0F},
\r
386 return ERR_DSI_INVALID_INSTANCE;
\r
388 if (phy->status < INITIALIZED)
\r
390 return ERR_DSI_INVALID_INSTANCE;
\r
392 if (output_freq < MIN_OUTPUT_FREQ)
\r
394 return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
\r
396 /* find M and N dividers */
\r
397 for (input_divider = 1 + (phy->reference_freq / DPHY_DIV_UPPER_LIMIT); ((phy->reference_freq / input_divider) >= DPHY_DIV_LOWER_LIMIT) && (!flag); input_divider++)
\r
398 { /* here the >= DPHY_DIV_LOWER_LIMIT is a phy constraint, formula should be above 1 MHz */
\r
399 if (((output_freq * input_divider) % (phy->reference_freq )) == 0)
\r
400 { /* values found */
\r
401 loop_divider = ((output_freq * input_divider) / (phy->reference_freq ));
\r
402 if (loop_divider >= 12)
\r
408 if ((!flag) || ((phy->reference_freq / input_divider) < DPHY_DIV_LOWER_LIMIT))
\r
409 { /* no exact value found in previous for loop */
\r
410 /* this solution is not favourable as jitter would be maximum */
\r
411 loop_divider = output_freq / DPHY_DIV_LOWER_LIMIT;
\r
412 input_divider = phy->reference_freq / DPHY_DIV_LOWER_LIMIT;
\r
415 { /* variable was incremented before exiting the loop */
\r
418 for (i = 0; (i < (sizeof(loop_bandwidth)/sizeof(loop_bandwidth[0]))) && (loop_divider > loop_bandwidth[i].loop_div); i++)
\r
422 if (i >= (sizeof(loop_bandwidth)/sizeof(loop_bandwidth[0])))
\r
424 return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
\r
426 printk("sprdfb: Gen1 D-PHY: Approximated Frequency: %d KHz\n", (loop_divider * (phy->reference_freq / input_divider)));
\r
427 #ifdef CONFIG_FB_DYNAMIC_FREQ_SCALING
\r
428 if (phy->phy_keep_work != true)
\r
431 /* get the PHY in power down mode (shutdownz=0) and reset it (rstz=0) to
\r
432 avoid transient periods in PHY operation during re-configuration procedures. */
\r
433 mipi_dsih_dphy_reset(phy, 0);
\r
434 mipi_dsih_dphy_clock_en(phy, 0);
\r
435 mipi_dsih_dphy_shutdown(phy, 0);
\r
436 /* provide an initial active-high test clear pulse in TESTCLR */
\r
437 mipi_dsih_dphy_test_clear(phy, 1);
\r
438 mipi_dsih_dphy_test_clear(phy, 0);
\r
440 #ifdef DWC_MIPI_DPHY_BIDIR_TSMC40LP
\r
442 for (range = 0; (range < (sizeof(ranges)/sizeof(ranges[0]))) && ((output_freq / 1000) > ranges[range].freq); range++)
\r
446 if (range >= (sizeof(ranges)/sizeof(ranges[0])))
\r
448 return ERR_DSI_PHY_FREQ_OUT_OF_BOUND;
\r
450 /* set up board depending on environment if any */
\r
451 if (phy->bsp_pre_config != 0)
\r
453 phy->bsp_pre_config(phy, 0);
\r
456 /* Jessica add - begin*/
\r
457 data[0] = 0x42;//0x44;//0x44;//0x40; //0x40: ok for 200 clock lane lpx /*about 52ns*/
\r
458 mipi_dsih_dphy_write(phy, 0x60, data, 1);
\r
459 data[0] = 0x0; //0xA6;//0xC6;//0xC6;//0x86; //0x48: ok for 200 prepare time
\r
460 mipi_dsih_dphy_write(phy, 0x61, data, 1);
\r
462 data[0] = 0x0;//0x6a;//0x6a;//0x4a; //0x4a: ok for 200 zero time
\r
463 mipi_dsih_dphy_write(phy, 0x62, data, 1);
\r
465 data[0] = 0x42;//0x44;//0x40;//0x40; // 0x40: ok for 200 data lane lpx /*about 52ns*/
\r
466 mipi_dsih_dphy_write(phy, 0x70, data, 1);
\r
468 data[0] = 0x0;// 0x84;//0x96;//0x96;//0x86; //0x48: ok for 200 prepare time
\r
469 mipi_dsih_dphy_write(phy, 0x71, data, 1);
\r
471 data[0] = 0x0;//0x44;//0x44;//0x40; //0x4a: ok for 200 zero time
\r
472 mipi_dsih_dphy_write(phy, 0x72, data, 1);
\r
475 //mipi_dsih_dphy_write(phy, 0x73, data, 1);
\r
478 //mipi_dsih_dphy_write(phy, 0x74, data, 1);
\r
480 /* Jessica add - end*/
\r
482 /* setup digital part */
\r
483 /* hs frequency range [7]|[6:1]|[0]*/
\r
484 data[0] = (0 << 7) | (ranges[range].hs_freq << 1) | 0;
\r
485 //data[0] = (0 << 7) | (0x23 << 1) | 0;
\r
486 /*From ASIC, we need unmask this code to make the frequency correct*/
\r
487 mipi_dsih_dphy_write(phy, 0x44, data, 1); //Jessica remove for more accurate frequency
\r
489 /* vco range [7]|[6:3]|[2:1]|[0] */
\r
490 data[0] = (1 << 7) | (ranges[range].vco_range << 3) | (0 << 1) | 0;
\r
491 mipi_dsih_dphy_write(phy, 0x10, data, 1); //Jessica
\r
492 /* PLL reserved|Input divider control|Loop Divider Control|Post Divider Ratio [7:6]|[5]|[4]|[3:0] */
\r
493 data[0] = (0x00 << 6) | (0x01 << 5) | (0x01 << 4) | (0x03 << 0); /* post divider default = 0x03 - it is only used for clock out 2*/
\r
494 mipi_dsih_dphy_write(phy, 0x19, data, 1); //Jessica
\r
495 #elif defined DPHY2Btql
\r
496 /* vco range [7:5]|[4]|[3]|[2:1]|[0] */
\r
497 data[0] = ((((output_freq / 1000) > 500 )? 1: 0) << 4) | (1 << 3) | (0 << 1) | 0;
\r
498 mipi_dsih_dphy_write(phy, 0x10, data, 1);
\r
500 /* PLL Lock bypass|charge pump current [7:4]|[3:0] */
\r
501 data[0] = (0x00 << 4) | (loop_bandwidth[i].cp_current << 0);
\r
502 mipi_dsih_dphy_write(phy, 0x11, data, 1); //Jessica
\r
503 /* bypass CP default|bypass LPF default| LPF resistor [7]|[6]|[5:0] */
\r
504 data[0] = (0x01 << 7) | (0x01 << 6) |(loop_bandwidth[i].lpf_resistor << 0);
\r
505 mipi_dsih_dphy_write(phy, 0x12, data, 1);
\r
506 /* PLL input divider ratio [7:0] */
\r
507 data[0] = input_divider - 1;
\r
508 mipi_dsih_dphy_write(phy, 0x17, data, 1); //Jessica
\r
510 data[0] = 0x04; //short the delay time before BTA
\r
511 mipi_dsih_dphy_write(phy, 0x07, data, 1);
\r
514 // mipi_dsih_dphy_write(phy, 0xB0, data, 1);
\r
517 mipi_dsih_dphy_write(phy, 0x22, data, 1);
\r
518 // data[1] = mipi_dsih_dphy_test_data_out(phy);
\r
519 // printk("sprdfb:mipi dphy config-->0x22 write:%x,read:%x \n",data[0],data[1]);
\r
521 no_of_bytes = 2; /* pll loop divider (code 0x18) takes only 2 bytes (10 bits in data) */
\r
522 for (i = 0; i < no_of_bytes; i++)
\r
524 data[i] = ((uint8_t)((((loop_divider - 1) >> (5 * i)) & 0x1F) | (i << 7) ));
\r
525 /* 7 is dependent on no_of_bytes
\r
526 make sure 5 bits only of value are written at a time */
\r
528 /* PLL loop divider ratio - SET no|reserved|feedback divider [7]|[6:5]|[4:0] */
\r
529 mipi_dsih_dphy_write(phy, 0x18, data, no_of_bytes);
\r
530 mipi_dsih_dphy_no_of_lanes(phy, no_of_lanes);
\r
531 #ifdef CONFIG_FB_DYNAMIC_FREQ_SCALING
\r
532 if (phy->phy_keep_work != true)
\r
535 mipi_dsih_dphy_stop_wait_time(phy, 0x1C);
\r
536 mipi_dsih_dphy_clock_en(phy, 1);
\r
537 for(n=0;n<100;n++){
\r
540 mipi_dsih_dphy_shutdown(phy, 1);
\r
541 for(n=0;n<100;n++){
\r
544 mipi_dsih_dphy_reset(phy, 1);
\r
550 * Close and power down D-PHY module
\r
551 * @param phy pointer to structure which holds information about the d-phy
\r
553 * @return error code
\r
555 dsih_error_t mipi_dsih_dphy_close(dphy_t * phy)
\r
559 return ERR_DSI_INVALID_INSTANCE;
\r
561 else if ((phy->core_read_function == 0) || (phy->core_write_function == 0))
\r
563 return ERR_DSI_INVALID_IO;
\r
565 if (phy->status < NOT_INITIALIZED)
\r
567 return ERR_DSI_INVALID_INSTANCE;
\r
569 mipi_dsih_dphy_reset(phy, 0);
\r
570 mipi_dsih_dphy_reset(phy, 1);
\r
571 mipi_dsih_dphy_shutdown(phy, 0);
\r
572 phy->status = NOT_INITIALIZED;
\r
576 * Enable clock lane module
\r
577 * @param instance pointer to structure which holds information about the d-phy
\r
581 void mipi_dsih_dphy_clock_en(dphy_t * instance, int en)
\r
583 mipi_dsih_dphy_write_part(instance, R_DPHY_RSTZ, en, 2, 1);
\r
586 * Reset D-PHY module
\r
587 * @param instance pointer to structure which holds information about the d-phy
\r
591 void mipi_dsih_dphy_reset(dphy_t * instance, int reset)
\r
593 mipi_dsih_dphy_write_part(instance, R_DPHY_RSTZ, reset, 1, 1);
\r
596 * Power up/down D-PHY module
\r
597 * @param instance pointer to structure which holds information about the d-phy
\r
599 * @param powerup (1) shutdown (0)
\r
601 void mipi_dsih_dphy_shutdown(dphy_t * instance, int powerup)
\r
603 mipi_dsih_dphy_write_part(instance, R_DPHY_RSTZ, powerup, 0, 1);
\r
606 * Force D-PHY PLL to stay on while in ULPS
\r
607 * @param instance pointer to structure which holds information about the d-phy
\r
609 * @param force (1) disable (0)
\r
610 * @note To follow the programming model, use wakeup_pll function
\r
612 void mipi_dsih_dphy_force_pll(dphy_t * instance, int force)
\r
614 mipi_dsih_dphy_write_part(instance, R_DPHY_RSTZ, force, 3, 1);
\r
617 * Get force D-PHY PLL module
\r
618 * @param instance pointer to structure which holds information about the d-phy
\r
620 * @return force value
\r
622 int mipi_dsih_dphy_get_force_pll(dphy_t * instance)
\r
624 return mipi_dsih_dphy_read_part(instance, R_DPHY_RSTZ, 3, 1);
\r
627 * Wake up or make sure D-PHY PLL module is awake
\r
628 * This function must be called after going into ULPS and before exiting it
\r
629 * to force the DPHY PLLs to wake up. It will wait until the DPHY status is
\r
630 * locked. It follows the procedure described in the user guide.
\r
631 * This function should be used to make sure the PLL is awake, rather than
\r
632 * the force_pll above.
\r
633 * @param instance pointer to structure which holds information about the d-phy
\r
635 * @return error code
\r
636 * @note this function has an active wait
\r
638 int mipi_dsih_dphy_wakeup_pll(dphy_t * instance)
\r
641 if (mipi_dsih_dphy_status(instance, 0x1) == 0)
\r
643 mipi_dsih_dphy_force_pll(instance, 1);
\r
644 for (i = 0; i < DSIH_PHY_ACTIVE_WAIT; i++)
\r
646 if(mipi_dsih_dphy_status(instance, 0x1))
\r
651 if (mipi_dsih_dphy_status(instance, 0x1) == 0)
\r
653 return ERR_DSI_PHY_PLL_NOT_LOCKED;
\r
659 * Configure minimum wait period for HS transmission request after a stop state
\r
660 * @param instance pointer to structure which holds information about the d-phy
\r
662 * @param no_of_byte_cycles [in byte (lane) clock cycles]
\r
664 void mipi_dsih_dphy_stop_wait_time(dphy_t * instance, uint8_t no_of_byte_cycles)
\r
666 mipi_dsih_dphy_write_part(instance, R_DPHY_IF_CFG, no_of_byte_cycles, 8, 8);
\r
669 * Set number of active lanes
\r
670 * @param instance pointer to structure which holds information about the d-phy
\r
672 * @param no_of_lanes
\r
674 void mipi_dsih_dphy_no_of_lanes(dphy_t * instance, uint8_t no_of_lanes)
\r
676 mipi_dsih_dphy_write_part(instance, R_DPHY_IF_CFG, no_of_lanes - 1, 0, 2);
\r
679 * Get number of currently active lanes
\r
680 * @param instance pointer to structure which holds information about the d-phy
\r
682 * @return number of active lanes
\r
684 uint8_t mipi_dsih_dphy_get_no_of_lanes(dphy_t * instance)
\r
686 return mipi_dsih_dphy_read_part(instance, R_DPHY_IF_CFG, 0, 2);
\r
691 * Set non-continuous clock mode
\r
692 * @param instance pointer to structure which holds information about the d-phy
\r
696 void mipi_dsih_dphy_enable_nc_clk(dphy_t * instance, int enable)
\r
698 mipi_dsih_dphy_write_part(instance, R_DPHY_LPCLK_CTRL, enable, 1, 1);
\r
702 * Request the PHY module to start transmission of high speed clock.
\r
703 * This causes the clock lane to start transmitting DDR clock on the
\r
704 * lane interconnect.
\r
705 * @param instance pointer to structure which holds information about the d-phy
\r
708 * @note this function should be called explicitly by user always except for
\r
711 void mipi_dsih_dphy_enable_hs_clk(dphy_t * instance, int enable)
\r
713 mipi_dsih_dphy_write_part(instance, R_DPHY_LPCLK_CTRL, enable, 0, 1);
\r
716 * One bit is asserted in the trigger_request (4bits) to cause the lane module
\r
717 * to cause the associated trigger to be sent across the lane interconnect.
\r
718 * The trigger request is synchronous with the rising edge of the clock.
\r
719 * @note: Only one bit of the trigger_request is asserted at any given time, the
\r
720 * remaining must be left set to 0, and only when not in LPDT or ULPS modes
\r
721 * @param instance pointer to structure which holds information about the d-phy
\r
723 * @param trigger_request 4 bit request
\r
725 dsih_error_t mipi_dsih_dphy_escape_mode_trigger(dphy_t * instance, uint8_t trigger_request)
\r
729 for (i = 0; i < 4; i++)
\r
731 sum += ((trigger_request >> i) & 1);
\r
734 { /* clear old trigger */
\r
735 mipi_dsih_dphy_write_part(instance, R_DPHY_TX_TRIGGERS, 0x00, 0, 4);
\r
736 mipi_dsih_dphy_write_part(instance, R_DPHY_TX_TRIGGERS, trigger_request, 0, 4);
\r
737 for (i = 0; i < DSIH_PHY_ACTIVE_WAIT; i++)
\r
739 if(mipi_dsih_dphy_status(instance, 0x0010))
\r
744 mipi_dsih_dphy_write_part(instance, R_DPHY_TX_TRIGGERS, 0x00, 0, 4);
\r
745 if (i >= DSIH_PHY_ACTIVE_WAIT)
\r
747 return ERR_DSI_TIMEOUT;
\r
751 return ERR_DSI_INVALID_COMMAND;
\r
754 * ULPS mode request/exit on all active data lanes.
\r
755 * @param instance pointer to structure which holds information about the d-phy
\r
757 * @param enable (request 1/ exit 0)
\r
758 * @return error code
\r
759 * @note this is a blocking function. wait upon exiting the ULPS will exceed 1ms
\r
762 dsih_error_t mipi_dsih_dphy_ulps_data_lanes(dphy_t * instance, int enable)
\r
765 /* mask 1 0101 0010 0000 */
\r
766 uint16_t data_lanes_mask = 0;
\r
769 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 1, 2, 1);
\r
774 if (mipi_dsih_dphy_status(instance, 0x1) == 0)
\r
776 return ERR_DSI_PHY_PLL_NOT_LOCKED;
\r
778 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 1, 3, 1);
\r
779 switch (mipi_dsih_dphy_get_no_of_lanes(instance))
\r
782 data_lanes_mask |= (1 << 12);
\r
784 data_lanes_mask |= (1 << 10);
\r
786 data_lanes_mask |= (1 << 8);
\r
788 data_lanes_mask |= (1 << 5);
\r
791 data_lanes_mask = 0;
\r
794 for (timeout = 0; timeout < DSIH_PHY_ACTIVE_WAIT; timeout++)
\r
795 { /* verify that the DPHY has left ULPM */
\r
797 if (mipi_dsih_dphy_status(instance, data_lanes_mask) == data_lanes_mask)
\r
801 /* wait at least 1ms */
\r
802 for (timeout = 0; timeout < ONE_MS_ACTIVE_WAIT; timeout++)
\r
807 if (mipi_dsih_dphy_status(instance, data_lanes_mask) != data_lanes_mask)
\r
809 instance->log_info("sprdfb: stat %x, mask %x", mipi_dsih_dphy_status(instance, data_lanes_mask), data_lanes_mask);
\r
810 return ERR_DSI_TIMEOUT;
\r
812 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 0, 2, 1);
\r
813 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 0, 3, 1);
\r
818 void mipi_dsih_dphy_ulps_data_lanes(dphy_t * instance, int enable)
\r
823 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 1, 3, 1);
\r
827 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 1, 4, 1);
\r
828 for (timeout = 0; timeout < DSIH_PHY_ACTIVE_WAIT; timeout++)
\r
829 { /* verify that the DPHY has left ULPM */
\r
830 /* mask 1010100100000 */
\r
831 if (mipi_dsih_dphy_status(instance, 0x1520) == 0)
\r
832 { /* wait at least 1ms */
\r
833 for (timeout = 0; timeout < ONE_MS_ACTIVE_WAIT; timeout++)
\r
840 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 0, 3, 1);
\r
841 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 0, 4, 1);
\r
846 * ULPS mode request/exit on Clock Lane.
\r
847 * @param instance pointer to structure which holds information about the
\r
849 * @param enable 1 or disable 0 of the Ultra Low Power State of the clock lane
\r
850 * @return error code
\r
851 * @note this is a blocking function. wait upon exiting the ULPS will exceed 1ms
\r
854 dsih_error_t mipi_dsih_dphy_ulps_clk_lane(dphy_t * instance, int enable)
\r
858 uint16_t clk_lane_mask = 0x0008;
\r
861 /* mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 0, 0, 1); */
\r
862 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 1, 0, 1);
\r
866 if (mipi_dsih_dphy_status(instance, 0x1) == 0)
\r
868 return ERR_DSI_PHY_PLL_NOT_LOCKED;
\r
870 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 1, 1, 1);
\r
871 for (timeout = 0; timeout < DSIH_PHY_ACTIVE_WAIT; timeout++)
\r
872 { /* verify that the DPHY has left ULPM */
\r
873 /* mask 1010100100000 */
\r
874 if (mipi_dsih_dphy_status(instance, clk_lane_mask) == clk_lane_mask)
\r
875 { /* wait at least 1ms */
\r
876 instance->log_info("sprdfb: stat %x, mask %x", mipi_dsih_dphy_status(instance, clk_lane_mask), clk_lane_mask);
\r
879 /* wait at least 1ms */
\r
880 for (timeout = 0; timeout < ONE_MS_ACTIVE_WAIT; timeout++)
\r
881 { /* dummy operation for the loop not to be optimised */
\r
882 enable = mipi_dsih_dphy_status(instance, clk_lane_mask);
\r
885 if (mipi_dsih_dphy_status(instance, clk_lane_mask) != clk_lane_mask)
\r
887 return ERR_DSI_TIMEOUT;
\r
889 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 0, 0, 1);
\r
890 mipi_dsih_dphy_write_part(instance, R_DPHY_ULPS_CTRL, 0, 1, 1);
\r
895 void mipi_dsih_dphy_ulps_clk_lane(dphy_t * instance, int enable)
\r
900 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 0, 0, 1);
\r
901 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 1, 1, 1);
\r
905 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 1, 2, 1);
\r
906 for (timeout = 0; timeout < DSIH_PHY_ACTIVE_WAIT; timeout++)
\r
907 { /* verify that the DPHY has left ULPM */
\r
908 /* mask 1010100100000 */
\r
909 if (mipi_dsih_dphy_status(instance, 0x0004) == 0)
\r
910 { /* wait at least 1ms */
\r
911 for (timeout = 0; timeout < ONE_MS_ACTIVE_WAIT; timeout++)
\r
918 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 0, 1, 1);
\r
919 mipi_dsih_dphy_write_part(instance, R_DSI_HOST_PHY_IF_CTRL, 0, 2, 1);
\r
924 * Get D-PHY PPI status
\r
925 * @param instance pointer to structure which holds information about the d-phy
\r
930 uint32_t mipi_dsih_dphy_status(dphy_t * instance, uint16_t mask)
\r
932 return mipi_dsih_dphy_read_word(instance, R_DPHY_STATUS) & mask;
\r
935 * @param instance pointer to structure which holds information about the d-phy
\r
939 void mipi_dsih_dphy_test_clock(dphy_t * instance, int value)
\r
941 mipi_dsih_dphy_write_part(instance, R_DPHY_TST_CRTL0, value, 1, 1);
\r
944 * @param instance pointer to structure which holds information about the d-phy
\r
948 void mipi_dsih_dphy_test_clear(dphy_t * instance, int value)
\r
950 mipi_dsih_dphy_write_part(instance, R_DPHY_TST_CRTL0, value, 0, 1);
\r
953 * @param instance pointer to structure which holds information about the d-phy
\r
955 * @param on_falling_edge
\r
957 void mipi_dsih_dphy_test_en(dphy_t * instance, uint8_t on_falling_edge)
\r
959 mipi_dsih_dphy_write_part(instance, R_DPHY_TST_CRTL1, on_falling_edge, 16, 1);
\r
962 * @param instance pointer to structure which holds information about the d-phy
\r
965 uint8_t mipi_dsih_dphy_test_data_out(dphy_t * instance)
\r
967 return mipi_dsih_dphy_read_part(instance, R_DPHY_TST_CRTL1, 8, 8);
\r
970 * @param instance pointer to structure which holds information about the d-phy
\r
974 void mipi_dsih_dphy_test_data_in(dphy_t * instance, uint8_t test_data)
\r
976 mipi_dsih_dphy_write_word(instance, R_DPHY_TST_CRTL1, test_data);
\r
979 * Write to D-PHY module (encapsulating the digital interface)
\r
980 * @param instance pointer to structure which holds information about the d-phy
\r
982 * @param address offset inside the D-PHY digital interface
\r
983 * @param data array of bytes to be written to D-PHY
\r
984 * @param data_length of the data array
\r
986 void mipi_dsih_dphy_write(dphy_t * instance, uint8_t address, uint8_t * data, uint8_t data_length)
\r
991 #if ((defined DWC_MIPI_DPHY_BIDIR_TSMC40LP) || (defined DPHY2Btql) || (defined GEN_2))
\r
992 /* set the TESTCLK input high in preparation to latch in the desired test mode */
\r
993 mipi_dsih_dphy_test_clock(instance, 1);
\r
994 /* set the desired test code in the input 8-bit bus TESTDIN[7:0] */
\r
995 mipi_dsih_dphy_test_data_in(instance, address);
\r
996 /* set TESTEN input high */
\r
997 mipi_dsih_dphy_test_en(instance, 1);
\r
998 /* drive the TESTCLK input low; the falling edge captures the chosen test code into the transceiver */
\r
999 mipi_dsih_dphy_test_clock(instance, 0);
\r
1000 /* set TESTEN input low to disable further test mode code latching */
\r
1001 mipi_dsih_dphy_test_en(instance, 0);
\r
1002 /* start writing MSB first */
\r
1003 for (i = data_length; i > 0; i--)
\r
1004 { /* set TESTDIN[7:0] to the desired test data appropriate to the chosen test mode */
\r
1005 mipi_dsih_dphy_test_data_in(instance, data[i - 1]);
\r
1006 /* pulse TESTCLK high to capture this test data into the macrocell; repeat these two steps as necessary */
\r
1007 mipi_dsih_dphy_test_clock(instance, 1);
\r
1008 mipi_dsih_dphy_test_clock(instance, 0);
\r
1016 /* abstracting BSP */
\r
1018 * Write to whole register to D-PHY module (encapsulating the bus interface)
\r
1019 * @param instance pointer to structure which holds information about the d-phy
\r
1021 * @param reg_address offset
\r
1022 * @param data 32-bit word
\r
1024 void mipi_dsih_dphy_write_word(dphy_t * instance, uint32_t reg_address, uint32_t data)
\r
1026 if (instance->core_write_function != 0)
\r
1028 instance->core_write_function(instance->address, reg_address, data);
\r
1032 * Write bit field to D-PHY module (encapsulating the bus interface)
\r
1033 * @param instance pointer to structure which holds information about the d-phy
\r
1035 * @param reg_address offset
\r
1036 * @param data bits to be written to D-PHY
\r
1037 * @param shift from the right hand side of the register (big endian)
\r
1038 * @param width of the bit field
\r
1040 void mipi_dsih_dphy_write_part(dphy_t * instance, uint32_t reg_address, uint32_t data, uint8_t shift, uint8_t width)
\r
1042 uint32_t mask = 0;
\r
1043 uint32_t temp = 0;
\r
1044 if (instance->core_read_function != 0)
\r
1046 mask = (1 << width) - 1;
\r
1047 temp = mipi_dsih_dphy_read_word(instance, reg_address);
\r
1048 temp &= ~(mask << shift);
\r
1049 temp |= (data & mask) << shift;
\r
1050 mipi_dsih_dphy_write_word(instance, reg_address, temp);
\r
1054 * Read whole register from D-PHY module (encapsulating the bus interface)
\r
1055 * @param instance pointer to structure which holds information about the d-phy
\r
1057 * @param reg_address offset
\r
1058 * @return data 32-bit word
\r
1060 uint32_t mipi_dsih_dphy_read_word(dphy_t * instance, uint32_t reg_address)
\r
1062 if (instance->core_read_function == 0)
\r
1064 return ERR_DSI_INVALID_IO;
\r
1066 return instance->core_read_function(instance->address, reg_address);
\r
1069 * Read bit field from D-PHY module (encapsulating the bus interface)
\r
1070 * @param instance pointer to structure which holds information about the d-phy
\r
1072 * @param reg_address offset
\r
1073 * @param shift from the right hand side of the register (big endian)
\r
1074 * @param width of the bit field
\r
1075 * @return data bits to be written to D-PHY
\r
1077 uint32_t mipi_dsih_dphy_read_part(dphy_t * instance, uint32_t reg_address, uint8_t shift, uint8_t width)
\r
1079 return (mipi_dsih_dphy_read_word(instance, reg_address) >> shift) & ((1 << width) - 1);
\r