3 The Synopsys Software Driver and documentation (hereinafter "Software")
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4 is an unsupported proprietary work of Synopsys, Inc. unless otherwise
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5 expressly agreed to in writing between Synopsys and you.
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7 The Software IS NOT an item of Licensed Software or Licensed Product under
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8 any End User Software License Agreement or Agreement for Licensed Product
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9 with Synopsys or any supplement thereto. Permission is hereby granted,
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10 free of charge, to any person obtaining a copy of this software annotated
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11 with this license and the Software, to deal in the Software without
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12 restriction, including without limitation the rights to use, copy, modify,
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13 merge, publish, distribute, sublicense, and/or sell copies of the Software,
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14 and to permit persons to whom the Software is furnished to do so, subject
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15 to the following conditions:
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17 The above copyright notice and this permission notice shall be included in
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18 all copies or substantial portions of the Software.
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20 THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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24 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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25 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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26 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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27 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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28 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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29 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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33 #ifndef MIPI_DSIH_LOCAL_H_
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34 #define MIPI_DSIH_LOCAL_H_
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36 //#include <stdint.h>
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38 #include "../sprdfb_chip_common.h"
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40 //#define MIPI_DEBUG
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42 #define MIPI_PRINT printf
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44 #define MIPI_PRINT(...)
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47 //typedef unsigned char uint8_t;
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48 //typedef unsigned short uint16_t;
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49 //typedef unsigned int uint32_t;
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51 #define DSIH_PIXEL_TOLERANCE 2
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52 #define DSIH_FIFO_ACTIVE_WAIT 5000 /* no of tries to access the fifo*/
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53 #define DSIH_PHY_ACTIVE_WAIT 200
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54 #define ONE_MS_ACTIVE_WAIT 50000 /* 50MHz processor */
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55 #define DEFAULT_BYTE_CLOCK 864000 /* a value to start PHY PLL - random */
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57 /** Define D-PHY type */
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58 #ifdef SPRD_MIPI_DPHY_GEN1
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59 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP 4 Lanes Gen 1 1GHz */
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60 #define DWC_MIPI_DPHY_BIDIR_TSMC40LP
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62 #ifdef SPRD_MIPI_DPHY_GEN2
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63 /** DWC_MIPI_DPHY_BIDIR_TSMC40LP / GF28LP 4 Lanes Gen 2 1.5GHz */
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66 /** 4 Lanes Gen 2 1.5GHz testchips */
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68 /** TQL 2 Lane test chip */
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69 /* #define DPHY2Btql */
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73 ERR_DSI_COLOR_CODING,
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74 ERR_DSI_OUT_OF_BOUND,
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76 ERR_DSI_INVALID_INSTANCE,
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77 ERR_DSI_INVALID_IO,
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78 ERR_DSI_CORE_INCOMPATIBLE,
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79 ERR_DSI_VIDEO_MODE,
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80 ERR_DSI_INVALID_COMMAND,
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81 ERR_DSI_INVALID_EVENT,
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82 ERR_DSI_INVALID_HANDLE,
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83 ERR_DSI_PHY_POWERUP,
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84 ERR_DSI_PHY_INVALID,
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85 ERR_DSI_PHY_FREQ_OUT_OF_BOUND,
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87 ERR_DSI_PHY_PLL_NOT_LOCKED,
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94 VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
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95 VIDEO_NON_BURST_WITH_SYNC_EVENTS,
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96 VIDEO_BURST_WITH_SYNC_PULSES
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101 COLOR_CODE_16BIT_CONFIG1,
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102 COLOR_CODE_16BIT_CONFIG2,
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103 COLOR_CODE_16BIT_CONFIG3,
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104 COLOR_CODE_18BIT_CONFIG1,
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105 COLOR_CODE_18BIT_CONFIG2,
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108 dsih_color_coding_t;
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114 ACK_ESCAPE_CMD_ERR,
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115 ACK_LP_TX_SYNC_ERR,
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116 ACK_HS_RX_TIMEOUT_ERR,
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117 ACK_FALSE_CONTROL_ERR,
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118 ACK_RSVD_DEVICE_ERR_7,
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119 ACK_ECC_SINGLE_BIT_ERR,
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120 ACK_ECC_MULTI_BIT_ERR,
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122 ACK_DSI_TYPE_NOT_RECOGNIZED_ERR,
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123 ACK_VC_ID_INVALID_ERR,
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124 ACK_INVALID_TX_LENGTH_ERR,
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125 ACK_RSVD_DEVICE_ERR_14,
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126 ACK_DSI_PROTOCOL_ERR,
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128 DPHY_ESC_ENTRY_ERR,
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129 DPHY_SYNC_ESC_LP_ERR,
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130 DPHY_CONTROL_LANE0_ERR,
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131 DPHY_CONTENTION_LP0_ERR,
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132 DPHY_CONTENTION_LP1_ERR,
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136 RX_ECC_SINGLE_ERR,
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141 DPI_PLD_FIFO_FULL_ERR,
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142 GEN_TX_CMD_FIFO_FULL_ERR,
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143 GEN_TX_PLD_FIFO_FULL_ERR,
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144 GEN_TX_PLD_FIFO_EMPTY_ERR,
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145 GEN_RX_PLD_FIFO_EMPTY_ERR,
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146 GEN_RX_PLD_FIFO_FULL_ERR,
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148 DBI_TX_CMD_FIFO_FULL_ERR,
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149 DBI_TX_PLD_FIFO_FULL_ERR,
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150 DBI_RX_PLD_FIFO_EMPTY_ERR,
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151 DBI_RX_PLD_FIFO_FULL_ERR,
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152 DBI_ILLEGAL_CMD_ERR,
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158 NOT_INITIALIZED = 0,
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165 typedef struct dphy_t
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168 uint32_t reference_freq;
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169 dsih_state_t status;
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170 void (*bsp_pre_config)(struct dphy_t *instance, void* param);
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171 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
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172 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
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173 void (*log_error)(const char * string);
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174 void (*log_info)(const char *fmt, ...);
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178 typedef struct dsih_ctrl_t
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181 dphy_t phy_instance;
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183 uint8_t max_lanes;
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184 uint8_t max_hs_to_lp_cycles;
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185 uint8_t max_lp_to_hs_cycles;
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186 uint16_t max_bta_cycles;
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187 int color_mode_polarity;
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188 int shut_down_polarity;
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189 dsih_state_t status;
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190 uint32_t (*core_read_function)(uint32_t addr, uint32_t offset);
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191 void (*core_write_function)(uint32_t addr, uint32_t offset, uint32_t data);
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192 void (*log_error)(const char * string);
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193 void (*log_info)(const char *fmt, ...);
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194 void (*event_registry[DSI_MAX_EVENT])(struct dsih_ctrl_t *instance, void *handler);
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199 uint8_t no_of_lanes;
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200 uint8_t virtual_channel;
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201 dsih_video_mode_t video_mode;
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202 int receive_ack_packets;
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203 uint32_t byte_clock;
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204 uint32_t pixel_clock;
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205 dsih_color_coding_t color_coding;
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206 int is_18_loosely;
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207 int data_en_polarity;
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209 uint16_t h_active_pixels; /* hadr*/
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210 uint16_t h_sync_pixels;
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211 uint16_t h_back_porch_pixels; /* hbp */
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212 uint16_t h_total_pixels; /* h_total */
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214 uint16_t v_active_lines; /* vadr*/
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215 uint16_t v_sync_lines;
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216 uint16_t v_back_porch_lines; /* vbp */
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217 uint16_t v_total_lines; /* v_total */
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225 register_config_t;
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227 #endif /* MIPI_DSIH_LOCAL_H_ */
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