drivers/video/sc8810_fb.c

   1 /*
   2  * Copyright (C) 2010 Spreadtrum
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <common.h>
  15 #include <lcd.h>
  16 #include <asm/io.h>
  17 #include <asm/errno.h>
  18
  19 #include <asm/arch/sc8810_reg_base.h>
  20 #include <asm/arch/sc8810_lcd.h>
  21 #include <asm/arch/lcdc_reg_v3.h>
  22 #include <asm/arch/lcm_reg_v3.h>
  23
  24 #include <asm/arch/mfp.h>
  25 #include <asm/arch/adi_hal_internal.h>
  26 #include <asm/arch/regs_ana.h>
  27 #include <asm/arch/analog_reg_v3.h>
  28
  29 #include <asm/arch/sc8810_reg_ahb.h>
  30 #include <asm/arch/sc8810_reg_global.h>
  31
  32 #include <asm/arch/gpio_drvapi.h>
  33
  34 #include <asm/arch/regs_global.h>
  35 #include <asm/arch/regs_cpc.h>
  36 #include <asm/arch/ldo.h>
  37 #include "sprdfb_panel.c"
  38 #define mdelay(a) udelay(a * 1000)
  39 #define printk printf
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 void *lcd_base;         /* Start of framebuffer memory  */
  44 void *lcd_console_address;      /* Start of console buffer      */
  45
  46 int lcd_line_length;
  47 int lcd_color_fg;
  48 int lcd_color_bg;
  49
  50 short console_col;
  51 short console_row;
  52
  53 //#define TEST_RRM /* enable rrm test */
  54 #define  FB_DEBUG
  55 #ifdef FB_DEBUG
  56 #define FB_PRINT printk
  57 #else
  58 #define FB_PRINT(...)
  59 #endif
  60
  61 #define BIT20 (1<<20)
  62 #define SPRD_GREG_BASE       GREG_BASE
  63
  64 #define GR_PLL_SRC           (SPRD_GREG_BASE + 0x70)
  65 #define BITS_PER_PIXEL 16
  66
  67 #define LCDC_CYCLES(t, ahb, div)  ((t) * (ahb) + (div) - 1) / (div)
  68 #define MAX_LCDC_TIMING_VALUE 15
  69
  70 struct sc8810fb_info {
  71         uint32_t cap;
  72         struct ops_mcu *ops;
  73         struct lcd_spec *panel;
  74         uint32_t smem_start;
  75         uint32_t smem_len;
  76
  77         uint32_t register_timing;
  78         uint32_t gram_timing;
  79 };
  80
  81
  82
  83 extern void FB_LDO_TurnOnLDO();
  84
  85 #ifdef CONFIG_LCD_WVGA
  86 vidinfo_t panel_info = {
  87         .vl_col = 480,
  88         .vl_bpix = 4,
  89         .vl_row = 800,
  90 };
  91 #endif
  92
  93 #ifdef CONFIG_LCD_HVGA
  94 vidinfo_t panel_info = {
  95         .vl_col = 320,
  96         .vl_bpix = 4,
  97         .vl_row = 480,
  98 };
  99 #endif
 100
 101 #ifdef CONFIG_LCD_QVGA
 102 vidinfo_t panel_info = {
 103         .vl_col = 240,
 104         .vl_bpix = 4,
 105         .vl_row = 320,
 106 };
 107 #endif
 108 static void __raw_bits_and(unsigned int v, unsigned int a)
 109 {
 110         __raw_writel((__raw_readl(a) & v), a);
 111
 112 }
 113
 114 static void __raw_bits_or(unsigned int v, unsigned int a)
 115 {
 116         __raw_writel((__raw_readl(a) | v), a);
 117 }
 118
 119 static int32_t lcm_send_cmd (uint32_t cmd)
 120 {
 121         /* busy wait for ahb fifo full sign's disappearance */
 122         while(__raw_readl(LCM_CTRL) & BIT20);
 123
 124         __raw_writel(cmd, LCM_CD0);
 125
 126         return 0;
 127 }
 128
 129 static int32_t lcm_send_cmd_data (uint32_t cmd, uint32_t data)
 130 {
 131         /* busy wait for ahb fifo full sign's disappearance */
 132         while(__raw_readl(LCM_CTRL) & BIT20);
 133
 134         __raw_writel(cmd, LCM_CD0);
 135
 136         /* busy wait for ahb fifo full sign's disappearance */
 137         while(__raw_readl(LCM_CTRL) & BIT20);
 138
 139         __raw_writel(data, LCM_DATA0);
 140
 141         return 0;
 142 }
 143
 144 static int32_t lcm_send_data (uint32_t data)
 145 {
 146         /* busy wait for ahb fifo full sign's disappearance */
 147          while(__raw_readl(LCM_CTRL) & BIT20);
 148
 149         __raw_writel(data, LCM_DATA0);
 150
 151         return 0;
 152 }
 153
 154 static uint32_t lcm_read_data (void)
 155 {
 156         /* busy wait for ahb fifo full sign's disappearance */
 157         while(__raw_readl(LCM_CTRL) & BIT20);
 158         __raw_writel(1 << 24, LCM_DATA0);
 159
 160         udelay(50);
 161         while(__raw_readl(LCM_CTRL) & BIT20);
 162
 163         return __raw_readl(LCM_RDDATA);
 164 }
 165
 166 static struct ops_mcu lcm_mcu_ops = {
 167         .send_cmd = lcm_send_cmd,
 168         .send_cmd_data = lcm_send_cmd_data,
 169         .send_data = lcm_send_data,
 170         .read_data = lcm_read_data,
 171 };
 172
 173 static int32_t panel_reset()
 174 {
 175 #if (CONFIG_MACH_CORI || CONFIG_MACH_MINT || CONFIG_MACH_KYLEW)
 176         //panel reset
 177         __raw_writel(0, LCM_RSTN);
 178         udelay(10);
 179         __raw_writel(1, LCM_RSTN);
 180         mdelay(0x80);
 181 #else
 182         __raw_writel(0, LCM_RSTN);
 183         udelay(10);
 184         __raw_writel(1, LCM_RSTN);
 185         mdelay(10);
 186 #endif
 187
 188         return 0;
 189 }
 190
 191 static void lcdc_mcu_init(void)
 192 {
 193         uint32_t reg_val = 0;
 194
 195         /* LCDC module enable */
 196         reg_val |= (1 << 0);
 197
 198         /* FMARK mode ï¼?disable */
 199         reg_val |= (1 << 1);
 200
 201         /*FMARK pol*/
 202
 203         /* dithering enable ï¼?the logo is in the rgb565 buffer */
 204         reg_val |= (1 << 4);
 205
 206         __raw_writel(reg_val, LCDC_CTRL);
 207
 208         FB_PRINT("[%s] LCDC_CTRL: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_CTRL));
 209
 210         /* set background */
 211         __raw_writel(0xffffff, LCDC_BG_COLOR);
 212 }
 213
 214 static uint32_t lcdc_calc_lcm_timing(struct timing_mcu *timing)
 215 {
 216         uint32_t ahb_clk;
 217         uint32_t rcss, rlpw, rhpw, wcss, wlpw, whpw;
 218
 219         /* can not get ahb clock rate; do later */
 220         ahb_clk = 250; // 250 MHz
 221
 222         FB_PRINT("[%s] ahb_clk: 0x%x\n", __FUNCTION__, ahb_clk);
 223
 224         /************************************************
 225         * we assume : t = ? ns, AHB = ? MHz   so
 226         *      1ns  cycle  :  AHB /1000
 227         *      tns  cycles :  t * AHB / 1000
 228         *
 229         *****************************************/
 230         rcss = LCDC_CYCLES(timing->rcss, ahb_clk, 1000);//ceiling
 231
 232         if (rcss > MAX_LCDC_TIMING_VALUE) {
 233                 rcss = MAX_LCDC_TIMING_VALUE ; // max 15 cycles
 234         }
 235
 236         rlpw = LCDC_CYCLES(timing->rlpw, ahb_clk , 1000);
 237         if (rlpw > MAX_LCDC_TIMING_VALUE) {
 238                 rlpw = MAX_LCDC_TIMING_VALUE ;
 239         }
 240
 241         rhpw = LCDC_CYCLES(timing->rhpw, ahb_clk , 1000);
 242         if (rhpw > MAX_LCDC_TIMING_VALUE) {
 243                 rhpw = MAX_LCDC_TIMING_VALUE ;
 244         }
 245
 246         wcss = LCDC_CYCLES(timing->wcss, ahb_clk, 1000);
 247         if (wcss > MAX_LCDC_TIMING_VALUE) {
 248                 wcss = MAX_LCDC_TIMING_VALUE ;
 249         }
 250
 251         wlpw = LCDC_CYCLES(timing->wlpw, ahb_clk, 1000);
 252         if (wlpw > MAX_LCDC_TIMING_VALUE) {
 253                 wlpw = MAX_LCDC_TIMING_VALUE ;
 254         }
 255
 256         whpw = LCDC_CYCLES(timing->whpw, ahb_clk, 1000) - 1;
 257         if (whpw > MAX_LCDC_TIMING_VALUE) {
 258                 whpw = MAX_LCDC_TIMING_VALUE ;
 259         }
 260
 261         /* LCDC_ChangePulseWidth() */
 262         return whpw | (wlpw << 4) | (wcss << 8)
 263                         | (rhpw << 16) |(rlpw << 20) | (rcss << 24);
 264
 265 }
 266
 267
 268 #ifdef CONFIG_FB_LCDC_CS1
 269
 270 static void lcdc_update_lcm_timing(uint32_t value)
 271 {
 272         __raw_writel(value, LCM_PARAMETER1);
 273
 274         FB_PRINT("[%s] LCM_PARAMETER1: 0x%x\n", __FUNCTION__, __raw_readl(LCM_PARAMETER1));
 275 }
 276
 277 #else
 278
 279 static void lcdc_update_lcm_timing(uint32_t value)
 280 {
 281         /* LCD_UpdateTiming() */
 282
 283         __raw_writel(value, LCM_PARAMETER0); /* FIXME: hardcoded for !CS0 */
 284
 285         FB_PRINT("[%s] LCM_PARAMETER0: 0x%x\n", __FUNCTION__, __raw_readl(LCM_PARAMETER0));
 286 }
 287
 288 #endif
 289
 290 static int mount_panel(struct sc8810fb_info *fb, struct lcd_spec *panel)
 291 {
 292         fb->panel = panel;
 293
 294         panel->info.mcu->ops = fb->ops;
 295
 296         panel->ops->lcd_reset = panel_reset;
 297
 298         {
 299                 struct timing_mcu *timing = panel->info.mcu->timing;
 300                 fb->register_timing = lcdc_calc_lcm_timing(timing);
 301                 timing++;
 302                 fb->gram_timing = lcdc_calc_lcm_timing(timing);
 303         }
 304         return 0;
 305 }
 306
 307 static void real_set_layer(struct sc8810fb_info *fb)
 308 {
 309         uint32_t reg_val;
 310
 311         /* image layer base */
 312         reg_val = fb->smem_start;
 313         __raw_writel(reg_val, LCDC_OSD1_BASE_ADDR);
 314 }
 315
 316 static void real_refresh(struct sc8810fb_info *fb)
 317 {
 318         fb->panel->ops->lcd_invalidate(fb->panel);
 319         /* set timing parameters for LCD */
 320         lcdc_update_lcm_timing(fb->gram_timing);
 321
 322         __raw_bits_or((1<<3), LCDC_CTRL); /* start refresh */
 323
 324         while(!(__raw_readl(LCDC_IRQ_RAW) & (1<<0))); /* wait util lcdc done */
 325
 326         __raw_bits_or((1<<0), LCDC_IRQ_CLR);
 327
 328         /* set timing parameters for LCD */
 329         lcdc_update_lcm_timing(fb->register_timing);
 330 }
 331
 332
 333 #ifdef CONFIG_FB_LCDC_CS1
 334
 335 static void lcdc_lcm_configure(struct sc8810fb_info *fb)
 336 {
 337         uint32_t reg_val = 0;
 338         /* CS0 bus mode [BIT0]: 8080/6800 */
 339         switch (fb->panel->info.mcu->bus_mode) {
 340         case LCD_BUS_8080:
 341
 342                 break;
 343         case LCD_BUS_6800:
 344                 reg_val  |= (1 << 8);
 345                 break;
 346         default:
 347                 break;
 348         }
 349         /* CS0 bus width [BIT1:0] */
 350         switch (fb->panel->info.mcu->bus_width) {
 351         case 8:
 352                 break;
 353         case 9:
 354                 reg_val  |= ((1 << 9) | (1 << 12));
 355                 break;
 356         case 16:
 357                 reg_val  |= (2 << 9);
 358                 break;
 359         case 18:
 360                 reg_val  |= ((3 << 9) | (1 << 12));
 361                 break;
 362         case 24:
 363                 reg_val  |= ((4 << 9) | (2 << 12));
 364                 break;
 365         default:
 366                 break;
 367
 368         }
 369
 370         reg_val  |= (1 << 16);
 371         __raw_writel(reg_val, LCM_CTRL);
 372
 373         FB_PRINT("[%s] LCM_CTRL: 0x%x\n", __FUNCTION__, __raw_readl(LCM_CTRL));
 374 }
 375
 376 #else
 377
 378 static void lcdc_lcm_configure(struct sc8810fb_info *fb)
 379 {
 380         uint32_t reg_val = 0;
 381         /* CS0 bus mode [BIT0]: 8080/6800 */
 382         switch (fb->panel->info.mcu->bus_mode) {
 383         case LCD_BUS_8080:
 384
 385                 break;
 386         case LCD_BUS_6800:
 387                 reg_val  |= 1;
 388                 break;
 389         default:
 390                 break;
 391         }
 392         /* CS0 bus width [BIT1:0] */
 393         switch (fb->panel->info.mcu->bus_width) {
 394         case 8:
 395                 break;
 396         case 9:
 397                 reg_val  |= ((1 << 1) | (1 << 4));
 398                 break;
 399         case 16:
 400                 reg_val  |= (2 << 1);
 401                 break;
 402         case 18:
 403                 reg_val  |= ((3 << 1) | (1 << 4));
 404                 break;
 405         case 24:
 406                 reg_val  |= ((4 << 1) | (2 << 4));
 407                 break;
 408         default:
 409                 break;
 410
 411         }
 412         __raw_writel(reg_val, LCM_CTRL);
 413
 414         FB_PRINT("[%s] LCM_CTRL: 0x%x\n", __FUNCTION__, __raw_readl(LCM_CTRL));
 415 }
 416
 417 #endif
 418
 419 static inline int set_lcdsize(struct lcd_spec *panel)
 420 {
 421         uint32_t reg_val;
 422
 423         reg_val = ( panel->width & 0xfff) | (( panel->height & 0xfff )<<16);
 424         __raw_writel(reg_val, LCDC_DISP_SIZE);
 425
 426         FB_PRINT("[%s] LCDC_DISP_SIZE: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_DISP_SIZE));
 427
 428         return 0;
 429 }
 430
 431 static inline int set_lcmrect( struct lcd_spec *panel)
 432 {
 433         uint32_t reg_val;
 434
 435         __raw_writel(0, LCDC_LCM_START);
 436
 437         reg_val = ( panel->width & 0xfff) | (( panel->height & 0xfff )<<16);
 438         __raw_writel(reg_val, LCDC_LCM_SIZE);
 439
 440         FB_PRINT("[%s] LCDC_LCM_START: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_LCM_START));
 441         FB_PRINT("[%s] LCDC_LCM_SIZE: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_LCM_SIZE));
 442
 443         return 0;
 444 }
 445
 446 int set_lcdc_layers(struct sc8810fb_info *fb)
 447 {
 448         uint32_t reg_val = 0;
 449
 450         __raw_bits_and(~(1<<0),LCDC_IMG_CTRL);
 451         __raw_bits_and(~(1<<0),LCDC_OSD2_CTRL);
 452         __raw_bits_and(~(1<<0),LCDC_OSD3_CTRL);
 453         __raw_bits_and(~(1<<0),LCDC_OSD4_CTRL);
 454         __raw_bits_and(~(1<<0),LCDC_OSD5_CTRL);
 455         /*enable OSD1 layer*/
 456         //__raw_bits_or((1<<0),LCDC_OSD1_CTRL);
 457         reg_val |= (1 << 0);
 458
 459         /*color key */
 460         //__raw_bits_and(~(1<<1),LCDC_OSD1_CTRL);  //disable
 461
 462         /*alpha mode select*/
 463         //__raw_bits_or((1<<2),LCDC_OSD1_CTRL);  //block alpha
 464         reg_val |= (1 << 2);
 465
 466         reg_val |= (5 << 3); //RGB565
 467         reg_val |= (2 << 7); //B2B3B0B1
 468
 469         __raw_writel(reg_val, LCDC_OSD1_CTRL);
 470
 471         FB_PRINT("[%s] LCDC_OSD1_CTRL: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_CTRL));
 472
 473         /* OSD1 layer base */
 474         reg_val = fb->smem_start;
 475         __raw_writel(reg_val, LCDC_OSD1_BASE_ADDR);
 476
 477         //FB_PRINT("[%s] LCDC_OSD1_BASE_ADDR: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_BASE_ADDR));
 478
 479         /*OSD1 layer alpha value*/
 480         __raw_writel(0xff, LCDC_OSD1_ALPHA);
 481
 482         FB_PRINT("[%s] LCDC_OSD1_ALPHA: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_ALPHA));
 483
 484         /*alpha base addr*/
 485         //__raw_writel(reg_val, LCDC_OSD1_ALPHA_BASE_ADDR);
 486
 487         /*OSD1 layer size*/
 488         reg_val = ( fb->panel->width & 0xfff) | (( fb->panel->height & 0xfff )<<16);
 489         __raw_writel(reg_val, LCDC_OSD1_SIZE_XY);
 490
 491         FB_PRINT("[%s] LCDC_OSD1_SIZE_XY: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_SIZE_XY));
 492
 493         /*OSD1 layer start position*/
 494         __raw_writel(0, LCDC_OSD1_DISP_XY);
 495
 496         FB_PRINT("[%s] LCDC_OSD1_DISP_XY: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_DISP_XY));
 497
 498         /*OSD1 layer pitch*/
 499         reg_val = ( fb->panel->width & 0xfff) ;
 500         __raw_writel(reg_val, LCDC_OSD1_PITCH);
 501
 502         FB_PRINT("[%s] LCDC_OSD1_PITCH: 0x%x\n", __FUNCTION__, __raw_readl(LCDC_OSD1_PITCH));
 503
 504         /*LCDC workplane size*/
 505         set_lcdsize(fb->panel);
 506
 507         /*LCDC LCM rect size*/
 508         set_lcmrect(fb->panel);
 509
 510         return 0;
 511 }
 512
 513 static void hw_early_init(struct sc8810fb_info *fb)
 514 {
 515         //select LCDC clock source
 516         __raw_bits_and(~(1<<6), GR_PLL_SRC);    //pll_src=96M
 517         __raw_bits_and(~(1<<7), GR_PLL_SRC);
 518
 519         //set LCDC divdior
 520         __raw_bits_and(~(1<<0), GR_GEN4);  //div=0
 521         __raw_bits_and(~(1<<1), GR_GEN4);
 522         __raw_bits_and(~(1<<2), GR_GEN4);
 523
 524         //enable LCDC clock
 525         __raw_bits_or((1<<3), AHB_CTL0);
 526
 527         //LCDC soft reset
 528         __raw_bits_or((1<<3), AHB_SOFT_RST);
 529         udelay(10);
 530         __raw_bits_and(~(1<<3), AHB_SOFT_RST);
 531
 532         __raw_bits_and(~(1<<0), LCDC_IRQ_EN);
 533         __raw_bits_or((1<<0), LCDC_IRQ_CLR);
 534
 535         /* init lcdc mcu mode using default configuration */
 536         lcdc_mcu_init();
 537 }
 538
 539 static void hw_init(struct sc8810fb_info *fb)
 540 {
 541         /* only MCU mode is supported currently */
 542         if (LCD_MODE_RGB == fb->panel->mode)
 543                 return;
 544
 545         //panel reset
 546         panel_reset(fb->panel);
 547
 548         /* set lcdc-lcd interface parameters */
 549         lcdc_lcm_configure(fb);
 550
 551         /* set timing parameters for LCD */
 552         lcdc_update_lcm_timing(fb->register_timing);
 553
 554 }
 555
 556 static void hw_later_init(struct sc8810fb_info *fb)
 557 {
 558         /* init mounted lcd panel */
 559         fb->panel->ops->lcd_init(fb->panel);
 560
 561         set_lcdc_layers(fb);
 562 }
 563
 564 #define WHTLED_CTL              ANA_LED_CTL
 565 #define WHTLED_PD_SET           BIT_0
 566 #define WHTLED_PD_RST           BIT_1
 567 #define WHTLED_V_SHIFT          2
 568 #define WHTLED_V_MSK            (0x1F << WHTLED_V_SHIFT)
 569
 570 static void LCD_SetPwmRatio(unsigned short value)
 571 {
 572         __raw_bits_or(CLK_PWM0_EN, GR_CLK_EN);
 573         __raw_bits_or(CLK_PWM0_SEL, GR_CLK_EN);
 574         __raw_bits_or(PIN_PWM0_MOD_VALUE, CPC_LCD_PWM_REG);
 575         __raw_writel(LCD_PWM_PRESCALE_VALUE, SPRD_PWM0_PRESCALE);
 576         __raw_writel(value, SPRD_PWM0_CNT);
 577         __raw_writel(PWM_REG_MSK_VALUE, SPRD_PWM0_PAT_LOW);
 578         __raw_writel(PWM_REG_MSK_VALUE, SPRD_PWM0_PAT_HIG);
 579
 580         __raw_bits_or(LCD_PWM0_EN, SPRD_PWM0_PRESCALE);
 581 }
 582
 583 void LCD_SetBackLightBrightness( unsigned long  value)
 584 {
 585         unsigned long duty_mod= 0;
 586         if(value > LCD_PWM_MOD_VALUE)
 587                 value = LCD_PWM_MOD_VALUE;
 588
 589 /*
 590         if(value < 0)
 591                 value = 0;
 592 */
 593         duty_mod = (value << 8) | LCD_PWM_MOD_VALUE;
 594         LCD_SetPwmRatio(duty_mod);
 595 }
 596
 597 static struct sc8810fb_info sc8810fb = {0};
 598
 599 static uint32_t lcd_id_to_kernel = 0;
 600
 601 void save_lcd_id_to_kernel(uint32_t id)
 602 {
 603         lcd_id_to_kernel = id;
 604 }
 605
 606 uint32_t load_lcd_id_to_kernel()
 607 {
 608         return lcd_id_to_kernel;
 609 }
 610
 611 static int lcd_readid_default(struct lcd_spec *self)
 612 {
 613         uint32_t dummy;
 614         //default id reg is 0
 615         self->info.mcu->ops->send_cmd(0x0);
 616
 617         if(self->info.mcu->bus_width == 8)      {
 618                 dummy = (self->info.mcu->ops->read_data())&0xff;
 619                 dummy <<= 8;
 620                 dummy |= (self->info.mcu->ops->read_data())&0xff;
 621         } else {
 622                 dummy = (self->info.mcu->ops->read_data());
 623         }
 624         return dummy;
 625 }
 626
 627
 628 static int find_adapt_from_readid(struct sc8810fb_info *fb)
 629 {
 630         int i;
 631         uint32_t id;
 632         for(i = 0;i<(sizeof(lcd_panel))/(sizeof(lcd_panel[0]));i++) {
 633                 //first ,try mount
 634                 mount_panel(fb,lcd_panel[i].panel);
 635                 //hw init to every panel
 636                 hw_init(fb);
 637                 //readid
 638                 if(fb->panel->ops->lcd_readid) {
 639                         id = fb->panel->ops->lcd_readid(fb->panel);
 640                 } else {
 641                         id = lcd_readid_default(fb->panel);
 642                 }
 643                 //if the id is right?
 644                 if(id == lcd_panel[i].lcd_id) {
 645                         save_lcd_id_to_kernel(id);
 646                         return i;
 647                 }
 648         }
 649         return -1;
 650 }
 651
 652
 653 static int sc8810fb_probe(void * lcdbase)
 654 {
 655         int32_t ret;
 656         int lcd_adapt;
 657         struct sc8810fb_info *fb= &sc8810fb;
 658
 659         FB_PRINT("[%s]\n", __FUNCTION__);
 660
 661         FB_LDO_TurnOnLDO();
 662         fb->ops = &lcm_mcu_ops;
 663         //we maybe readid ,so hardware should be init
 664         hw_early_init(fb);
 665
 666         lcd_adapt = find_adapt_from_readid(fb);
 667
 668         if(lcd_adapt == -1) {
 669                 lcd_adapt = 0;
 670         }
 671
 672         ret = mount_panel(fb, lcd_panel[lcd_adapt].panel);
 673         if (ret) {
 674                 printk("unsupported panel!!");
 675                 return -EFAULT;
 676         }
 677
 678         fb->smem_start = (uint32_t)lcdbase;
 679         fb->smem_len = fb->panel->width * fb->panel->height;
 680
 681         hw_init(fb);
 682         hw_later_init(fb);
 683
 684         return 0;
 685 }
 686
 687 void lcd_initcolregs(void)
 688 {
 689 }
 690
 691 void lcd_disable(void)
 692 {
 693 }
 694
 695
 696 /* References in this function refer to respective Linux kernel sources */
 697 void lcd_enable(void)
 698 {
 699 }
 700
 701 void lcd_ctrl_init(void *lcdbase)
 702 {
 703      sc8810fb_probe(lcdbase);
 704 }
 705
 706 void lcd_display(void)
 707 {
 708     real_refresh(&sc8810fb);
 709 }
 710
 711 #ifdef CONFIG_LCD_INFO
 712 #include <nand.h>
 713 extern nand_info_t nand_info[];
 714
 715 void lcd_show_board_info(void)
 716 {
 717     ulong dram_size, nand_size;
 718     int i;
 719     char temp[32];
 720
 721     dram_size = 0;
 722     for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 723       dram_size += gd->bd->bi_dram[i].size;
 724     nand_size = 0;
 725     for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 726       nand_size += nand_info[i].size;
 727
 728     lcd_printf("\n%s\n", U_BOOT_VERSION);
 729     lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 730                 dram_size >> 20,
 731                 nand_size >> 20 );
 732     lcd_printf("  Board            : esd ARM9 \n");
 733     lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
 734 }
 735 #endif /* CONFIG_LCD_INFO */
 736
 737