1 /* linux/drivers/video/s5p_mipi_dsi_common.c
3 * Samsung SoC MIPI-DSI common driver.
5 * Copyright (c) 2011 Samsung Electronics Co., Ltd
7 * InKi Dae, <inki.dae@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/mutex.h>
18 #include <linux/wait.h>
22 #include <linux/ctype.h>
23 #include <linux/platform_device.h>
25 #include <linux/memory.h>
26 #include <linux/delay.h>
27 #include <linux/kthread.h>
29 #include <video/mipi_display.h>
31 #include <plat/regs-dsim2.h>
34 #include <plat/mipi_dsim2.h>
35 #include <plat/regs-dsim2.h>
37 #include "s5p_mipi_dsi_lowlevel.h"
38 #include "s5p_mipi_dsi_common.h"
40 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
41 #define MIPI_RX_FIFO_READ_DONE 0x30800002
42 #define MIPI_MAX_RX_FIFO 20
43 #define MHZ (1000 * 1000)
44 #define FIN_HZ (24 * MHZ)
46 #define DFIN_PLL_MIN_HZ (6 * MHZ)
47 #define DFIN_PLL_MAX_HZ (12 * MHZ)
49 #define DFVCO_MIN_HZ (500 * MHZ)
50 #define DFVCO_MAX_HZ (1000 * MHZ)
52 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
53 #define TRY_FIFO_CLEAR (10)
55 /* MIPI-DSIM status types. */
57 DSIM_STATE_INIT, /* should be initialized. */
58 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
59 DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
63 /* define DSI lane types. */
65 DSIM_LANE_CLOCK = (1 << 0),
66 DSIM_LANE_DATA0 = (1 << 1),
67 DSIM_LANE_DATA1 = (1 << 2),
68 DSIM_LANE_DATA2 = (1 << 3),
69 DSIM_LANE_DATA3 = (1 << 4)
72 static unsigned int dpll_table[15] = {
73 100, 120, 170, 220, 270,
74 320, 390, 450, 510, 560,
75 640, 690, 770, 870, 950,
78 irqreturn_t s5p_mipi_dsi_interrupt_handler(int irq, void *dev_id)
80 unsigned int intsrc = 0;
81 unsigned int intmsk = 0;
82 struct mipi_dsim_device *dsim = NULL;
84 dsim = (struct mipi_dsim_device *)dev_id;
86 dev_dbg(dsim->dev, KERN_ERR "%s:error: wrong parameter\n",
91 intsrc = s5p_mipi_dsi_read_interrupt(dsim);
92 intmsk = s5p_mipi_dsi_read_interrupt_mask(dsim);
94 intmsk = ~(intmsk) & intsrc;
98 complete(&dsim_rd_comp);
99 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
101 case INTMSK_FIFO_EMPTY:
102 complete(&dsim_wr_comp);
103 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
109 s5p_mipi_dsi_clear_interrupt(dsim, intmsk);
114 static void s5p_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
115 unsigned int data0, unsigned int data1)
117 unsigned int data_cnt = 0, payload = 0;
119 /* in case that data count is more then 4 */
120 for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
122 * after sending 4bytes per one time,
123 * send remainder data less then 4.
125 if ((data1 - data_cnt) < 4) {
126 if ((data1 - data_cnt) == 3) {
127 payload = *(u8 *)(data0 + data_cnt) |
128 (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
129 (*(u8 *)(data0 + (data_cnt + 2))) << 16;
130 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
131 payload, *(u8 *)(data0 + data_cnt),
132 *(u8 *)(data0 + (data_cnt + 1)),
133 *(u8 *)(data0 + (data_cnt + 2)));
134 } else if ((data1 - data_cnt) == 2) {
135 payload = *(u8 *)(data0 + data_cnt) |
136 (*(u8 *)(data0 + (data_cnt + 1))) << 8;
138 "count = 2 payload = %x, %x %x\n", payload,
139 *(u8 *)(data0 + data_cnt),
140 *(u8 *)(data0 + (data_cnt + 1)));
141 } else if ((data1 - data_cnt) == 1) {
142 payload = *(u8 *)(data0 + data_cnt);
145 s5p_mipi_dsi_wr_tx_data(dsim, payload);
146 /* send 4bytes per one time. */
148 payload = *(u8 *)(data0 + data_cnt) |
149 (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
150 (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
151 (*(u8 *)(data0 + (data_cnt + 3))) << 24;
154 "count = 4 payload = %x, %x %x %x %x\n",
155 payload, *(u8 *)(data0 + data_cnt),
156 *(u8 *)(data0 + (data_cnt + 1)),
157 *(u8 *)(data0 + (data_cnt + 2)),
158 *(u8 *)(data0 + (data_cnt + 3)));
160 s5p_mipi_dsi_wr_tx_data(dsim, payload);
165 int s5p_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
166 unsigned int data0, unsigned int data1)
168 unsigned int check_rx_ack = 0;
170 if (dsim->state == DSIM_STATE_ULPS) {
171 dev_err(dsim->dev, "state is ULPS.\n");
176 /* FIXME!!! why does it need this delay? */
179 mutex_lock(&dsim->lock);
182 /* short packet types of packet types for command. */
183 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
184 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
185 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
186 case MIPI_DSI_DCS_SHORT_WRITE:
187 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
188 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
189 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
191 /* process response func should be implemented */
192 mutex_unlock(&dsim->lock);
195 mutex_unlock(&dsim->lock);
199 /* general command */
200 case MIPI_DSI_COLOR_MODE_OFF:
201 case MIPI_DSI_COLOR_MODE_ON:
202 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
203 case MIPI_DSI_TURN_ON_PERIPHERAL:
204 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
206 /* process response func should be implemented. */
207 mutex_unlock(&dsim->lock);
210 mutex_unlock(&dsim->lock);
214 /* packet types for video data */
215 case MIPI_DSI_V_SYNC_START:
216 case MIPI_DSI_V_SYNC_END:
217 case MIPI_DSI_H_SYNC_START:
218 case MIPI_DSI_H_SYNC_END:
219 case MIPI_DSI_END_OF_TRANSMISSION:
220 mutex_unlock(&dsim->lock);
223 /* long packet type and null packet */
224 case MIPI_DSI_NULL_PACKET:
225 case MIPI_DSI_BLANKING_PACKET:
226 mutex_unlock(&dsim->lock);
228 case MIPI_DSI_GENERIC_LONG_WRITE:
229 case MIPI_DSI_DCS_LONG_WRITE:
231 unsigned int size, data_cnt = 0, payload = 0;
232 INIT_COMPLETION(dsim_wr_comp);
236 /* if data count is less then 4, then send 3bytes data. */
238 payload = *(u8 *)(data0) |
239 *(u8 *)(data0 + 1) << 8 |
240 *(u8 *)(data0 + 2) << 16;
242 s5p_mipi_dsi_wr_tx_data(dsim, payload);
244 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
246 *(u8 *)(data0 + data_cnt),
247 *(u8 *)(data0 + (data_cnt + 1)),
248 *(u8 *)(data0 + (data_cnt + 2)));
249 /* in case that data count is more then 4 */
251 s5p_mipi_dsi_long_data_wr(dsim, data0, data1);
253 /* put data into header fifo */
254 s5p_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
255 (data1 & 0xff00) >> 8);
257 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
258 MIPI_FIFO_TIMEOUT)) {
259 dev_warn(dsim->dev, "command write timeout.\n");
260 mutex_unlock(&dsim->lock);
265 /* process response func should be implemented. */
266 mutex_unlock(&dsim->lock);
269 mutex_unlock(&dsim->lock);
274 /* packet typo for video data */
275 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
276 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
277 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
278 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
280 /* process response func should be implemented. */
281 mutex_unlock(&dsim->lock);
284 mutex_unlock(&dsim->lock);
289 "data id %x is not supported current DSI spec.\n",
292 mutex_unlock(&dsim->lock);
296 mutex_unlock(&dsim->lock);
300 static unsigned int s5p_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
301 unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
303 unsigned int rcv_pkt, i, j;
306 /* for long packet */
307 rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
308 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
309 if (rxsize != req_size)
312 for (i = 0; i < (rxsize >> 2); i++) {
313 rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
314 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
315 for (j = 0; j < 4; j++) {
316 rx_buf[(i * 4) + j] =
317 (u8)(rcv_pkt >> (j * 8)) & 0xff;
318 dev_dbg(dsim->dev, "received value : %02x\n",
319 (rcv_pkt >> (j * 8)) & 0xff);
323 rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
324 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
325 for (j = 0; j < (rxsize % 4); j++) {
326 rx_buf[(i * 4) + j] =
327 (u8)(rcv_pkt >> (j * 8)) & 0xff;
328 dev_dbg(dsim->dev, "received value : %02x\n",
329 (rcv_pkt >> (j * 8)) & 0xff);
339 static unsigned int s5p_mipi_dsi_respense_size(unsigned int req_size)
344 response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
347 response = MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
350 response = MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
357 int s5p_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
358 unsigned int data0, unsigned int req_size, u8 *rx_buf)
360 unsigned int rx_data, rcv_pkt, i;
364 if (dsim->state == DSIM_STATE_ULPS) {
365 dev_err(dsim->dev, "state is ULPS.\n");
373 mutex_lock(&dsim->lock);
374 INIT_COMPLETION(dsim_rd_comp);
375 s5p_mipi_dsi_rd_tx_header(dsim,
376 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
378 response = s5p_mipi_dsi_respense_size(req_size);
381 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
382 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
383 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
384 case MIPI_DSI_DCS_READ:
385 s5p_mipi_dsi_rd_tx_header(dsim,
387 /* process response func should be implemented. */
391 "data id %x is not supported current DSI spec.\n",
397 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
398 MIPI_FIFO_TIMEOUT)) {
399 printk(KERN_ERR "RX done interrupt timeout\n");
400 mutex_unlock(&dsim->lock);
406 rx_data = s5p_mipi_dsi_rd_rx_fifo(dsim);
408 if ((u8)(rx_data & 0xff) != response) {
410 "mipi dsi wrong response rx_data : %x, response:%x\n",
416 /* for short packet */
417 for (i = 0; i < req_size; i++)
418 rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
421 /* for long packet */
422 rxsize = s5p_mipi_dsi_long_data_rd(dsim,
423 req_size, rx_data, rx_buf);
424 if (rxsize != req_size)
428 rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
432 if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
434 "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
438 mutex_unlock(&dsim->lock);
445 rcv_pkt = s5p_mipi_dsi_rd_rx_fifo(dsim);
446 if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
447 || (i > MIPI_MAX_RX_FIFO))
450 "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
454 "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
456 mutex_unlock(&dsim->lock);
461 static int s5p_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
469 s5p_mipi_dsi_enable_pll(dsim, 1);
472 if (s5p_mipi_dsi_is_pll_stable(dsim))
478 s5p_mipi_dsi_enable_pll(dsim, 0);
483 static unsigned long s5p_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
484 unsigned int pre_divider, unsigned int main_divider,
487 unsigned long dfin_pll, dfvco, dpll_out;
488 unsigned int i, freq_band = 0xf;
490 dfin_pll = (FIN_HZ / pre_divider);
492 /******************************************************
493 * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
494 ******************************************************
496 * 100 ~ 119.99 MHz 0001
497 * 120 ~ 159.99 MHz 0010
498 * 160 ~ 199.99 MHz 0011
499 * 200 ~ 239.99 MHz 0100
500 * 140 ~ 319.99 MHz 0101
501 * 320 ~ 389.99 MHz 0110
502 * 390 ~ 449.99 MHz 0111
503 * 450 ~ 509.99 MHz 1000
504 * 510 ~ 559.99 MHz 1001
505 * 560 ~ 639.99 MHz 1010
506 * 640 ~ 689.99 MHz 1011
507 * 690 ~ 769.99 MHz 1100
508 * 770 ~ 869.99 MHz 1101
509 * 870 ~ 949.99 MHz 1110
510 * 950 ~ 1000 MHz 1111
511 ******************************************************/
512 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
513 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
514 s5p_mipi_dsi_enable_afc(dsim, 0, 0);
516 if (dfin_pll < 7 * MHZ)
517 s5p_mipi_dsi_enable_afc(dsim, 1, 0x1);
518 else if (dfin_pll < 8 * MHZ)
519 s5p_mipi_dsi_enable_afc(dsim, 1, 0x0);
520 else if (dfin_pll < 9 * MHZ)
521 s5p_mipi_dsi_enable_afc(dsim, 1, 0x3);
522 else if (dfin_pll < 10 * MHZ)
523 s5p_mipi_dsi_enable_afc(dsim, 1, 0x2);
524 else if (dfin_pll < 11 * MHZ)
525 s5p_mipi_dsi_enable_afc(dsim, 1, 0x5);
527 s5p_mipi_dsi_enable_afc(dsim, 1, 0x4);
530 dfvco = dfin_pll * main_divider;
531 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
532 dfvco, dfin_pll, main_divider);
533 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
534 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
536 dpll_out = dfvco / (1 << scaler);
537 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
538 dpll_out, dfvco, scaler);
540 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
541 if (dpll_out < dpll_table[i] * MHZ) {
547 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
549 s5p_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
551 s5p_mipi_dsi_hs_zero_ctrl(dsim, 0);
552 s5p_mipi_dsi_prep_ctrl(dsim, 0);
555 s5p_mipi_dsi_pll_freq_band(dsim, freq_band);
558 s5p_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
561 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
567 static int s5p_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
568 unsigned int byte_clk_sel, unsigned int enable)
570 unsigned int esc_div;
571 unsigned long esc_clk_error_rate;
572 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
575 dsim->e_clk_src = byte_clk_sel;
577 /* Escape mode clock and byte clock source */
578 s5p_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
580 /* DPHY, DSIM Link : D-PHY clock out */
581 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
582 hs_clk = s5p_mipi_dsi_change_pll(dsim,
583 dsim->dsim_config->p, dsim->dsim_config->m,
584 dsim->dsim_config->s);
587 "failed to get hs clock.\n");
591 byte_clk = hs_clk / 8;
592 s5p_mipi_dsi_enable_pll_bypass(dsim, 0);
593 s5p_mipi_dsi_pll_on(dsim, 1);
594 /* DPHY : D-PHY clock out, DSIM link : external clock out */
595 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
596 dev_warn(dsim->dev, "this project is not support\n");
598 "external clock source for MIPI DSIM.\n");
599 } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
600 dev_warn(dsim->dev, "this project is not support\n");
602 "external clock source for MIPI DSIM\n");
605 /* escape clock divider */
606 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
608 "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
609 esc_div, byte_clk, dsim->dsim_config->esc_clk);
610 if ((byte_clk / esc_div) >= (20 * MHZ) ||
611 (byte_clk / esc_div) >
612 dsim->dsim_config->esc_clk)
615 escape_clk = byte_clk / esc_div;
617 "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
618 escape_clk, byte_clk, esc_div);
620 /* enable escape clock. */
621 s5p_mipi_dsi_enable_byte_clock(dsim, 1);
623 /* enable byte clk and escape clock */
624 s5p_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
625 /* escape clock on lane */
626 s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
627 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
629 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
631 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
632 (dsim->dsim_config->esc_clk / MHZ));
633 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
634 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
635 ((byte_clk / esc_div) / MHZ));
637 if ((byte_clk / esc_div) > escape_clk) {
638 esc_clk_error_rate = escape_clk /
639 (byte_clk / esc_div);
640 dev_warn(dsim->dev, "error rate is %lu over.\n",
641 (esc_clk_error_rate / 100));
642 } else if ((byte_clk / esc_div) < (escape_clk)) {
643 esc_clk_error_rate = (byte_clk / esc_div) /
645 dev_warn(dsim->dev, "error rate is %lu under.\n",
646 (esc_clk_error_rate / 100));
649 s5p_mipi_dsi_enable_esc_clk_on_lane(dsim,
650 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
651 s5p_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
653 /* disable escape clock. */
654 s5p_mipi_dsi_enable_byte_clock(dsim, 0);
656 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
657 s5p_mipi_dsi_pll_on(dsim, 0);
663 int s5p_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
665 dsim->state = DSIM_STATE_INIT;
667 switch (dsim->dsim_config->e_no_data_lane) {
668 case DSIM_DATA_LANE_1:
669 dsim->data_lane = DSIM_LANE_DATA0;
671 case DSIM_DATA_LANE_2:
672 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
674 case DSIM_DATA_LANE_3:
675 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
678 case DSIM_DATA_LANE_4:
679 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
680 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
683 dev_info(dsim->dev, "data lane is invalid.\n");
687 s5p_mipi_dsi_sw_reset(dsim);
688 s5p_mipi_dsi_func_reset(dsim);
690 s5p_mipi_dsi_dp_dn_swap(dsim, 0);
695 void s5p_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
697 unsigned int src = 0;
699 #ifdef CONFIG_MACH_SLP_NAPLES
700 struct mipi_dsim_config *dsim_config;
702 dsim_config = dsim->dsim_config;
704 if (dsim_config->e_interface == DSIM_COMMAND) {
705 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE
706 | INTSRC_FRAME_DONE);
710 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
712 s5p_mipi_dsi_set_interrupt(dsim, src, 1);
716 if (dsim_config->e_interface == DSIM_COMMAND)
717 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY | INTMSK_FRAME_DONE);
719 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
720 s5p_mipi_dsi_set_interrupt_mask(dsim, src, 1);
722 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
723 s5p_mipi_dsi_set_interrupt(dsim, src, 1);
726 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
727 s5p_mipi_dsi_set_interrupt_mask(dsim, src, 1);
731 int s5p_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
734 /* enable only frame done interrupt */
735 s5p_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
741 /* this function can be used to convert legacy timing to generic one. */
742 void convert_to_fb_videomode(struct fb_videomode *mode1,
743 struct s3cfb_lcd *mode2)
745 mode1->xres = mode2->width;
746 mode1->yres = mode2->height;
747 mode1->upper_margin = mode2->timing.v_fp;
748 mode1->lower_margin = mode2->timing.v_bp;
749 mode1->left_margin = mode2->timing.h_fp;
750 mode1->right_margin = mode2->timing.h_bp;
751 mode1->vsync_len = mode2->timing.v_sw;
752 mode1->hsync_len = mode2->timing.h_sw;
756 void s5p_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
760 /* consider Main display and Sub display. */
762 s5p_mipi_dsi_set_main_stand_by(dsim, enable);
765 int s5p_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
766 struct mipi_dsim_config *dsim_config)
768 struct s5p_platform_mipi_dsim *dsim_pd;
769 struct fb_videomode *timing;
771 dsim_pd = (struct s5p_platform_mipi_dsim *)dsim->pd;
772 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
774 /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
775 if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
776 if (dsim_config->auto_vertical_cnt == 0) {
777 s5p_mipi_dsi_set_main_disp_vporch(dsim,
778 dsim_config->cmd_allow,
779 timing->upper_margin,
780 timing->lower_margin);
781 s5p_mipi_dsi_set_main_disp_hporch(dsim,
783 timing->right_margin);
784 s5p_mipi_dsi_set_main_disp_sync_area(dsim,
790 s5p_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
793 s5p_mipi_dsi_display_config(dsim, dsim_config);
795 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
796 timing->xres, timing->yres);
801 int s5p_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
803 unsigned int time_out = 100;
805 switch (dsim->state) {
806 case DSIM_STATE_INIT:
807 s5p_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
809 /* dsi configuration */
810 s5p_mipi_dsi_init_config(dsim);
811 s5p_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
812 s5p_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
814 /* set clock configuration */
815 s5p_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
817 /* check clock and data lane state are stop state */
818 while (!(s5p_mipi_dsi_is_lane_state(dsim))) {
822 "DSI Master is not stop state.\n");
824 "Check initialization process\n");
831 "DSI Master driver has been completed.\n");
832 dev_info(dsim->dev, "DSI Master state is stop state\n");
835 dsim->state = DSIM_STATE_STOP;
837 /* BTA sequence counters */
838 s5p_mipi_dsi_set_stop_state_counter(dsim,
839 dsim->dsim_config->stop_holding_cnt);
840 s5p_mipi_dsi_set_bta_timeout(dsim,
841 dsim->dsim_config->bta_timeout);
842 s5p_mipi_dsi_set_lpdr_timeout(dsim,
843 dsim->dsim_config->rx_timeout);
847 dev_info(dsim->dev, "DSI Master is already init.\n");
854 int s5p_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
856 if (dsim->state == DSIM_STATE_STOP) {
857 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
858 dsim->state = DSIM_STATE_HSCLKEN;
860 /* set LCDC and CPU transfer mode to HS. */
861 s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
862 s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
864 s5p_mipi_dsi_enable_hs_clock(dsim, 1);
869 "clock source is external bypass.\n");
871 dev_warn(dsim->dev, "DSIM is not stop state.\n");
876 int s5p_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
880 if (dsim->state != DSIM_STATE_HSCLKEN) {
881 dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
885 s5p_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
887 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
890 "DSI Master is not STOP or HSDT state.\n");
894 s5p_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
900 int s5p_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
902 return _s5p_mipi_dsi_get_frame_done_status(dsim);
905 int s5p_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
907 _s5p_mipi_dsi_clear_frame_done(dsim);
912 int s5p_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
915 int try = TRY_FIFO_CLEAR;
917 s5p_mipi_dsi_sw_reset_release(dsim);
918 s5p_mipi_dsi_func_reset(dsim);
921 if (s5p_mipi_dsi_get_sw_reset_release(dsim)) {
922 s5p_mipi_dsi_init_interrupt(dsim);
923 dev_dbg(dsim->dev, "reset release done.\n");
928 dev_err(dsim->dev, "failed to clear dsim fifo.\n");
932 #ifdef CONFIG_MACH_SLP_NAPLES
933 void s5p_mipi_dsi_trigger(struct fb_info *info)
938 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
939 MODULE_DESCRIPTION("Samusung MIPI-DSIM common driver");
940 MODULE_LICENSE("GPL");