2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/regs-fb.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/gpio.h>
35 /* DISPLAY CONTROL REGISTER */
36 #define DCR 0xE0107008
39 #define CLK_DIV0 0xE0100300
40 #define CLK_DIV1 0xE0100304
42 /* LCD CONTROLLER REGISTER BASE */
43 #define S5PC100_LCRB 0xEE000000
44 #define S5PC110_LCRB 0xF8000000
48 #define S5P_VFRAME_FREQ 60
50 static unsigned int ctrl_base;
51 static unsigned long *lcd_base_addr;
52 static vidinfo_t *pvid = NULL;
54 extern unsigned long get_pll_clk(int pllreg);
56 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
58 lcd_base_addr = (unsigned long *)screen_base;
60 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
65 void s5pc_c100_gpio_setup(void)
67 /* set GPF0[0:7] for RGB Interface and Data lines */
68 writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F0_OFFSET));
71 writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F1_OFFSET));
72 writel(0x22222222, S5PC100_GPIO_BASE(S5PC100_GPIO_F2_OFFSET));
73 writel(0x2222, S5PC100_GPIO_BASE(S5PC100_GPIO_F3_OFFSET));
75 /* set gpio configuration pin for MLCD_RST */
76 writel(0x10000000, S5PC100_GPIO_BASE(S5PC100_GPIO_H1_OFFSET));
78 /* set gpio configuration pin for MLCD_ON */
79 writel(0x1000, S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET));
80 writel(readl(S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET)) & 0xf7,
81 S5PC100_GPIO_BASE(S5PC100_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET));
83 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */
84 writel(0x11100000, S5PC100_GPIO_BASE(S5PC100_GPIO_K3_OFFSET));
87 void s5pc_c110_gpio_setup(void)
89 /* set GPF0[0:7] for RGB Interface and Data lines (32bit) */
90 writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET));
91 /* pull-up/down disable */
92 writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET+S5PC1XX_GPIO_PULL_OFFSET));
93 /* drive strength to max (24bit) */
94 writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F0_OFFSET+S5PC1XX_GPIO_DRV_OFFSET));
96 /* set Data lines (32bit) */
97 writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET));
98 writel(0x22222222, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET));
99 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)) & 0xFF0000,
100 S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET));
101 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET)) | 0x002222,
102 S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET));
104 /* drive strength to max (24bit) */
105 writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET+S5PC1XX_GPIO_DRV_OFFSET));
106 writel(0xffffff, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET+S5PC1XX_GPIO_DRV_OFFSET));
107 /* [11:0](drive stength level), [15:12](none), [21:16](Slew Rate) */
108 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)) & 0x3FFF00,
109 S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET));
110 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET)) | 0x0000FF,
111 S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_DRV_OFFSET));
113 /* pull-up/down disable */
114 writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F1_OFFSET+S5PC1XX_GPIO_PULL_OFFSET));
115 writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F2_OFFSET+S5PC1XX_GPIO_PULL_OFFSET));
116 writel(0x0, S5PC110_GPIO_BASE(S5PC110_GPIO_F3_OFFSET+S5PC1XX_GPIO_PULL_OFFSET));
118 /* display output path selection (only [1:0] valid) */
121 /* set gpio configuration pin for MLCD_RST */
122 /* for s5pc110 Universal board.
123 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)) & 0x0fffffff,
124 S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET));
125 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET)) | 0x10000000,
126 S5PC110_GPIO_BASE(S5PC110_GPIO_H1_OFFSET));
129 /* for s5pc110 Limo board. */
130 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)) & 0xff0fffff,
131 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET));
132 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET)) | 0x00100000,
133 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_5_OFFSET));
135 /* set gpio configuration pin for MLCD_ON and then to LOW */
136 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)) & 0xFFFF0FFF,
137 S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET));
138 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET)) | 0x00001000,
139 S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET));
140 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+4)) & 0xf7,
141 S5PC110_GPIO_BASE(S5PC110_GPIO_J1_OFFSET+S5PC1XX_GPIO_DAT_OFFSET));
143 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK, DISPLSY_SI and LCD_ID */
144 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)) & 0xFFFFFF0F,
145 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET));
146 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET)) | 0x00000010,
147 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_1_OFFSET));
148 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)) & 0xFFFF000F,
149 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET));
150 writel(readl(S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET)) | 0x00001110,
151 S5PC110_GPIO_BASE(S5PC110_GPIO_MP0_4_OFFSET));
155 static void s5pc_fimd_set_par(unsigned int win_id)
157 unsigned int cfg = 0;
159 /* set window control */
160 cfg = readl(ctrl_base + S5P_WINCON(win_id));
162 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
163 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
164 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
165 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
167 /* DATAPATH is DMA */
168 cfg |= S5P_WINCON_DATAPATH_DMA;
171 cfg |= S5P_WINCON_WSWP_ENABLE;
173 /* dma burst is 16 */
174 cfg |= S5P_WINCON_BURSTLEN_16WORD;
176 /* pixel format is unpacked RGB888 */
177 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
179 writel(cfg, ctrl_base + S5P_WINCON(win_id));
180 udebug("wincon%d = %x\n", win_id, cfg);
182 /* set window position to x=0, y=0*/
183 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
184 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
185 udebug("window postion left,top = %x\n", cfg);
187 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
188 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
189 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
190 udebug("window postion right,bottom= %x\n", cfg);
192 /* set window size for window0*/
193 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
194 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
195 udebug("vidosd_c%d= %x\n", win_id, cfg);
200 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
202 unsigned long start_addr, end_addr;
204 start_addr = (unsigned long)lcd_base_addr;
205 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
208 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
209 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
211 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
216 static void s5pc_fimd_set_clock(void)
218 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
219 unsigned long pixel_clock, src_clock, max_clock;
221 max_clock = 66 * 1000000;
223 pixel_clock = S5P_VFRAME_FREQ * (pvid->vl_hpw + pvid->vl_blw +
224 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
225 pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
227 src_clock = get_pll_clk(MPLL);
229 cfg = readl(ctrl_base + S5P_VIDCON0);
230 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
231 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
232 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
233 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
235 if (pixel_clock > max_clock)
236 pixel_clock = max_clock;
239 if (cpu_is_s5pc110())
240 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
242 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
245 * It can get source clock speed as (mpll / mpll_ratio)
246 * because lcd controller uses hclk_dsys.
247 * mpll is a parent of hclk_dsys.
249 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
250 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
251 writel(cfg, ctrl_base + S5P_VIDCON0);
253 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
254 mpll_ratio, src_clock, pixel_clock, div);
259 static s5pc_fimd_lcd_on(unsigned int win_id)
264 cfg = readl(ctrl_base + S5P_VIDCON0);
265 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
266 writel(cfg, ctrl_base + S5P_VIDCON0);
267 udebug("vidcon0 = %x\n", cfg);
270 cfg = readl(ctrl_base + S5P_WINCON(win_id));
271 cfg |= S5P_WINCON_ENWIN_ENABLE;
272 writel(cfg, ctrl_base + S5P_WINCON(win_id));
273 udebug("wincon%d=%x\n", win_id, cfg);
276 void s5pc_fimd_lcd_init(vidinfo_t *vid)
278 unsigned int cfg = 0, rgb_mode, win_id = 0;
280 /* store panel info to global variable */
283 /* select register base according to cpu type */
284 if (cpu_is_s5pc110())
285 ctrl_base = S5PC110_LCRB;
287 ctrl_base = S5PC100_LCRB;
289 /* set output to RGB */
290 rgb_mode = MODE_RGB_P;
291 cfg = readl(ctrl_base + S5P_VIDCON0);
292 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
294 /* clock source is HCLK */
297 cfg |= S5P_VIDCON0_VIDOUT_RGB;
298 writel(cfg, ctrl_base + S5P_VIDCON0);
300 /* set display mode */
301 cfg = readl(ctrl_base + S5P_VIDCON0);
302 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
303 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
304 writel(cfg, ctrl_base + S5P_VIDCON0);
308 cfg |= S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISING_EDGE;
309 writel(cfg, ctrl_base + S5P_VIDCON1);
313 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
314 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
315 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
316 writel(cfg, ctrl_base + S5P_VIDTCON0);
317 udebug("vidtcon0 = %x\n", cfg);
320 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
321 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
322 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
324 writel(cfg, ctrl_base + S5P_VIDTCON1);
325 udebug("vidtcon1 = %x\n", cfg);
329 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
330 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
332 writel(cfg, ctrl_base + S5P_VIDTCON2);
333 udebug("vidtcon2 = %x\n", cfg);
336 s5pc_fimd_set_par(win_id);
338 /* set memory address */
339 s5pc_fimd_set_buffer_address(win_id);
341 /* set buffer size */
342 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
343 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
344 udebug("vidaddr_pagewidth = %d\n", cfg);
347 s5pc_fimd_set_clock();
350 s5pc_fimd_lcd_on(win_id);
352 udebug("lcd controller init completed.\n");
357 ulong s5pc_fimd_calc_fbsize(void)
359 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));