2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/regs-fb.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/gpio.h>
35 /* DISPLAY CONTROL REGISTER */
36 #define DCR 0xE0107008
39 #define CLK_DIV0 0xE0100300
40 #define CLK_DIV1 0xE0100304
42 /* LCD CONTROLLER REGISTER BASE */
43 #define S5PC100_LCRB 0xEE000000
44 #define S5PC110_LCRB 0xF8000000
48 #define S5P_VFRAME_FREQ 60
50 static unsigned int ctrl_base;
51 static unsigned long *lcd_base_addr;
52 static vidinfo_t *pvid = NULL;
54 extern unsigned long get_pll_clk(int pllreg);
55 extern void s5pc1xx_clock_init(void);
57 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
59 lcd_base_addr = (unsigned long *)screen_base;
61 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
66 void s5pc_c100_gpio_setup(void)
70 void s5pc_c110_gpio_setup(void)
73 struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE;
75 for (i = 0; i < 8; i++) {
76 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
77 gpio_cfg_pin(&gpio->gpio_f0, i, GPIO_FUNC(2));
78 gpio_cfg_pin(&gpio->gpio_f1, i, GPIO_FUNC(2));
79 gpio_cfg_pin(&gpio->gpio_f2, i, GPIO_FUNC(2));
80 /* pull-up/down disable */
81 gpio_set_pull(&gpio->gpio_f0, i, GPIO_PULL_NONE);
82 gpio_set_pull(&gpio->gpio_f1, i, GPIO_PULL_NONE);
83 gpio_set_pull(&gpio->gpio_f2, i, GPIO_PULL_NONE);
85 /* drive strength to max (24bit) */
86 gpio_set_drv(&gpio->gpio_f0, i, GPIO_DRV_4x);
87 gpio_set_rate(&gpio->gpio_f0, i, GPIO_DRV_SLOW);
88 gpio_set_drv(&gpio->gpio_f1, i, GPIO_DRV_4x);
89 gpio_set_rate(&gpio->gpio_f1, i, GPIO_DRV_SLOW);
90 gpio_set_drv(&gpio->gpio_f2, i, GPIO_DRV_4x);
91 gpio_set_rate(&gpio->gpio_f2, i, GPIO_DRV_SLOW);
94 for (i =0; i < 4; i++) {
95 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
96 gpio_cfg_pin(&gpio->gpio_f3, i, GPIO_PULL_UP);
97 /* pull-up/down disable */
98 gpio_set_pull(&gpio->gpio_f3, i, GPIO_PULL_NONE);
99 /* drive strength to max (24bit) */
100 gpio_set_drv(&gpio->gpio_f3, i, GPIO_DRV_4x);
101 gpio_set_rate(&gpio->gpio_f3, i, GPIO_DRV_SLOW);
103 /* display output path selection (only [1:0] valid) */
106 /* gpio pad configuration for LCD reset. */
107 gpio_cfg_pin(&gpio->gpio_mp0_5, 5, GPIO_OUTPUT);
109 /* gpio pad configuration for LCD ON. */
110 gpio_cfg_pin(&gpio->gpio_j1, 3, GPIO_OUTPUT);
112 /* gpio pad configuration for DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI. */
113 gpio_cfg_pin(&gpio->gpio_mp0_1, 1, GPIO_OUTPUT);
114 gpio_cfg_pin(&gpio->gpio_mp0_4, 1, GPIO_OUTPUT);
115 gpio_cfg_pin(&gpio->gpio_mp0_4, 2, GPIO_INPUT);
116 gpio_cfg_pin(&gpio->gpio_mp0_4, 3, GPIO_OUTPUT);
118 s5pc1xx_clock_init();
123 static void s5pc_fimd_set_par(unsigned int win_id)
125 unsigned int cfg = 0;
127 /* set window control */
128 cfg = readl(ctrl_base + S5P_WINCON(win_id));
130 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
131 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
132 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
133 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
135 /* DATAPATH is DMA */
136 cfg |= S5P_WINCON_DATAPATH_DMA;
139 cfg |= S5P_WINCON_WSWP_ENABLE;
141 /* dma burst is 16 */
142 cfg |= S5P_WINCON_BURSTLEN_16WORD;
144 /* pixel format is unpacked RGB888 */
145 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
147 writel(cfg, ctrl_base + S5P_WINCON(win_id));
148 udebug("wincon%d = %x\n", win_id, cfg);
150 /* set window position to x=0, y=0*/
151 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
152 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
153 udebug("window postion left,top = %x\n", cfg);
155 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
156 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
157 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
158 udebug("window postion right,bottom= %x\n", cfg);
160 /* set window size for window0*/
161 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
162 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
163 udebug("vidosd_c%d= %x\n", win_id, cfg);
168 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
170 unsigned long start_addr, end_addr;
172 start_addr = (unsigned long)lcd_base_addr;
173 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
176 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
177 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
179 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
184 static void s5pc_fimd_set_clock(void)
186 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
187 unsigned long pixel_clock, src_clock, max_clock;
189 max_clock = 66 * 1000000;
191 pixel_clock = S5P_VFRAME_FREQ * (pvid->vl_hpw + pvid->vl_blw +
192 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
193 pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
195 if (get_pll_clk == NULL) {
196 printf("get_pll_clk is null.\n");
199 //src_clock = get_pll_clk(MPLL);
200 src_clock = 667000000;
202 cfg = readl(ctrl_base + S5P_VIDCON0);
203 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
204 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
205 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
206 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
208 if (pixel_clock > max_clock)
209 pixel_clock = max_clock;
212 if (cpu_is_s5pc110())
213 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
215 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
218 * It can get source clock speed as (mpll / mpll_ratio)
219 * because lcd controller uses hclk_dsys.
220 * mpll is a parent of hclk_dsys.
222 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
223 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
224 writel(cfg, ctrl_base + S5P_VIDCON0);
226 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
227 mpll_ratio, src_clock, pixel_clock, div);
232 static void s5pc_fimd_lcd_on(unsigned int win_id)
234 unsigned int cfg = 0;
237 cfg = readl(ctrl_base + S5P_VIDCON0);
238 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
239 writel(cfg, ctrl_base + S5P_VIDCON0);
240 udebug("vidcon0 = %x\n", cfg);
243 cfg = readl(ctrl_base + S5P_WINCON(win_id));
244 cfg |= S5P_WINCON_ENWIN_ENABLE;
245 writel(cfg, ctrl_base + S5P_WINCON(win_id));
246 udebug("wincon%d=%x\n", win_id, cfg);
249 void s5pc_fimc_lcd_off(unsigned int win_id)
251 unsigned int cfg = 0;
253 cfg = readl(ctrl_base + S5P_VIDCON0);
254 cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
255 writel(cfg, ctrl_base + S5P_VIDCON0);
257 cfg = readl(ctrl_base + S5P_WINCON(win_id));
258 cfg &= S5P_WINCON_ENWIN_DISABLE;
259 writel(cfg, ctrl_base + S5P_WINCON(win_id));
263 void s5pc_fimd_lcd_init(vidinfo_t *vid)
265 unsigned int cfg = 0, rgb_mode, win_id = 0;
267 /* store panel info to global variable */
270 /* select register base according to cpu type */
271 if (cpu_is_s5pc110())
272 ctrl_base = S5PC110_LCRB;
274 ctrl_base = S5PC100_LCRB;
276 /* set output to RGB */
277 rgb_mode = MODE_RGB_P;
278 cfg = readl(ctrl_base + S5P_VIDCON0);
279 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
281 /* clock source is HCLK */
284 cfg |= S5P_VIDCON0_VIDOUT_RGB;
285 writel(cfg, ctrl_base + S5P_VIDCON0);
287 /* set display mode */
288 cfg = readl(ctrl_base + S5P_VIDCON0);
289 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
290 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
291 writel(cfg, ctrl_base + S5P_VIDCON0);
295 cfg |= S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISING_EDGE;
296 writel(cfg, ctrl_base + S5P_VIDCON1);
300 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
301 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
302 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
303 writel(cfg, ctrl_base + S5P_VIDTCON0);
304 udebug("vidtcon0 = %x\n", cfg);
307 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
308 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
309 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
311 writel(cfg, ctrl_base + S5P_VIDTCON1);
312 udebug("vidtcon1 = %x\n", cfg);
316 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
317 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
319 writel(cfg, ctrl_base + S5P_VIDTCON2);
320 udebug("vidtcon2 = %x\n", cfg);
323 s5pc_fimd_set_par(win_id);
325 /* set memory address */
326 s5pc_fimd_set_buffer_address(win_id);
328 /* set buffer size */
329 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
330 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
331 udebug("vidaddr_pagewidth = %d\n", cfg);
334 s5pc_fimd_set_clock();
337 s5pc_fimd_lcd_on(win_id);
339 udebug("lcd controller init completed.\n");
344 ulong s5pc_fimd_calc_fbsize(void)
346 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));