drivers/video/s5p-fimd.c

   1 /*
   2  * S5PC100 and S5PC110 LCD Controller Specific driver.
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <common.h>
  24 #include <stdarg.h>
  25 #include <linux/types.h>
  26 #include <asm/io.h>
  27 #include <lcd.h>
  28
  29 #include <asm/arch/clk.h>
  30 #include <asm/arch/cpu.h>
  31 #include <asm/arch/regs-fb.h>
  32 #include <asm/arch/gpio.h>
  33 #include "s5p-fb.h"
  34
  35 /* CLOCK DIVIDER 0 */
  36 #define CLK_DIV0        0xE0100300
  37 #define CLK_DIV1        0xE0100304
  38
  39 /* LCD CONTROLLER REGISTER BASE */
  40 #define S5PC100_LCRB            0xEE000000
  41 #define S5PC110_LCRB            0xF8000000
  42
  43 #define MPLL 1
  44
  45 static unsigned int ctrl_base;
  46 static unsigned long *lcd_base_addr;
  47 static vidinfo_t *pvid = NULL;
  48
  49 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
  50 {
  51         lcd_base_addr = (unsigned long *)screen_base;
  52
  53         udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
  54
  55         return;
  56 }
  57
  58 static void s5pc_fimd_set_par(unsigned int win_id)
  59 {
  60         unsigned int cfg = 0;
  61
  62         /* set window control */
  63         cfg = readl(ctrl_base + S5P_WINCON(win_id));
  64
  65         cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
  66                 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
  67                 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
  68                 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
  69
  70         /* DATAPATH is DMA */
  71         cfg |= S5P_WINCON_DATAPATH_DMA;
  72
  73         /* bpp is 32 */
  74         cfg |= S5P_WINCON_WSWP_ENABLE;
  75
  76         /* dma burst is 16 */
  77         cfg |= S5P_WINCON_BURSTLEN_16WORD;
  78
  79         /* pixel format is unpacked RGB888 */
  80         cfg |= S5P_WINCON_BPPMODE_24BPP_888;
  81
  82         writel(cfg, ctrl_base + S5P_WINCON(win_id));
  83         udebug("wincon%d = %x\n", win_id, cfg);
  84
  85         /* set window position to x=0, y=0*/
  86         cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
  87         writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
  88         udebug("window postion left,top = %x\n", cfg);
  89
  90         cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
  91                 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
  92         writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
  93         udebug("window postion right,bottom= %x\n", cfg);
  94
  95         /* set window size for window0*/
  96         cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
  97         writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
  98         udebug("vidosd_c%d= %x\n", win_id, cfg);
  99
 100         return;
 101 }
 102
 103 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
 104 {
 105         unsigned long start_addr, end_addr;
 106
 107         start_addr = (unsigned long)lcd_base_addr;
 108         end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
 109                 * pvid->vl_row);
 110
 111         writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
 112         writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
 113
 114         udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
 115
 116         return;
 117 }
 118
 119 static void s5pc_fimd_set_clock(void)
 120 {
 121         unsigned int cfg = 0, div = 0, mpll_ratio = 0;
 122         unsigned long pixel_clock, src_clock, max_clock;
 123
 124         s5pc1xx_clock_init();
 125
 126         max_clock = 66 * 1000000;
 127
 128         pixel_clock = pvid->vl_freq * (pvid->vl_hpw + pvid->vl_blw +
 129                 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
 130                     pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
 131
 132         if (get_pll_clk == NULL) {
 133                 printf("get_pll_clk is null.\n");
 134                 return;
 135         }
 136         src_clock = get_pll_clk(MPLL);
 137
 138         cfg = readl(ctrl_base + S5P_VIDCON0);
 139         cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
 140                 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
 141         cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
 142                 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
 143
 144         if (pixel_clock > max_clock)
 145                 pixel_clock = max_clock;
 146
 147         /* get mpll ratio */
 148         if (cpu_is_s5pc110())
 149                 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
 150         else
 151                 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
 152
 153         /*
 154          * It can get source clock speed as (mpll / mpll_ratio)
 155          * because lcd controller uses hclk_dsys.
 156          * mpll is a parent of hclk_dsys.
 157          */
 158         div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
 159         cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
 160         writel(cfg, ctrl_base + S5P_VIDCON0);
 161
 162         udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
 163                 mpll_ratio, src_clock, pixel_clock, div);
 164
 165         return;
 166 }
 167
 168 static void s5pc_fimd_lcd_on(unsigned int win_id)
 169 {
 170         unsigned int cfg = 0;
 171
 172         /* display on */
 173         cfg = readl(ctrl_base + S5P_VIDCON0);
 174         cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
 175         writel(cfg, ctrl_base + S5P_VIDCON0);
 176         udebug("vidcon0 = %x\n", cfg);
 177
 178         /* enable window */
 179         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 180         cfg |= S5P_WINCON_ENWIN_ENABLE;
 181         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 182         udebug("wincon%d=%x\n", win_id, cfg);
 183 }
 184
 185 void s5pc_fimc_lcd_off(unsigned int win_id)
 186 {
 187         unsigned int cfg = 0;
 188
 189         cfg = readl(ctrl_base + S5P_VIDCON0);
 190         cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
 191         writel(cfg, ctrl_base + S5P_VIDCON0);
 192
 193         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 194         cfg &= S5P_WINCON_ENWIN_DISABLE;
 195         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 196 }
 197
 198
 199 void s5pc_fimd_lcd_init(vidinfo_t *vid)
 200 {
 201         unsigned int cfg = 0, rgb_mode, win_id = 3;
 202
 203         /* store panel info to global variable */
 204         pvid = vid;
 205
 206         /* select register base according to cpu type */
 207         if (cpu_is_s5pc110())
 208                 ctrl_base = S5PC110_LCRB;
 209         else
 210                 ctrl_base = S5PC100_LCRB;
 211
 212         /* set output to RGB */
 213         rgb_mode = MODE_RGB_P;
 214         cfg = readl(ctrl_base + S5P_VIDCON0);
 215         cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
 216
 217         /* clock source is HCLK */
 218         cfg |= 0 << 2;
 219
 220         cfg |= S5P_VIDCON0_VIDOUT_RGB;
 221         writel(cfg, ctrl_base + S5P_VIDCON0);
 222
 223         /* set display mode */
 224         cfg = readl(ctrl_base + S5P_VIDCON0);
 225         cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
 226         cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
 227         writel(cfg, ctrl_base + S5P_VIDCON0);
 228
 229         /* set polarity */
 230         cfg = 0;
 231         if (!pvid->vl_clkp)
 232                 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
 233         if (!pvid->vl_hsp)
 234                 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
 235         if (!pvid->vl_vsp)
 236                 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
 237         if (!pvid->vl_dp)
 238                 cfg |= S5P_VIDCON1_IVDEN_INVERT;
 239
 240         writel(cfg, ctrl_base + S5P_VIDCON1);
 241
 242         /* set timing */
 243         cfg = 0;
 244         cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
 245         cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
 246         cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
 247         writel(cfg, ctrl_base + S5P_VIDTCON0);
 248         udebug("vidtcon0 = %x\n", cfg);
 249
 250         cfg = 0;
 251         cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
 252         cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
 253         cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
 254
 255         writel(cfg, ctrl_base + S5P_VIDTCON1);
 256         udebug("vidtcon1 = %x\n", cfg);
 257
 258         /* set lcd size */
 259         cfg = 0;
 260         cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
 261         cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
 262
 263         writel(cfg, ctrl_base + S5P_VIDTCON2);
 264         udebug("vidtcon2 = %x\n", cfg);
 265
 266         /* set par */
 267         s5pc_fimd_set_par(win_id);
 268
 269         /* set memory address */
 270         s5pc_fimd_set_buffer_address(win_id);
 271
 272         /* set buffer size */
 273         cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
 274         writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
 275         udebug("vidaddr_pagewidth = %d\n", cfg);
 276
 277         /* set clock */
 278         s5pc_fimd_set_clock();
 279
 280         /* display on */
 281         s5pc_fimd_lcd_on(win_id);
 282
 283         udebug("lcd controller init completed.\n");
 284
 285         return;
 286 }
 287
 288 ulong s5pc_fimd_calc_fbsize(void)
 289 {
 290         return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));
 291 }