2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/clk.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/regs-fb.h>
32 #include <asm/arch/gpio.h>
35 /* DISPLAY CONTROL REGISTER */
36 #define DCR 0xE0107008
39 #define CLK_DIV0 0xE0100300
40 #define CLK_DIV1 0xE0100304
42 /* LCD CONTROLLER REGISTER BASE */
43 #define S5PC100_LCRB 0xEE000000
44 #define S5PC110_LCRB 0xF8000000
48 #define S5P_VFRAME_FREQ 60
50 static unsigned int ctrl_base;
51 static unsigned long *lcd_base_addr;
52 static vidinfo_t *pvid = NULL;
54 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
56 lcd_base_addr = (unsigned long *)screen_base;
58 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
63 void s5pc_c100_gpio_setup(void)
67 void s5pc_c110_gpio_setup(void)
70 struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE;
72 for (i = 0; i < 8; i++) {
73 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
74 gpio_cfg_pin(&gpio->gpio_f0, i, GPIO_FUNC(2));
75 gpio_cfg_pin(&gpio->gpio_f1, i, GPIO_FUNC(2));
76 gpio_cfg_pin(&gpio->gpio_f2, i, GPIO_FUNC(2));
77 /* pull-up/down disable */
78 gpio_set_pull(&gpio->gpio_f0, i, GPIO_PULL_NONE);
79 gpio_set_pull(&gpio->gpio_f1, i, GPIO_PULL_NONE);
80 gpio_set_pull(&gpio->gpio_f2, i, GPIO_PULL_NONE);
82 /* drive strength to max (24bit) */
83 gpio_set_drv(&gpio->gpio_f0, i, GPIO_DRV_4x);
84 gpio_set_rate(&gpio->gpio_f0, i, GPIO_DRV_SLOW);
85 gpio_set_drv(&gpio->gpio_f1, i, GPIO_DRV_4x);
86 gpio_set_rate(&gpio->gpio_f1, i, GPIO_DRV_SLOW);
87 gpio_set_drv(&gpio->gpio_f2, i, GPIO_DRV_4x);
88 gpio_set_rate(&gpio->gpio_f2, i, GPIO_DRV_SLOW);
91 for (i =0; i < 4; i++) {
92 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
93 gpio_cfg_pin(&gpio->gpio_f3, i, GPIO_PULL_UP);
94 /* pull-up/down disable */
95 gpio_set_pull(&gpio->gpio_f3, i, GPIO_PULL_NONE);
96 /* drive strength to max (24bit) */
97 gpio_set_drv(&gpio->gpio_f3, i, GPIO_DRV_4x);
98 gpio_set_rate(&gpio->gpio_f3, i, GPIO_DRV_SLOW);
100 /* display output path selection (only [1:0] valid) */
103 /* gpio pad configuration for LCD reset. */
104 gpio_cfg_pin(&gpio->gpio_mp0_5, 5, GPIO_OUTPUT);
106 /* gpio pad configuration for LCD ON. */
107 gpio_cfg_pin(&gpio->gpio_j1, 3, GPIO_OUTPUT);
108 gpio_cfg_pin(&gpio->gpio_j1, 4, GPIO_OUTPUT);
110 /* gpio pad configuration for DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI. */
111 gpio_cfg_pin(&gpio->gpio_mp0_1, 1, GPIO_OUTPUT);
112 gpio_cfg_pin(&gpio->gpio_mp0_4, 1, GPIO_OUTPUT);
113 gpio_cfg_pin(&gpio->gpio_mp0_4, 2, GPIO_INPUT);
114 gpio_cfg_pin(&gpio->gpio_mp0_4, 3, GPIO_OUTPUT);
116 s5pc1xx_clock_init();
121 static void s5pc_fimd_set_par(unsigned int win_id)
123 unsigned int cfg = 0;
125 /* set window control */
126 cfg = readl(ctrl_base + S5P_WINCON(win_id));
128 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
129 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
130 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
131 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
133 /* DATAPATH is DMA */
134 cfg |= S5P_WINCON_DATAPATH_DMA;
137 cfg |= S5P_WINCON_WSWP_ENABLE;
139 /* dma burst is 16 */
140 cfg |= S5P_WINCON_BURSTLEN_16WORD;
142 /* pixel format is unpacked RGB888 */
143 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
145 writel(cfg, ctrl_base + S5P_WINCON(win_id));
146 udebug("wincon%d = %x\n", win_id, cfg);
148 /* set window position to x=0, y=0*/
149 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
150 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
151 udebug("window postion left,top = %x\n", cfg);
153 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
154 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
155 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
156 udebug("window postion right,bottom= %x\n", cfg);
158 /* set window size for window0*/
159 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
160 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
161 udebug("vidosd_c%d= %x\n", win_id, cfg);
166 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
168 unsigned long start_addr, end_addr;
170 start_addr = (unsigned long)lcd_base_addr;
171 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
174 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
175 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
177 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
182 static void s5pc_fimd_set_clock(void)
184 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
185 unsigned long pixel_clock, src_clock, max_clock;
187 max_clock = 66 * 1000000;
189 pixel_clock = S5P_VFRAME_FREQ * (pvid->vl_hpw + pvid->vl_blw +
190 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
191 pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
193 if (get_pll_clk == NULL) {
194 printf("get_pll_clk is null.\n");
197 src_clock = get_pll_clk(MPLL);
199 cfg = readl(ctrl_base + S5P_VIDCON0);
200 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
201 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
202 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
203 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
205 if (pixel_clock > max_clock)
206 pixel_clock = max_clock;
209 if (cpu_is_s5pc110())
210 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
212 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
215 * It can get source clock speed as (mpll / mpll_ratio)
216 * because lcd controller uses hclk_dsys.
217 * mpll is a parent of hclk_dsys.
219 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
220 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
221 writel(cfg, ctrl_base + S5P_VIDCON0);
223 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
224 mpll_ratio, src_clock, pixel_clock, div);
229 static void s5pc_fimd_lcd_on(unsigned int win_id)
231 unsigned int cfg = 0;
234 cfg = readl(ctrl_base + S5P_VIDCON0);
235 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
236 writel(cfg, ctrl_base + S5P_VIDCON0);
237 udebug("vidcon0 = %x\n", cfg);
240 cfg = readl(ctrl_base + S5P_WINCON(win_id));
241 cfg |= S5P_WINCON_ENWIN_ENABLE;
242 writel(cfg, ctrl_base + S5P_WINCON(win_id));
243 udebug("wincon%d=%x\n", win_id, cfg);
246 void s5pc_fimc_lcd_off(unsigned int win_id)
248 unsigned int cfg = 0;
250 cfg = readl(ctrl_base + S5P_VIDCON0);
251 cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
252 writel(cfg, ctrl_base + S5P_VIDCON0);
254 cfg = readl(ctrl_base + S5P_WINCON(win_id));
255 cfg &= S5P_WINCON_ENWIN_DISABLE;
256 writel(cfg, ctrl_base + S5P_WINCON(win_id));
260 void s5pc_fimd_lcd_init(vidinfo_t *vid)
262 unsigned int cfg = 0, rgb_mode, win_id = 1;
264 /* store panel info to global variable */
267 /* select register base according to cpu type */
268 if (cpu_is_s5pc110())
269 ctrl_base = S5PC110_LCRB;
271 ctrl_base = S5PC100_LCRB;
273 /* set output to RGB */
274 rgb_mode = MODE_RGB_P;
275 cfg = readl(ctrl_base + S5P_VIDCON0);
276 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
278 /* clock source is HCLK */
281 cfg |= S5P_VIDCON0_VIDOUT_RGB;
282 writel(cfg, ctrl_base + S5P_VIDCON0);
284 /* set display mode */
285 cfg = readl(ctrl_base + S5P_VIDCON0);
286 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
287 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
288 writel(cfg, ctrl_base + S5P_VIDCON0);
293 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
295 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
297 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
299 cfg |= S5P_VIDCON1_IVDEN_INVERT;
301 writel(cfg, ctrl_base + S5P_VIDCON1);
305 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
306 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
307 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
308 writel(cfg, ctrl_base + S5P_VIDTCON0);
309 udebug("vidtcon0 = %x\n", cfg);
312 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
313 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
314 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
316 writel(cfg, ctrl_base + S5P_VIDTCON1);
317 udebug("vidtcon1 = %x\n", cfg);
321 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
322 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
324 writel(cfg, ctrl_base + S5P_VIDTCON2);
325 udebug("vidtcon2 = %x\n", cfg);
328 s5pc_fimd_set_par(win_id);
330 /* set memory address */
331 s5pc_fimd_set_buffer_address(win_id);
333 /* set buffer size */
334 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
335 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
336 udebug("vidaddr_pagewidth = %d\n", cfg);
339 s5pc_fimd_set_clock();
342 s5pc_fimd_lcd_on(win_id);
344 udebug("lcd controller init completed.\n");
349 ulong s5pc_fimd_calc_fbsize(void)
351 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));