2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/clk.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/regs-fb.h>
32 #include <asm/arch/gpio.h>
35 /* DISPLAY CONTROL REGISTER */
36 #define DCR 0xE0107008
39 #define CLK_DIV0 0xE0100300
40 #define CLK_DIV1 0xE0100304
42 /* LCD CONTROLLER REGISTER BASE */
43 #define S5PC100_LCRB 0xEE000000
44 #define S5PC110_LCRB 0xF8000000
48 static unsigned int ctrl_base;
49 static unsigned long *lcd_base_addr;
50 static vidinfo_t *pvid = NULL;
52 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
54 lcd_base_addr = (unsigned long *)screen_base;
56 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
61 void s5pc_c100_gpio_setup(void)
65 void s5pc_c110_gpio_setup(void)
68 struct s5pc110_gpio *gpio = (struct s5pc110_gpio *) S5PC110_GPIO_BASE;
70 for (i = 0; i < 8; i++) {
71 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
72 gpio_cfg_pin(&gpio->gpio_f0, i, GPIO_FUNC(2));
73 gpio_cfg_pin(&gpio->gpio_f1, i, GPIO_FUNC(2));
74 gpio_cfg_pin(&gpio->gpio_f2, i, GPIO_FUNC(2));
75 /* pull-up/down disable */
76 gpio_set_pull(&gpio->gpio_f0, i, GPIO_PULL_NONE);
77 gpio_set_pull(&gpio->gpio_f1, i, GPIO_PULL_NONE);
78 gpio_set_pull(&gpio->gpio_f2, i, GPIO_PULL_NONE);
80 /* drive strength to max (24bit) */
81 gpio_set_drv(&gpio->gpio_f0, i, GPIO_DRV_4x);
82 gpio_set_rate(&gpio->gpio_f0, i, GPIO_DRV_SLOW);
83 gpio_set_drv(&gpio->gpio_f1, i, GPIO_DRV_4x);
84 gpio_set_rate(&gpio->gpio_f1, i, GPIO_DRV_SLOW);
85 gpio_set_drv(&gpio->gpio_f2, i, GPIO_DRV_4x);
86 gpio_set_rate(&gpio->gpio_f2, i, GPIO_DRV_SLOW);
89 for (i =0; i < 4; i++) {
90 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
91 gpio_cfg_pin(&gpio->gpio_f3, i, GPIO_PULL_UP);
92 /* pull-up/down disable */
93 gpio_set_pull(&gpio->gpio_f3, i, GPIO_PULL_NONE);
94 /* drive strength to max (24bit) */
95 gpio_set_drv(&gpio->gpio_f3, i, GPIO_DRV_4x);
96 gpio_set_rate(&gpio->gpio_f3, i, GPIO_DRV_SLOW);
98 /* display output path selection (only [1:0] valid) */
101 /* gpio pad configuration for LCD reset. */
102 gpio_cfg_pin(&gpio->gpio_mp0_5, 5, GPIO_OUTPUT);
104 /* gpio pad configuration for LCD ON. */
105 gpio_cfg_pin(&gpio->gpio_j1, 3, GPIO_OUTPUT);
106 /* gpio_cfg_pin(&gpio->gpio_j1, 4, GPIO_OUTPUT); P1P2: Real: MLCD_ON2 */
108 /* gpio pad configuration for DISPLAY_CS, DISPLAY_CLK, DISPLAY_SO, DISPLAY_SI. */
109 gpio_cfg_pin(&gpio->gpio_mp0_1, 1, GPIO_OUTPUT);
110 gpio_cfg_pin(&gpio->gpio_mp0_4, 1, GPIO_OUTPUT);
111 gpio_cfg_pin(&gpio->gpio_mp0_4, 2, GPIO_INPUT);
112 gpio_cfg_pin(&gpio->gpio_mp0_4, 3, GPIO_OUTPUT);
114 s5pc1xx_clock_init();
119 static void s5pc_fimd_set_par(unsigned int win_id)
121 unsigned int cfg = 0;
123 /* set window control */
124 cfg = readl(ctrl_base + S5P_WINCON(win_id));
126 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
127 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
128 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
129 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
131 /* DATAPATH is DMA */
132 cfg |= S5P_WINCON_DATAPATH_DMA;
135 cfg |= S5P_WINCON_WSWP_ENABLE;
137 /* dma burst is 16 */
138 cfg |= S5P_WINCON_BURSTLEN_16WORD;
140 /* pixel format is unpacked RGB888 */
141 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
143 writel(cfg, ctrl_base + S5P_WINCON(win_id));
144 udebug("wincon%d = %x\n", win_id, cfg);
146 /* set window position to x=0, y=0*/
147 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
148 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
149 udebug("window postion left,top = %x\n", cfg);
151 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
152 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
153 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
154 udebug("window postion right,bottom= %x\n", cfg);
156 /* set window size for window0*/
157 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
158 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
159 udebug("vidosd_c%d= %x\n", win_id, cfg);
164 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
166 unsigned long start_addr, end_addr;
168 start_addr = (unsigned long)lcd_base_addr;
169 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
172 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
173 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
175 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
180 static void s5pc_fimd_set_clock(void)
182 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
183 unsigned long pixel_clock, src_clock, max_clock;
185 max_clock = 66 * 1000000;
187 pixel_clock = pvid->vl_freq * (pvid->vl_hpw + pvid->vl_blw +
188 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
189 pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
191 if (get_pll_clk == NULL) {
192 printf("get_pll_clk is null.\n");
195 src_clock = get_pll_clk(MPLL);
197 cfg = readl(ctrl_base + S5P_VIDCON0);
198 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
199 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
200 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
201 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
203 if (pixel_clock > max_clock)
204 pixel_clock = max_clock;
207 if (cpu_is_s5pc110())
208 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
210 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
213 * It can get source clock speed as (mpll / mpll_ratio)
214 * because lcd controller uses hclk_dsys.
215 * mpll is a parent of hclk_dsys.
217 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
218 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
219 writel(cfg, ctrl_base + S5P_VIDCON0);
221 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
222 mpll_ratio, src_clock, pixel_clock, div);
227 static void s5pc_fimd_lcd_on(unsigned int win_id)
229 unsigned int cfg = 0;
232 cfg = readl(ctrl_base + S5P_VIDCON0);
233 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
234 writel(cfg, ctrl_base + S5P_VIDCON0);
235 udebug("vidcon0 = %x\n", cfg);
238 cfg = readl(ctrl_base + S5P_WINCON(win_id));
239 cfg |= S5P_WINCON_ENWIN_ENABLE;
240 writel(cfg, ctrl_base + S5P_WINCON(win_id));
241 udebug("wincon%d=%x\n", win_id, cfg);
244 void s5pc_fimc_lcd_off(unsigned int win_id)
246 unsigned int cfg = 0;
248 cfg = readl(ctrl_base + S5P_VIDCON0);
249 cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
250 writel(cfg, ctrl_base + S5P_VIDCON0);
252 cfg = readl(ctrl_base + S5P_WINCON(win_id));
253 cfg &= S5P_WINCON_ENWIN_DISABLE;
254 writel(cfg, ctrl_base + S5P_WINCON(win_id));
258 void s5pc_fimd_lcd_init(vidinfo_t *vid)
260 unsigned int cfg = 0, rgb_mode, win_id = 1;
262 /* store panel info to global variable */
265 /* select register base according to cpu type */
266 if (cpu_is_s5pc110())
267 ctrl_base = S5PC110_LCRB;
269 ctrl_base = S5PC100_LCRB;
271 /* set output to RGB */
272 rgb_mode = MODE_RGB_P;
273 cfg = readl(ctrl_base + S5P_VIDCON0);
274 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
276 /* clock source is HCLK */
279 cfg |= S5P_VIDCON0_VIDOUT_RGB;
280 writel(cfg, ctrl_base + S5P_VIDCON0);
282 /* set display mode */
283 cfg = readl(ctrl_base + S5P_VIDCON0);
284 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
285 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
286 writel(cfg, ctrl_base + S5P_VIDCON0);
291 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
293 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
295 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
297 cfg |= S5P_VIDCON1_IVDEN_INVERT;
299 writel(cfg, ctrl_base + S5P_VIDCON1);
303 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
304 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
305 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
306 writel(cfg, ctrl_base + S5P_VIDTCON0);
307 udebug("vidtcon0 = %x\n", cfg);
310 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
311 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
312 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
314 writel(cfg, ctrl_base + S5P_VIDTCON1);
315 udebug("vidtcon1 = %x\n", cfg);
319 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
320 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
322 writel(cfg, ctrl_base + S5P_VIDTCON2);
323 udebug("vidtcon2 = %x\n", cfg);
326 s5pc_fimd_set_par(win_id);
328 /* set memory address */
329 s5pc_fimd_set_buffer_address(win_id);
331 /* set buffer size */
332 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
333 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
334 udebug("vidaddr_pagewidth = %d\n", cfg);
337 s5pc_fimd_set_clock();
340 s5pc_fimd_lcd_on(win_id);
342 udebug("lcd controller init completed.\n");
347 ulong s5pc_fimd_calc_fbsize(void)
349 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));