2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/regs-fb.h>
31 #include <asm/arch/hardware.h>
36 /* LCD Panel definitions */
37 #define PANEL_WIDTH 480
38 #define PANEL_HEIGHT 800
39 #define S5P_LCD_BPP 32
45 #define S5PCFB_HRES 480
46 #define S5PCFB_VRES 800
48 #define S5PCFB_HRES_VIRTUAL 480
49 #define S5PCFB_VRES_VIRTUAL 800
51 #define S5PCFB_HRES_OSD 480
52 #define S5PCFB_VRES_OSD 800
54 #define S5P_VFRAME_FREQ 60
56 static unsigned int ctrl_base;
57 static unsigned long *lcd_base_addr;
59 extern unsigned long get_pll_clk(int pllreg);
61 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
63 lcd_base_addr = (unsigned long *)screen_base;
65 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
70 void s5pc_c100_gpio_setup(void)
72 /* set GPF0[0:7] for RGB Interface and Data lines */
73 writel(0x22222222, 0xE03000E0);
76 writel(0x22222222, 0xE0300100);
77 writel(0x22222222, 0xE0300120);
78 writel(0x2222, 0xE0300140);
80 /* set gpio configuration pin for MLCD_RST */
81 writel(0x10000000, 0xE0300C20);
83 /* set gpio configuration pin for MLCD_ON */
84 writel(0x1000, 0xE0300220);
85 writel(readl(0xE0300224) & 0xf7, 0xE0300224);
87 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */
88 writel(0x11100000, 0xE0300300);
91 void s5pc_c110_gpio_setup(void)
93 /* set GPF0[0:7] for RGB Interface and Data lines */
94 writel(0x22222222, 0xE0200120);
95 /* pull-up/down disable */
96 writel(0x0, 0xE0200128);
97 /* drive strength to max */
98 writel(0xffffffff, 0xE020012C);
101 writel(0x22222222, 0xE0200140);
102 writel(0x22222222, 0xE0200160);
103 writel(0x2222, 0xE0200180);
105 /* drive strength to max */
106 writel(0xffffffff, 0xE020014C);
107 writel(0xffffffff, 0xE020016C);
108 writel(0x000000ff, 0xE020018C);
110 /* pull-up/down disable */
111 writel(0x0, 0xE0200148);
112 writel(0x0, 0xE0200168);
113 writel(0x0, 0xE0200188);
115 /* display output path selection */
116 writel(0x2, 0xE0107008);
118 /* set gpio configuration pin for MLCD_RST */
119 writel(0x10000000, 0xE0200C20);
121 /* set gpio configuration pin for MLCD_ON */
122 writel(0x1000, 0xE0200260);
123 writel(readl(0xE0200264) & 0xf7, 0xE0200264);
125 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK, DISPLSY_SI and LCD_ID */
126 writel(0x10, 0xE02002E0);
127 writel(0x1110, 0xE0200340);
132 static void s5pc_fimd_set_par(unsigned int win_id)
134 unsigned int cfg = 0;
136 /* set window control */
137 cfg = readl(ctrl_base + S5P_WINCON(win_id));
139 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
140 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
141 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
142 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
144 /* DATAPATH is DMA */
145 cfg |= S5P_WINCON_DATAPATH_DMA;
148 cfg |= S5P_WINCON_WSWP_ENABLE;
150 /* dma burst is 16 */
151 cfg |= S5P_WINCON_BURSTLEN_16WORD;
153 /* pixel format is unpacked RGB888 */
154 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
156 writel(cfg, ctrl_base + S5P_WINCON(win_id));
157 udebug("wincon%d = %x\n", win_id, cfg);
159 /* set window position to x=0, y=0*/
160 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
161 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
162 udebug("window postion left,top = %x\n", cfg);
164 cfg = S5P_VIDOSD_RIGHT_X(PANEL_WIDTH - 1) |
165 S5P_VIDOSD_BOTTOM_Y(PANEL_HEIGHT - 1);
166 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
167 udebug("window postion right,bottom= %x\n", cfg);
169 /* set window size for window0*/
170 cfg = S5P_VIDOSD_SIZE(PANEL_WIDTH * PANEL_HEIGHT);
171 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
172 udebug("vidosd_c%d= %x\n", win_id, cfg);
177 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
179 unsigned long start_addr, end_addr;
181 start_addr = (unsigned long)lcd_base_addr;
182 end_addr = start_addr + ((PANEL_WIDTH * (S5P_LCD_BPP / 8))
185 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
186 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
188 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
193 static void s5pc_fimd_set_clock(vidinfo_t *vid)
195 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
196 unsigned long pixel_clock, src_clock, max_clock;
198 max_clock = 66 * 1000000;
200 pixel_clock = S5P_VFRAME_FREQ * (vid->vl_hpw + vid->vl_blw + vid->vl_elw + vid->vl_width) *
201 (vid->vl_vpw + vid->vl_bfw + vid->vl_efw + vid->vl_height);
203 src_clock = get_pll_clk(MPLL);
205 cfg = readl(ctrl_base + S5P_VIDCON0);
206 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
207 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
208 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
209 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
211 if (pixel_clock > max_clock)
212 pixel_clock = max_clock;
215 if (cpu_is_s5pc110())
216 mpll_ratio = (readl(0xE0100300) & 0xf0000) >> 16;
218 mpll_ratio = (readl(0xE0100304) & 0xf0) >> 4;
221 * It can get sorce clock speed as (mpll / mpll_ratio)
222 * because lcd controller uses hclk_dsys.
223 * mpll is a parent of hclk_dsys.
225 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
226 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
227 writel(cfg, ctrl_base + S5P_VIDCON0);
229 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
230 mpll_ratio, src_clock, pixel_clock, div);
235 void s5pc_fimd_lcd_init(vidinfo_t *vid)
237 unsigned int cfg = 0, rgb_mode, win_id = 0;
239 /* select register base according to cpu type */
240 if (cpu_is_s5pc110())
241 ctrl_base = 0xF8000000;
243 ctrl_base = 0xEE000000;
245 /* set output to RGB */
246 rgb_mode = MODE_RGB_P;
247 cfg = readl(ctrl_base + S5P_VIDCON0);
248 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
250 /* clock source is HCLK */
253 cfg |= S5P_VIDCON0_VIDOUT_RGB;
254 writel(cfg, ctrl_base + S5P_VIDCON0);
256 /* set display mode */
257 cfg = readl(ctrl_base + S5P_VIDCON0);
258 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
259 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
260 writel(cfg, ctrl_base + S5P_VIDCON0);
264 cfg |= S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISING_EDGE;
265 writel(cfg, ctrl_base + S5P_VIDCON1);
270 //cfg |= S5P_VIDTCON0_VBPDE(S5PCFB_VBPE - 1);
271 cfg |= S5P_VIDTCON0_VBPD(vid->vl_bfw - 1);
272 cfg |= S5P_VIDTCON0_VFPD(vid->vl_efw - 1);
273 cfg |= S5P_VIDTCON0_VSPW(vid->vl_vpw - 1);
274 writel(cfg, ctrl_base + S5P_VIDTCON0);
275 udebug("vidtcon0 = %x\n", cfg);
278 //cfg |= S5P_VIDTCON1_VFPDE(S5PCFB_VFPE - 1);
279 cfg |= S5P_VIDTCON1_HBPD(vid->vl_blw - 1);
280 cfg |= S5P_VIDTCON1_HFPD(vid->vl_elw - 1);
281 cfg |= S5P_VIDTCON1_HSPW(vid->vl_hpw - 1);
283 writel(cfg, ctrl_base + S5P_VIDTCON1);
284 udebug("vidtcon1 = %x\n", cfg);
288 cfg |= S5P_VIDTCON2_HOZVAL(PANEL_WIDTH - 1);
289 cfg |= S5P_VIDTCON2_LINEVAL(PANEL_HEIGHT - 1);
291 writel(cfg, ctrl_base + S5P_VIDTCON2);
292 udebug("vidtcon2 = %x\n", cfg);
295 s5pc_fimd_set_par(win_id);
297 /* set memory address */
298 s5pc_fimd_set_buffer_address(win_id);
300 /* set buffer size */
301 cfg = S5P_VIDADDR_PAGEWIDTH(PANEL_WIDTH * S5P_LCD_BPP / 8);
302 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
303 udebug("vidaddr_pagewidth = %d\n", cfg);
306 s5pc_fimd_set_clock(vid);
309 cfg = readl(ctrl_base + S5P_VIDCON0);
310 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
311 writel(cfg, ctrl_base + S5P_VIDCON0);
312 udebug("vidcon0 = %x\n", cfg);
315 cfg = readl(ctrl_base + S5P_WINCON(win_id));
316 cfg |= S5P_WINCON_ENWIN_ENABLE;
317 writel(cfg, ctrl_base + S5P_WINCON(win_id));
318 udebug("wincon%d=%x\n", win_id, cfg);
320 udebug("lcd controller init completed.\n");
325 ulong s5pc_fimd_calc_fbsize(void)
327 return (PANEL_WIDTH * PANEL_HEIGHT * (S5P_LCD_BPP / 8));