2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/regs-fb.h>
31 #include <asm/arch/hardware.h>
36 #define S5P_VFRAME_FREQ 60
38 static unsigned int ctrl_base;
39 static unsigned long *lcd_base_addr;
40 static vidinfo_t *pvid = NULL;
42 extern unsigned long get_pll_clk(int pllreg);
44 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
46 lcd_base_addr = (unsigned long *)screen_base;
48 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
53 void s5pc_c100_gpio_setup(void)
55 /* set GPF0[0:7] for RGB Interface and Data lines */
56 writel(0x22222222, 0xE03000E0);
59 writel(0x22222222, 0xE0300100);
60 writel(0x22222222, 0xE0300120);
61 writel(0x2222, 0xE0300140);
63 /* set gpio configuration pin for MLCD_RST */
64 writel(0x10000000, 0xE0300C20);
66 /* set gpio configuration pin for MLCD_ON */
67 writel(0x1000, 0xE0300220);
68 writel(readl(0xE0300224) & 0xf7, 0xE0300224);
70 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK and DISPLSY_SI */
71 writel(0x11100000, 0xE0300300);
74 void s5pc_c110_gpio_setup(void)
76 /* set GPF0[0:7] for RGB Interface and Data lines (32bit) */
77 writel(0x22222222, 0xE0200120);
78 /* pull-up/down disable */
79 writel(0x0, 0xE0200128);
80 /* drive strength to max (24bit) */
81 writel(0xffffff, 0xE020012C);
83 /* set Data lines (32bit) */
84 writel(0x22222222, 0xE0200140);
85 writel(0x22222222, 0xE0200160);
86 writel(readl(0xE0200180) & 0xFF0000, 0xE0200180);
87 writel(readl(0xE0200180) | 0x002222, 0xE0200180);
89 /* drive strength to max (24bit) */
90 writel(0xffffff, 0xE020014C);
91 writel(0xffffff, 0xE020016C);
92 /* [11:0](drive stength level), [15:12](none), [21:16](Slew Rate) */
93 writel(readl(0xE020018C) & 0x3FFF00, 0xE020018C);
94 writel(readl(0xE020018C) | 0x0000FF, 0xE020018C);
96 /* pull-up/down disable */
97 writel(0x0, 0xE0200148);
98 writel(0x0, 0xE0200168);
99 writel(0x0, 0xE0200188);
101 /* display output path selection (only [1:0] valid) */
102 writel(0x2, 0xE0107008);
104 /* set gpio configuration pin for MLCD_RST */
105 writel(readl(0xE0200C20) & 0x0fffffff, 0xE0200C20);
106 writel(readl(0xE0200C20) | 0x10000000, 0xE0200C20);
108 /* set gpio configuration pin for MLCD_ON and then to LOW */
109 writel(readl(0xE0200260) & 0xFFFF0FFF, 0xE0200260);
110 writel(readl(0xE0200260) | 0x00001000, 0xE0200260);
111 writel(readl(0xE0200264) & 0xf7, 0xE0200264);
113 /* set gpio configuration pin for DISPLAY_CS, DISPLAY_CLK, DISPLSY_SI and LCD_ID */
114 writel(readl(0xE02002E0) & 0xFFFFFF0F, 0xE02002E0);
115 writel(readl(0xE02002E0) | 0x00000010, 0xE02002E0);
116 writel(readl(0xE0200340) & 0xFFFF000F, 0xE0200340);
117 writel(readl(0xE0200340) | 0x00001110, 0xE0200340);
122 static void s5pc_fimd_set_par(unsigned int win_id)
124 unsigned int cfg = 0;
126 /* set window control */
127 cfg = readl(ctrl_base + S5P_WINCON(win_id));
129 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
130 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
131 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
132 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
134 /* DATAPATH is DMA */
135 cfg |= S5P_WINCON_DATAPATH_DMA;
138 cfg |= S5P_WINCON_WSWP_ENABLE;
140 /* dma burst is 16 */
141 cfg |= S5P_WINCON_BURSTLEN_16WORD;
143 /* pixel format is unpacked RGB888 */
144 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
146 writel(cfg, ctrl_base + S5P_WINCON(win_id));
147 udebug("wincon%d = %x\n", win_id, cfg);
149 /* set window position to x=0, y=0*/
150 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
151 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
152 udebug("window postion left,top = %x\n", cfg);
154 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
155 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
156 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
157 udebug("window postion right,bottom= %x\n", cfg);
159 /* set window size for window0*/
160 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
161 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
162 udebug("vidosd_c%d= %x\n", win_id, cfg);
167 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
169 unsigned long start_addr, end_addr;
171 start_addr = (unsigned long)lcd_base_addr;
172 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
175 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
176 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
178 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
183 static void s5pc_fimd_set_clock(void)
185 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
186 unsigned long pixel_clock, src_clock, max_clock;
188 max_clock = 66 * 1000000;
190 pixel_clock = S5P_VFRAME_FREQ * (pvid->vl_hpw + pvid->vl_blw +
191 pvid->vl_elw + pvid->vl_width) * (pvid->vl_vpw +
192 pvid->vl_bfw + pvid->vl_efw + pvid->vl_height);
194 src_clock = get_pll_clk(MPLL);
196 cfg = readl(ctrl_base + S5P_VIDCON0);
197 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
198 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
199 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
200 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
202 if (pixel_clock > max_clock)
203 pixel_clock = max_clock;
206 if (cpu_is_s5pc110())
207 mpll_ratio = (readl(0xE0100300) & 0xf0000) >> 16;
209 mpll_ratio = (readl(0xE0100304) & 0xf0) >> 4;
212 * It can get source clock speed as (mpll / mpll_ratio)
213 * because lcd controller uses hclk_dsys.
214 * mpll is a parent of hclk_dsys.
216 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
217 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
218 writel(cfg, ctrl_base + S5P_VIDCON0);
220 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
221 mpll_ratio, src_clock, pixel_clock, div);
226 static s5pc_fimd_lcd_on(unsigned int win_id)
231 cfg = readl(ctrl_base + S5P_VIDCON0);
232 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
233 writel(cfg, ctrl_base + S5P_VIDCON0);
234 udebug("vidcon0 = %x\n", cfg);
237 cfg = readl(ctrl_base + S5P_WINCON(win_id));
238 cfg |= S5P_WINCON_ENWIN_ENABLE;
239 writel(cfg, ctrl_base + S5P_WINCON(win_id));
240 udebug("wincon%d=%x\n", win_id, cfg);
243 void s5pc_fimd_lcd_init(vidinfo_t *vid)
245 unsigned int cfg = 0, rgb_mode, win_id = 0;
247 /* store panel info to global variable */
250 /* select register base according to cpu type */
251 if (cpu_is_s5pc110())
252 ctrl_base = 0xF8000000;
254 ctrl_base = 0xEE000000;
256 /* set output to RGB */
257 rgb_mode = MODE_RGB_P;
258 cfg = readl(ctrl_base + S5P_VIDCON0);
259 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
261 /* clock source is HCLK */
264 cfg |= S5P_VIDCON0_VIDOUT_RGB;
265 writel(cfg, ctrl_base + S5P_VIDCON0);
267 /* set display mode */
268 cfg = readl(ctrl_base + S5P_VIDCON0);
269 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
270 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
271 writel(cfg, ctrl_base + S5P_VIDCON0);
275 cfg |= S5P_VIDCON1_IVDEN_INVERT | S5P_VIDCON1_IVCLK_RISING_EDGE;
276 writel(cfg, ctrl_base + S5P_VIDCON1);
280 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_bfw - 1);
281 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_efw - 1);
282 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vpw - 1);
283 writel(cfg, ctrl_base + S5P_VIDTCON0);
284 udebug("vidtcon0 = %x\n", cfg);
287 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_blw - 1);
288 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_elw - 1);
289 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hpw - 1);
291 writel(cfg, ctrl_base + S5P_VIDTCON1);
292 udebug("vidtcon1 = %x\n", cfg);
296 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
297 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
299 writel(cfg, ctrl_base + S5P_VIDTCON2);
300 udebug("vidtcon2 = %x\n", cfg);
303 s5pc_fimd_set_par(win_id);
305 /* set memory address */
306 s5pc_fimd_set_buffer_address(win_id);
308 /* set buffer size */
309 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
310 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
311 udebug("vidaddr_pagewidth = %d\n", cfg);
314 s5pc_fimd_set_clock();
317 s5pc_fimd_lcd_on(win_id);
319 udebug("lcd controller init completed.\n");
324 ulong s5pc_fimd_calc_fbsize(void)
326 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));