drivers/video/s5p-fimd.c

   1 /*
   2  * S5PC100 and S5PC110 LCD Controller Specific driver.
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <common.h>
  24 #include <stdarg.h>
  25 #include <linux/types.h>
  26 #include <asm/io.h>
  27 #include <lcd.h>
  28
  29 #include <asm/arch/clk.h>
  30 #include <asm/arch/cpu.h>
  31 #include <asm/arch/regs-fb.h>
  32 #include <asm/arch/gpio.h>
  33 #include "s5p-fb.h"
  34
  35 /* CLOCK DIVIDER 0 */
  36 #define CLK_DIV0        0xE0100300
  37 #define CLK_DIV1        0xE0100304
  38
  39 /* LCD CONTROLLER REGISTER BASE */
  40 #define S5PC100_LCRB            0xEE000000
  41 #define S5PC110_LCRB            0xF8000000
  42
  43 #define MPLL 1
  44
  45 static unsigned int ctrl_base;
  46 static unsigned long *lcd_base_addr;
  47 static vidinfo_t *pvid = NULL;
  48
  49 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
  50 {
  51         lcd_base_addr = (unsigned long *)screen_base;
  52
  53         udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
  54
  55         return;
  56 }
  57
  58 static void s5pc_fimd_set_dualrgb(unsigned int enabled)
  59 {
  60         unsigned int cfg = 0;
  61
  62         if (enabled) {
  63                 cfg = S5P_DUALRGB_BYPASS_DUAL | S5P_DUALRGB_LINESPLIT |
  64                         S5P_DUALRGB_VDEN_EN_ENABLE;
  65
  66                 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
  67                 cfg |= S5P_DUALRGB_SUB_CNT(pvid->vl_col/2) | S5P_DUALRGB_MAIN_CNT(0);
  68         } else
  69                 cfg = 0;
  70
  71         writel(cfg, ctrl_base + S5P_DUALRGB);
  72 }
  73
  74 static void s5pc_fimd_set_par(unsigned int win_id)
  75 {
  76         unsigned int cfg = 0;
  77
  78         /* set window control */
  79         cfg = readl(ctrl_base + S5P_WINCON(win_id));
  80
  81         cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
  82                 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
  83                 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
  84                 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
  85
  86         /* DATAPATH is DMA */
  87         cfg |= S5P_WINCON_DATAPATH_DMA;
  88
  89         /* bpp is 32 */
  90         cfg |= S5P_WINCON_WSWP_ENABLE;
  91
  92         /* dma burst is 16 */
  93         cfg |= S5P_WINCON_BURSTLEN_16WORD;
  94
  95         /* pixel format is unpacked RGB888 */
  96         cfg |= S5P_WINCON_BPPMODE_24BPP_888;
  97
  98         writel(cfg, ctrl_base + S5P_WINCON(win_id));
  99         udebug("wincon%d = %x\n", win_id, cfg);
 100
 101         /* set window position to x=0, y=0*/
 102         cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
 103         writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
 104         udebug("window postion left,top = %x\n", cfg);
 105
 106         cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
 107                 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
 108         writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
 109         udebug("window postion right,bottom= %x\n", cfg);
 110
 111         /* set window size for window0*/
 112         cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
 113         writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
 114         udebug("vidosd_c%d= %x\n", win_id, cfg);
 115
 116         return;
 117 }
 118
 119 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
 120 {
 121         unsigned long start_addr, end_addr;
 122
 123         start_addr = (unsigned long)lcd_base_addr;
 124         end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
 125                 * pvid->vl_row);
 126
 127         writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
 128         writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
 129
 130         udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
 131
 132         return;
 133 }
 134
 135 static void s5pc_fimd_set_clock(void)
 136 {
 137         unsigned int cfg = 0, div = 0, mpll_ratio = 0;
 138         unsigned long pixel_clock, src_clock, max_clock;
 139
 140         s5pc1xx_clock_init();
 141
 142         max_clock = 86 * 1000000;
 143
 144         if (pvid->dual_lcd_enabled)
 145                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 146                         pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
 147                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 148         else
 149                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 150                         pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
 151                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 152
 153
 154         if (get_pll_clk == NULL) {
 155                 printf("get_pll_clk is null.\n");
 156                 return;
 157         }
 158         src_clock = get_pll_clk(MPLL);
 159
 160         cfg = readl(ctrl_base + S5P_VIDCON0);
 161         cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
 162                 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
 163         cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
 164                 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
 165
 166         if (pixel_clock > max_clock)
 167                 pixel_clock = max_clock;
 168
 169         /* get mpll ratio */
 170         if (cpu_is_s5pc110())
 171                 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
 172         else
 173                 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
 174
 175         /*
 176          * It can get source clock speed as (mpll / mpll_ratio)
 177          * because lcd controller uses hclk_dsys.
 178          * mpll is a parent of hclk_dsys.
 179          */
 180         div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
 181
 182         /* in case of dual lcd mode. */
 183         if (pvid->dual_lcd_enabled)
 184                 div--;
 185
 186         cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
 187         writel(cfg, ctrl_base + S5P_VIDCON0);
 188
 189         udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
 190                 mpll_ratio, src_clock, pixel_clock, div);
 191
 192         return;
 193 }
 194
 195 static void s5pc_fimd_lcd_on(unsigned int win_id)
 196 {
 197         unsigned int cfg = 0;
 198
 199         /* display on */
 200         cfg = readl(ctrl_base + S5P_VIDCON0);
 201         cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
 202         writel(cfg, ctrl_base + S5P_VIDCON0);
 203         udebug("vidcon0 = %x\n", cfg);
 204 }
 205
 206 static void s5pc_fimd_window_on(unsigned int win_id)
 207 {
 208         unsigned int cfg = 0;
 209
 210         /* enable window */
 211         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 212         cfg |= S5P_WINCON_ENWIN_ENABLE;
 213         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 214         udebug("wincon%d=%x\n", win_id, cfg);
 215
 216         /* evt1 */
 217         cfg = readl(ctrl_base + S5P_WINSHMAP);
 218         cfg |= S5P_WINSHMAP_CH_ENABLE(win_id);
 219         writel(cfg, ctrl_base + S5P_WINSHMAP);
 220 }
 221
 222 void s5pc_fimd_lcd_off(unsigned int win_id)
 223 {
 224         unsigned int cfg = 0;
 225
 226         cfg = readl(ctrl_base + S5P_VIDCON0);
 227         cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
 228         writel(cfg, ctrl_base + S5P_VIDCON0);
 229 }
 230
 231 void s5pc_fimd_window_off(unsigned int win_id)
 232 {
 233         unsigned int cfg = 0;
 234
 235         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 236         cfg &= S5P_WINCON_ENWIN_DISABLE;
 237         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 238
 239         /* evt1 */
 240         cfg = readl(ctrl_base + S5P_WINSHMAP);
 241         cfg &= ~S5P_WINSHMAP_CH_DISABLE(win_id);
 242         writel(cfg, ctrl_base + S5P_WINSHMAP);
 243 }
 244
 245 void s5pc_fimd_lcd_init(vidinfo_t *vid)
 246 {
 247         unsigned int cfg = 0, rgb_mode, win_id = 3;
 248
 249         /* store panel info to global variable */
 250         pvid = vid;
 251
 252         /* select register base according to cpu type */
 253         if (cpu_is_s5pc110())
 254                 ctrl_base = S5PC110_LCRB;
 255         else
 256                 ctrl_base = S5PC100_LCRB;
 257
 258         /* set output to RGB */
 259         rgb_mode = MODE_RGB_P;
 260         cfg = readl(ctrl_base + S5P_VIDCON0);
 261         cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
 262
 263         /* clock source is HCLK */
 264         cfg |= 0 << 2;
 265
 266         cfg |= S5P_VIDCON0_VIDOUT_RGB;
 267         writel(cfg, ctrl_base + S5P_VIDCON0);
 268
 269         /* set display mode */
 270         cfg = readl(ctrl_base + S5P_VIDCON0);
 271         cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
 272         cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
 273         writel(cfg, ctrl_base + S5P_VIDCON0);
 274
 275         /* set polarity */
 276         cfg = 0;
 277         if (!pvid->vl_clkp)
 278                 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
 279         if (!pvid->vl_hsp)
 280                 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
 281         if (!pvid->vl_vsp)
 282                 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
 283         if (!pvid->vl_dp)
 284                 cfg |= S5P_VIDCON1_IVDEN_INVERT;
 285
 286         writel(cfg, ctrl_base + S5P_VIDCON1);
 287
 288         /* set timing */
 289         cfg = 0;
 290         cfg |= S5P_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
 291         cfg |= S5P_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
 292         cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vspw - 1);
 293         writel(cfg, ctrl_base + S5P_VIDTCON0);
 294         udebug("vidtcon0 = %x\n", cfg);
 295
 296         cfg = 0;
 297         cfg |= S5P_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
 298         cfg |= S5P_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
 299         cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hspw - 1);
 300
 301         writel(cfg, ctrl_base + S5P_VIDTCON1);
 302         udebug("vidtcon1 = %x\n", cfg);
 303
 304         /* set lcd size */
 305         cfg = 0;
 306         cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
 307         cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
 308
 309         writel(cfg, ctrl_base + S5P_VIDTCON2);
 310         udebug("vidtcon2 = %x\n", cfg);
 311
 312         /* set par */
 313         s5pc_fimd_set_par(win_id);
 314
 315         /* set memory address */
 316         s5pc_fimd_set_buffer_address(win_id);
 317
 318         /* set buffer size */
 319         cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
 320         writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
 321         udebug("vidaddr_pagewidth = %d\n", cfg);
 322
 323         /* set clock */
 324         s5pc_fimd_set_clock();
 325
 326         /* set rgb mode to dual lcd. */
 327         if (pvid->dual_lcd_enabled)
 328                 s5pc_fimd_set_dualrgb(1);
 329         else
 330                 s5pc_fimd_set_dualrgb(0);
 331
 332         /* display on */
 333         s5pc_fimd_lcd_on(win_id);
 334
 335         /* window on */
 336         s5pc_fimd_window_on(win_id);
 337
 338         udebug("lcd controller init completed.\n");
 339
 340         return;
 341 }
 342
 343 ulong s5pc_fimd_calc_fbsize(void)
 344 {
 345         return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));
 346 }