2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #include <asm/arch/clk.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/regs-fb.h>
32 #include <asm/arch/gpio.h>
36 #define CLK_DIV0 0xE0100300
37 #define CLK_DIV1 0xE0100304
39 /* LCD CONTROLLER REGISTER BASE */
40 #define S5PC100_LCRB 0xEE000000
41 #define S5PC110_LCRB 0xF8000000
45 static unsigned int ctrl_base;
46 static unsigned long *lcd_base_addr;
47 static vidinfo_t *pvid = NULL;
49 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
51 lcd_base_addr = (unsigned long *)screen_base;
53 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
58 static void s5pc_fimd_set_dualrgb(unsigned int enabled)
63 cfg = S5P_DUALRGB_BYPASS_DUAL | S5P_DUALRGB_LINESPLIT |
64 S5P_DUALRGB_VDEN_EN_ENABLE;
66 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
67 cfg |= S5P_DUALRGB_SUB_CNT(pvid->vl_col/2) | S5P_DUALRGB_MAIN_CNT(0);
71 writel(cfg, ctrl_base + S5P_DUALRGB);
74 static void s5pc_fimd_set_par(unsigned int win_id)
78 /* set window control */
79 cfg = readl(ctrl_base + S5P_WINCON(win_id));
81 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
82 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
83 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
84 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
87 cfg |= S5P_WINCON_DATAPATH_DMA;
90 cfg |= S5P_WINCON_WSWP_ENABLE;
93 cfg |= S5P_WINCON_BURSTLEN_16WORD;
95 /* pixel format is unpacked RGB888 */
96 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
98 writel(cfg, ctrl_base + S5P_WINCON(win_id));
99 udebug("wincon%d = %x\n", win_id, cfg);
101 /* set window position to x=0, y=0*/
102 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
103 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
104 udebug("window postion left,top = %x\n", cfg);
106 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
107 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
108 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
109 udebug("window postion right,bottom= %x\n", cfg);
111 /* set window size for window0*/
112 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
113 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
114 udebug("vidosd_c%d= %x\n", win_id, cfg);
119 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
121 unsigned long start_addr, end_addr;
123 start_addr = (unsigned long)lcd_base_addr;
124 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
127 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
128 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
130 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
135 static void s5pc_fimd_set_clock(void)
137 unsigned int cfg = 0, div = 0, mpll_ratio = 0;
138 unsigned long pixel_clock, src_clock, max_clock;
140 s5pc1xx_clock_init();
142 max_clock = 86 * 1000000;
144 if (pvid->dual_lcd_enabled)
145 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
146 pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
147 pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
149 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
150 pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
151 pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
154 if (get_pll_clk == NULL) {
155 printf("get_pll_clk is null.\n");
158 src_clock = get_pll_clk(MPLL);
160 cfg = readl(ctrl_base + S5P_VIDCON0);
161 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
162 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
163 cfg |= (S5P_VIDCON0_CLKSEL_HCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
164 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
166 if (pixel_clock > max_clock)
167 pixel_clock = max_clock;
170 if (cpu_is_s5pc110())
171 mpll_ratio = (readl(CLK_DIV0) & 0xf0000) >> 16;
173 mpll_ratio = (readl(CLK_DIV1) & 0xf0) >> 4;
176 * It can get source clock speed as (mpll / mpll_ratio)
177 * because lcd controller uses hclk_dsys.
178 * mpll is a parent of hclk_dsys.
180 div = (unsigned int)((src_clock / (mpll_ratio + 1)) / pixel_clock);
182 /* in case of dual lcd mode. */
183 if (pvid->dual_lcd_enabled)
186 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
187 writel(cfg, ctrl_base + S5P_VIDCON0);
189 udebug("mpll_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
190 mpll_ratio, src_clock, pixel_clock, div);
195 static void s5pc_fimd_lcd_on(unsigned int win_id)
197 unsigned int cfg = 0;
200 cfg = readl(ctrl_base + S5P_VIDCON0);
201 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
202 writel(cfg, ctrl_base + S5P_VIDCON0);
203 udebug("vidcon0 = %x\n", cfg);
206 cfg = readl(ctrl_base + S5P_WINCON(win_id));
207 cfg |= S5P_WINCON_ENWIN_ENABLE;
208 writel(cfg, ctrl_base + S5P_WINCON(win_id));
209 udebug("wincon%d=%x\n", win_id, cfg);
212 void s5pc_fimc_lcd_off(unsigned int win_id)
214 unsigned int cfg = 0;
216 cfg = readl(ctrl_base + S5P_VIDCON0);
217 cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
218 writel(cfg, ctrl_base + S5P_VIDCON0);
220 cfg = readl(ctrl_base + S5P_WINCON(win_id));
221 cfg &= S5P_WINCON_ENWIN_DISABLE;
222 writel(cfg, ctrl_base + S5P_WINCON(win_id));
226 void s5pc_fimd_lcd_init(vidinfo_t *vid)
228 unsigned int cfg = 0, rgb_mode, win_id = 3;
230 /* store panel info to global variable */
233 /* select register base according to cpu type */
234 if (cpu_is_s5pc110())
235 ctrl_base = S5PC110_LCRB;
237 ctrl_base = S5PC100_LCRB;
239 /* set output to RGB */
240 rgb_mode = MODE_RGB_P;
241 cfg = readl(ctrl_base + S5P_VIDCON0);
242 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
244 /* clock source is HCLK */
247 cfg |= S5P_VIDCON0_VIDOUT_RGB;
248 writel(cfg, ctrl_base + S5P_VIDCON0);
250 /* set display mode */
251 cfg = readl(ctrl_base + S5P_VIDCON0);
252 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
253 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
254 writel(cfg, ctrl_base + S5P_VIDCON0);
259 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
261 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
263 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
265 cfg |= S5P_VIDCON1_IVDEN_INVERT;
267 writel(cfg, ctrl_base + S5P_VIDCON1);
271 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
272 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
273 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vspw - 1);
274 writel(cfg, ctrl_base + S5P_VIDTCON0);
275 udebug("vidtcon0 = %x\n", cfg);
278 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
279 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
280 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hspw - 1);
282 writel(cfg, ctrl_base + S5P_VIDTCON1);
283 udebug("vidtcon1 = %x\n", cfg);
287 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
288 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
290 writel(cfg, ctrl_base + S5P_VIDTCON2);
291 udebug("vidtcon2 = %x\n", cfg);
294 s5pc_fimd_set_par(win_id);
296 /* set memory address */
297 s5pc_fimd_set_buffer_address(win_id);
299 /* set buffer size */
300 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
301 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
302 udebug("vidaddr_pagewidth = %d\n", cfg);
305 s5pc_fimd_set_clock();
307 /* set rgb mode to dual lcd. */
308 if (pvid->dual_lcd_enabled)
309 s5pc_fimd_set_dualrgb(1);
311 s5pc_fimd_set_dualrgb(0);
314 s5pc_fimd_lcd_on(win_id);
316 udebug("lcd controller init completed.\n");
321 ulong s5pc_fimd_calc_fbsize(void)
323 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));