drivers/video/s5p-fimd.c

   1 /*
   2  * S5PC100 and S5PC110 LCD Controller Specific driver.
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <common.h>
  24 #include <stdarg.h>
  25 #include <linux/types.h>
  26 #include <asm/io.h>
  27 #include <lcd.h>
  28 #include <div64.h>
  29
  30 #include <asm/arch/clk.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/cpu.h>
  33 #include <asm/arch/regs-fb.h>
  34 #include <asm/arch/gpio.h>
  35 #include "s5p-fb.h"
  36
  37 /* LCD CONTROLLER REGISTER BASE */
  38 #define S5PC100_LCRB            0xEE000000
  39 #define S5PC110_LCRB            0xF8000000
  40
  41 #define MPLL 1
  42
  43 static unsigned int ctrl_base;
  44 static unsigned long *lcd_base_addr;
  45 static vidinfo_t *pvid = NULL;
  46
  47 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
  48 {
  49         lcd_base_addr = (unsigned long *)screen_base;
  50
  51         udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
  52
  53         return;
  54 }
  55
  56 static void s5pc_fimd_set_dualrgb(unsigned int enabled)
  57 {
  58         unsigned int cfg = 0;
  59
  60         if (enabled) {
  61                 cfg = S5P_DUALRGB_BYPASS_DUAL | S5P_DUALRGB_LINESPLIT |
  62                         S5P_DUALRGB_VDEN_EN_ENABLE;
  63
  64                 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
  65                 cfg |= S5P_DUALRGB_SUB_CNT(pvid->vl_col/2) | S5P_DUALRGB_MAIN_CNT(0);
  66         } else
  67                 cfg = 0;
  68
  69         writel(cfg, ctrl_base + S5P_DUALRGB);
  70 }
  71
  72 static void s5pc_fimd_set_par(unsigned int win_id)
  73 {
  74         unsigned int cfg = 0;
  75
  76         /* set window control */
  77         cfg = readl(ctrl_base + S5P_WINCON(win_id));
  78
  79         cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
  80                 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
  81                 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
  82                 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
  83
  84         /* DATAPATH is DMA */
  85         cfg |= S5P_WINCON_DATAPATH_DMA;
  86
  87         /* bpp is 32 */
  88         cfg |= S5P_WINCON_WSWP_ENABLE;
  89
  90         /* dma burst is 16 */
  91         cfg |= S5P_WINCON_BURSTLEN_16WORD;
  92
  93         /* pixel format is unpacked RGB888 */
  94         cfg |= S5P_WINCON_BPPMODE_24BPP_888;
  95
  96         writel(cfg, ctrl_base + S5P_WINCON(win_id));
  97         udebug("wincon%d = %x\n", win_id, cfg);
  98
  99         /* set window position to x=0, y=0*/
 100         cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
 101         writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
 102         udebug("window postion left,top = %x\n", cfg);
 103
 104         cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
 105                 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
 106         writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
 107         udebug("window postion right,bottom= %x\n", cfg);
 108
 109         /* set window size for window0*/
 110         cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
 111         writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
 112         udebug("vidosd_c%d= %x\n", win_id, cfg);
 113
 114         return;
 115 }
 116
 117 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
 118 {
 119         unsigned long start_addr, end_addr;
 120
 121         start_addr = (unsigned long)lcd_base_addr;
 122         end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
 123                 * pvid->vl_row);
 124
 125         writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
 126         writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
 127
 128         udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
 129
 130         return;
 131 }
 132
 133 static void s5pc_fimd_set_clock(void)
 134 {
 135         unsigned int cfg = 0, div = 0, fimd_ratio = 0, temp = 0,
 136                      remainder, remainder_div;
 137         unsigned long pixel_clock, src_clock, max_clock;
 138         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 139         u64 div64;
 140
 141         s5pc1xx_clock_init();
 142
 143         max_clock = 86 * 1000000;
 144
 145         if (pvid->dual_lcd_enabled)
 146                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 147                         pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
 148                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 149         else
 150                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 151                         pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
 152                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 153
 154
 155         if (get_pll_clk == NULL) {
 156                 printf("get_pll_clk is null.\n");
 157                 return;
 158         }
 159         src_clock = get_pll_clk(MPLL);
 160
 161         cfg = readl(ctrl_base + S5P_VIDCON0);
 162         cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
 163                 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
 164         cfg |= (S5P_VIDCON0_CLKSEL_SCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
 165                 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
 166
 167         if (pixel_clock > max_clock)
 168                 pixel_clock = max_clock;
 169
 170         /* set source clock to SCLKMPLL. */
 171         temp = readl(&clk->src1);
 172         writel((temp & ~0xf00000) | 0x600000, &clk->src1);
 173         temp = 0;
 174
 175         /* set fimd ratio to 3. */
 176         temp = readl(&clk->div1);
 177         writel((temp & ~0xf00000) | 0x200000, &clk->div1);
 178         temp = 0;
 179
 180         /* get mpll ratio */
 181         temp = readl(&clk->div1);
 182         fimd_ratio = (temp & 0xf00000) >> 20;
 183         temp = 0;
 184
 185         div64 = ((u64)src_clock) / (fimd_ratio + 1);
 186
 187         /* get quotient and remainder. */
 188         remainder = do_div(div64, pixel_clock);
 189         div = (u32) div64;
 190
 191         remainder *= 10;
 192         remainder_div = remainder / pixel_clock;
 193
 194         /* round about one places of decimals. */
 195         if (remainder_div >= 5)
 196                 div++;
 197
 198         /* in case of dual lcd mode. */
 199         if (pvid->dual_lcd_enabled)
 200                 div--;
 201
 202         cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
 203         writel(cfg, ctrl_base + S5P_VIDCON0);
 204
 205         udebug("fimd_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
 206                 fimd_ratio, src_clock / (fimd_ratio + 1), pixel_clock, div);
 207
 208         return;
 209 }
 210
 211 static void s5pc_fimd_lcd_on(unsigned int win_id)
 212 {
 213         unsigned int cfg = 0;
 214
 215         /* display on */
 216         cfg = readl(ctrl_base + S5P_VIDCON0);
 217         cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
 218         writel(cfg, ctrl_base + S5P_VIDCON0);
 219         udebug("vidcon0 = %x\n", cfg);
 220 }
 221
 222 static void s5pc_fimd_window_on(unsigned int win_id)
 223 {
 224         unsigned int cfg = 0;
 225
 226         /* enable window */
 227         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 228         cfg |= S5P_WINCON_ENWIN_ENABLE;
 229         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 230         udebug("wincon%d=%x\n", win_id, cfg);
 231
 232         /* evt1 */
 233         cfg = readl(ctrl_base + S5P_WINSHMAP);
 234         cfg |= S5P_WINSHMAP_CH_ENABLE(win_id);
 235         writel(cfg, ctrl_base + S5P_WINSHMAP);
 236 }
 237
 238 void s5pc_fimd_lcd_off(unsigned int win_id)
 239 {
 240         unsigned int cfg = 0;
 241
 242         cfg = readl(ctrl_base + S5P_VIDCON0);
 243         cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
 244         writel(cfg, ctrl_base + S5P_VIDCON0);
 245 }
 246
 247 void s5pc_fimd_window_off(unsigned int win_id)
 248 {
 249         unsigned int cfg = 0;
 250
 251         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 252         cfg &= S5P_WINCON_ENWIN_DISABLE;
 253         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 254
 255         /* evt1 */
 256         cfg = readl(ctrl_base + S5P_WINSHMAP);
 257         cfg &= ~S5P_WINSHMAP_CH_DISABLE(win_id);
 258         writel(cfg, ctrl_base + S5P_WINSHMAP);
 259 }
 260
 261 void s5pc_fimd_lcd_init(vidinfo_t *vid)
 262 {
 263         unsigned int cfg = 0, rgb_mode, win_id = 3;
 264
 265         /* store panel info to global variable */
 266         pvid = vid;
 267
 268         /* select register base according to cpu type */
 269         if (cpu_is_s5pc110())
 270                 ctrl_base = S5PC110_LCRB;
 271         else
 272                 ctrl_base = S5PC100_LCRB;
 273
 274         /* set output to RGB */
 275         rgb_mode = MODE_RGB_P;
 276         cfg = readl(ctrl_base + S5P_VIDCON0);
 277         cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
 278
 279         /* clock source is HCLK */
 280         cfg |= 0 << 2;
 281
 282         cfg |= S5P_VIDCON0_VIDOUT_RGB;
 283         writel(cfg, ctrl_base + S5P_VIDCON0);
 284
 285         /* set display mode */
 286         cfg = readl(ctrl_base + S5P_VIDCON0);
 287         cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
 288         cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
 289         writel(cfg, ctrl_base + S5P_VIDCON0);
 290
 291         /* set polarity */
 292         cfg = 0;
 293         if (!pvid->vl_clkp)
 294                 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
 295         if (!pvid->vl_hsp)
 296                 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
 297         if (!pvid->vl_vsp)
 298                 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
 299         if (!pvid->vl_dp)
 300                 cfg |= S5P_VIDCON1_IVDEN_INVERT;
 301
 302         writel(cfg, ctrl_base + S5P_VIDCON1);
 303
 304         /* set timing */
 305         cfg = 0;
 306         cfg |= S5P_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
 307         cfg |= S5P_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
 308         cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vspw - 1);
 309         writel(cfg, ctrl_base + S5P_VIDTCON0);
 310         udebug("vidtcon0 = %x\n", cfg);
 311
 312         cfg = 0;
 313         cfg |= S5P_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
 314         cfg |= S5P_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
 315         cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hspw - 1);
 316
 317         writel(cfg, ctrl_base + S5P_VIDTCON1);
 318         udebug("vidtcon1 = %x\n", cfg);
 319
 320         /* set lcd size */
 321         cfg = 0;
 322         cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
 323         cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
 324
 325         writel(cfg, ctrl_base + S5P_VIDTCON2);
 326         udebug("vidtcon2 = %x\n", cfg);
 327
 328         /* set par */
 329         s5pc_fimd_set_par(win_id);
 330
 331         /* set memory address */
 332         s5pc_fimd_set_buffer_address(win_id);
 333
 334         /* set buffer size */
 335         cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
 336         writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
 337         udebug("vidaddr_pagewidth = %d\n", cfg);
 338
 339         /* set clock */
 340         s5pc_fimd_set_clock();
 341
 342         /* set rgb mode to dual lcd. */
 343         if (pvid->dual_lcd_enabled)
 344                 s5pc_fimd_set_dualrgb(1);
 345         else
 346                 s5pc_fimd_set_dualrgb(0);
 347
 348         /* display on */
 349         s5pc_fimd_lcd_on(win_id);
 350
 351         /* window on */
 352         s5pc_fimd_window_on(win_id);
 353
 354         udebug("lcd controller init completed.\n");
 355
 356         return;
 357 }
 358
 359 ulong s5pc_fimd_calc_fbsize(void)
 360 {
 361         return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));
 362 }