2 * S5PC100 and S5PC110 LCD Controller Specific driver.
4 * Author: InKi Dae <inki.dae@samsung.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
30 #include <asm/arch/clk.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/cpu.h>
33 #include <asm/arch/regs-fb.h>
34 #include <asm/arch/gpio.h>
37 /* LCD CONTROLLER REGISTER BASE */
38 #define S5PC100_LCRB 0xEE000000
39 #define S5PC110_LCRB 0xF8000000
43 static unsigned int ctrl_base;
44 static unsigned long *lcd_base_addr;
45 static vidinfo_t *pvid = NULL;
47 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
49 lcd_base_addr = (unsigned long *)screen_base;
51 udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
56 static void s5pc_fimd_set_dualrgb(unsigned int enabled)
61 cfg = S5P_DUALRGB_BYPASS_DUAL | S5P_DUALRGB_LINESPLIT |
62 S5P_DUALRGB_VDEN_EN_ENABLE;
64 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
65 cfg |= S5P_DUALRGB_SUB_CNT(pvid->vl_col/2) | S5P_DUALRGB_MAIN_CNT(0);
69 writel(cfg, ctrl_base + S5P_DUALRGB);
72 static void s5pc_fimd_set_par(unsigned int win_id)
76 /* set window control */
77 cfg = readl(ctrl_base + S5P_WINCON(win_id));
79 cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
80 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
81 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
82 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
85 cfg |= S5P_WINCON_DATAPATH_DMA;
88 cfg |= S5P_WINCON_WSWP_ENABLE;
91 cfg |= S5P_WINCON_BURSTLEN_16WORD;
93 /* pixel format is unpacked RGB888 */
94 cfg |= S5P_WINCON_BPPMODE_24BPP_888;
96 writel(cfg, ctrl_base + S5P_WINCON(win_id));
97 udebug("wincon%d = %x\n", win_id, cfg);
99 /* set window position to x=0, y=0*/
100 cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
101 writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
102 udebug("window postion left,top = %x\n", cfg);
104 cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
105 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
106 writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
107 udebug("window postion right,bottom= %x\n", cfg);
109 /* set window size for window0*/
110 cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
111 writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
112 udebug("vidosd_c%d= %x\n", win_id, cfg);
117 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
119 unsigned long start_addr, end_addr;
121 start_addr = (unsigned long)lcd_base_addr;
122 end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
125 writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
126 writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
128 udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
133 static void s5pc_fimd_set_clock(void)
135 unsigned int cfg = 0, div = 0, fimd_ratio = 0, temp = 0,
136 remainder, remainder_div;
137 unsigned long pixel_clock, src_clock, max_clock;
138 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
141 s5pc1xx_clock_init();
143 max_clock = 86 * 1000000;
145 if (pvid->dual_lcd_enabled)
146 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
147 pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
148 pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
150 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
151 pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
152 pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
155 if (get_pll_clk == NULL) {
156 printf("get_pll_clk is null.\n");
159 src_clock = get_pll_clk(MPLL);
161 cfg = readl(ctrl_base + S5P_VIDCON0);
162 cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
163 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
164 cfg |= (S5P_VIDCON0_CLKSEL_SCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
165 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
167 if (pixel_clock > max_clock)
168 pixel_clock = max_clock;
170 /* set source clock to SCLKMPLL. */
171 temp = readl(&clk->src1);
172 writel((temp & ~0xf00000) | 0x600000, &clk->src1);
175 /* set fimd ratio to 3. */
176 temp = readl(&clk->div1);
177 writel((temp & ~0xf00000) | 0x200000, &clk->div1);
181 temp = readl(&clk->div1);
182 fimd_ratio = (temp & 0xf00000) >> 20;
185 div64 = ((u64)src_clock) / (fimd_ratio + 1);
187 /* get quotient and remainder. */
188 remainder = do_div(div64, pixel_clock);
192 remainder_div = remainder / pixel_clock;
194 /* round about one places of decimals. */
195 if (remainder_div >= 5)
198 /* in case of dual lcd mode. */
199 if (pvid->dual_lcd_enabled)
202 cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
203 writel(cfg, ctrl_base + S5P_VIDCON0);
205 udebug("fimd_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
206 fimd_ratio, src_clock / (fimd_ratio + 1), pixel_clock, div);
211 static void s5pc_fimd_lcd_on(unsigned int win_id)
213 unsigned int cfg = 0;
216 cfg = readl(ctrl_base + S5P_VIDCON0);
217 cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
218 writel(cfg, ctrl_base + S5P_VIDCON0);
219 udebug("vidcon0 = %x\n", cfg);
222 static void s5pc_fimd_window_on(unsigned int win_id)
224 unsigned int cfg = 0;
227 cfg = readl(ctrl_base + S5P_WINCON(win_id));
228 cfg |= S5P_WINCON_ENWIN_ENABLE;
229 writel(cfg, ctrl_base + S5P_WINCON(win_id));
230 udebug("wincon%d=%x\n", win_id, cfg);
233 cfg = readl(ctrl_base + S5P_WINSHMAP);
234 cfg |= S5P_WINSHMAP_CH_ENABLE(win_id);
235 writel(cfg, ctrl_base + S5P_WINSHMAP);
238 void s5pc_fimd_lcd_off(unsigned int win_id)
240 unsigned int cfg = 0;
242 cfg = readl(ctrl_base + S5P_VIDCON0);
243 cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
244 writel(cfg, ctrl_base + S5P_VIDCON0);
247 void s5pc_fimd_window_off(unsigned int win_id)
249 unsigned int cfg = 0;
251 cfg = readl(ctrl_base + S5P_WINCON(win_id));
252 cfg &= S5P_WINCON_ENWIN_DISABLE;
253 writel(cfg, ctrl_base + S5P_WINCON(win_id));
256 cfg = readl(ctrl_base + S5P_WINSHMAP);
257 cfg &= ~S5P_WINSHMAP_CH_DISABLE(win_id);
258 writel(cfg, ctrl_base + S5P_WINSHMAP);
261 void s5pc_fimd_lcd_init(vidinfo_t *vid)
263 unsigned int cfg = 0, rgb_mode, win_id = 3;
265 /* store panel info to global variable */
268 /* select register base according to cpu type */
269 if (cpu_is_s5pc110())
270 ctrl_base = S5PC110_LCRB;
272 ctrl_base = S5PC100_LCRB;
274 /* set output to RGB */
275 rgb_mode = MODE_RGB_P;
276 cfg = readl(ctrl_base + S5P_VIDCON0);
277 cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
279 /* clock source is HCLK */
282 cfg |= S5P_VIDCON0_VIDOUT_RGB;
283 writel(cfg, ctrl_base + S5P_VIDCON0);
285 /* set display mode */
286 cfg = readl(ctrl_base + S5P_VIDCON0);
287 cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
288 cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
289 writel(cfg, ctrl_base + S5P_VIDCON0);
294 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
296 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
298 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
300 cfg |= S5P_VIDCON1_IVDEN_INVERT;
302 writel(cfg, ctrl_base + S5P_VIDCON1);
306 cfg |= S5P_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
307 cfg |= S5P_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
308 cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vspw - 1);
309 writel(cfg, ctrl_base + S5P_VIDTCON0);
310 udebug("vidtcon0 = %x\n", cfg);
313 cfg |= S5P_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
314 cfg |= S5P_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
315 cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hspw - 1);
317 writel(cfg, ctrl_base + S5P_VIDTCON1);
318 udebug("vidtcon1 = %x\n", cfg);
322 cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
323 cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
325 writel(cfg, ctrl_base + S5P_VIDTCON2);
326 udebug("vidtcon2 = %x\n", cfg);
329 s5pc_fimd_set_par(win_id);
331 /* set memory address */
332 s5pc_fimd_set_buffer_address(win_id);
334 /* set buffer size */
335 cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
336 writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
337 udebug("vidaddr_pagewidth = %d\n", cfg);
340 s5pc_fimd_set_clock();
342 /* set rgb mode to dual lcd. */
343 if (pvid->dual_lcd_enabled)
344 s5pc_fimd_set_dualrgb(1);
346 s5pc_fimd_set_dualrgb(0);
349 s5pc_fimd_lcd_on(win_id);
352 s5pc_fimd_window_on(win_id);
354 udebug("lcd controller init completed.\n");
359 ulong s5pc_fimd_calc_fbsize(void)
361 return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));