drivers/video/s5p-fimd.c

   1 /*
   2  * S5PC100 and S5PC110 LCD Controller Specific driver.
   3  *
   4  * Author: InKi Dae <inki.dae@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <common.h>
  24 #include <stdarg.h>
  25 #include <linux/types.h>
  26 #include <asm/io.h>
  27 #include <lcd.h>
  28
  29 #include <asm/arch/clk.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/cpu.h>
  32 #include <asm/arch/regs-fb.h>
  33 #include <asm/arch/gpio.h>
  34 #include "s5p-fb.h"
  35
  36 /* LCD CONTROLLER REGISTER BASE */
  37 #define S5PC100_LCRB            0xEE000000
  38 #define S5PC110_LCRB            0xF8000000
  39
  40 #define MPLL 1
  41
  42 static unsigned int ctrl_base;
  43 static unsigned long *lcd_base_addr;
  44 static vidinfo_t *pvid = NULL;
  45
  46 void s5pc_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size)
  47 {
  48         lcd_base_addr = (unsigned long *)screen_base;
  49
  50         udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
  51
  52         return;
  53 }
  54
  55 static void s5pc_fimd_set_dualrgb(unsigned int enabled)
  56 {
  57         unsigned int cfg = 0;
  58
  59         if (enabled) {
  60                 cfg = S5P_DUALRGB_BYPASS_DUAL | S5P_DUALRGB_LINESPLIT |
  61                         S5P_DUALRGB_VDEN_EN_ENABLE;
  62
  63                 /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
  64                 cfg |= S5P_DUALRGB_SUB_CNT(pvid->vl_col/2) | S5P_DUALRGB_MAIN_CNT(0);
  65         } else
  66                 cfg = 0;
  67
  68         writel(cfg, ctrl_base + S5P_DUALRGB);
  69 }
  70
  71 static void s5pc_fimd_set_par(unsigned int win_id)
  72 {
  73         unsigned int cfg = 0;
  74
  75         /* set window control */
  76         cfg = readl(ctrl_base + S5P_WINCON(win_id));
  77
  78         cfg &= ~(S5P_WINCON_BITSWP_ENABLE | S5P_WINCON_BYTESWP_ENABLE | \
  79                 S5P_WINCON_HAWSWP_ENABLE | S5P_WINCON_WSWP_ENABLE | \
  80                 S5P_WINCON_BURSTLEN_MASK | S5P_WINCON_BPPMODE_MASK | \
  81                 S5P_WINCON_INRGB_MASK | S5P_WINCON_DATAPATH_MASK);
  82
  83         /* DATAPATH is DMA */
  84         cfg |= S5P_WINCON_DATAPATH_DMA;
  85
  86         /* bpp is 32 */
  87         cfg |= S5P_WINCON_WSWP_ENABLE;
  88
  89         /* dma burst is 16 */
  90         cfg |= S5P_WINCON_BURSTLEN_16WORD;
  91
  92         /* pixel format is unpacked RGB888 */
  93         cfg |= S5P_WINCON_BPPMODE_24BPP_888;
  94
  95         writel(cfg, ctrl_base + S5P_WINCON(win_id));
  96         udebug("wincon%d = %x\n", win_id, cfg);
  97
  98         /* set window position to x=0, y=0*/
  99         cfg = S5P_VIDOSD_LEFT_X(0) | S5P_VIDOSD_TOP_Y(0);
 100         writel(cfg, ctrl_base + S5P_VIDOSD_A(win_id));
 101         udebug("window postion left,top = %x\n", cfg);
 102
 103         cfg = S5P_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
 104                 S5P_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
 105         writel(cfg, ctrl_base + S5P_VIDOSD_B(win_id));
 106         udebug("window postion right,bottom= %x\n", cfg);
 107
 108         /* set window size for window0*/
 109         cfg = S5P_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
 110         writel(cfg, ctrl_base + S5P_VIDOSD_C(win_id));
 111         udebug("vidosd_c%d= %x\n", win_id, cfg);
 112
 113         return;
 114 }
 115
 116 static void s5pc_fimd_set_buffer_address(unsigned int win_id)
 117 {
 118         unsigned long start_addr, end_addr;
 119
 120         start_addr = (unsigned long)lcd_base_addr;
 121         end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
 122                 * pvid->vl_row);
 123
 124         writel(start_addr, ctrl_base + S5P_VIDADDR_START0(win_id));
 125         writel(end_addr, ctrl_base + S5P_VIDADDR_END0(win_id));
 126
 127         udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
 128
 129         return;
 130 }
 131
 132 static void s5pc_fimd_set_clock(void)
 133 {
 134         unsigned int cfg = 0, div = 0, fimd_ratio = 0, temp = 0;
 135         unsigned long pixel_clock, src_clock, max_clock;
 136         struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
 137
 138         s5pc1xx_clock_init();
 139
 140         max_clock = 86 * 1000000;
 141
 142         if (pvid->dual_lcd_enabled)
 143                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 144                         pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
 145                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 146         else
 147                 pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
 148                         pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
 149                             pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
 150
 151
 152         if (get_pll_clk == NULL) {
 153                 printf("get_pll_clk is null.\n");
 154                 return;
 155         }
 156         src_clock = get_pll_clk(MPLL);
 157
 158         cfg = readl(ctrl_base + S5P_VIDCON0);
 159         cfg &= ~(S5P_VIDCON0_CLKSEL_MASK | S5P_VIDCON0_CLKVALUP_MASK | \
 160                 S5P_VIDCON0_VCLKEN_MASK | S5P_VIDCON0_CLKDIR_MASK);
 161         cfg |= (S5P_VIDCON0_CLKSEL_SCLK | S5P_VIDCON0_CLKVALUP_ALWAYS | \
 162                 S5P_VIDCON0_VCLKEN_NORMAL | S5P_VIDCON0_CLKDIR_DIVIDED);
 163
 164         if (pixel_clock > max_clock)
 165                 pixel_clock = max_clock;
 166
 167         /* set source clock to SCLKMPLL. */
 168         temp = readl(&clk->src1);
 169         writel((temp & ~0xf00000) | 0x600000, &clk->src1);
 170         temp = 0;
 171
 172         /* set fimd ratio to 3. */
 173         temp = readl(&clk->div1);
 174         writel((temp & ~0xf00000) | 0x300000, &clk->div1);
 175         temp = 0;
 176
 177         /* get mpll ratio */
 178         temp = readl(&clk->div1);
 179         fimd_ratio = (temp & 0xf00000) >> 20;
 180         temp = 0;
 181
 182         /* It can get source clock speed as (mpll / fimd_ratio + 1) */
 183         div = (unsigned int)((src_clock / (fimd_ratio + 1)) / pixel_clock);
 184
 185         /* in case of dual lcd mode. */
 186         if (pvid->dual_lcd_enabled)
 187                 div--;
 188
 189         cfg |= S5P_VIDCON0_CLKVAL_F(div - 1);
 190         writel(cfg, ctrl_base + S5P_VIDCON0);
 191
 192         udebug("fimd_ratio = %d, src_clock = %d, pixel_clock = %d, div = %d\n",
 193                 fimd_ratio, src_clock, pixel_clock, div);
 194
 195         return;
 196 }
 197
 198 static void s5pc_fimd_lcd_on(unsigned int win_id)
 199 {
 200         unsigned int cfg = 0;
 201
 202         /* display on */
 203         cfg = readl(ctrl_base + S5P_VIDCON0);
 204         cfg |= (S5P_VIDCON0_ENVID_ENABLE | S5P_VIDCON0_ENVID_F_ENABLE);
 205         writel(cfg, ctrl_base + S5P_VIDCON0);
 206         udebug("vidcon0 = %x\n", cfg);
 207 }
 208
 209 static void s5pc_fimd_window_on(unsigned int win_id)
 210 {
 211         unsigned int cfg = 0;
 212
 213         /* enable window */
 214         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 215         cfg |= S5P_WINCON_ENWIN_ENABLE;
 216         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 217         udebug("wincon%d=%x\n", win_id, cfg);
 218
 219         /* evt1 */
 220         cfg = readl(ctrl_base + S5P_WINSHMAP);
 221         cfg |= S5P_WINSHMAP_CH_ENABLE(win_id);
 222         writel(cfg, ctrl_base + S5P_WINSHMAP);
 223 }
 224
 225 void s5pc_fimd_lcd_off(unsigned int win_id)
 226 {
 227         unsigned int cfg = 0;
 228
 229         cfg = readl(ctrl_base + S5P_VIDCON0);
 230         cfg &= (S5P_VIDCON0_ENVID_DISABLE | S5P_VIDCON0_ENVID_F_DISABLE);
 231         writel(cfg, ctrl_base + S5P_VIDCON0);
 232 }
 233
 234 void s5pc_fimd_window_off(unsigned int win_id)
 235 {
 236         unsigned int cfg = 0;
 237
 238         cfg = readl(ctrl_base + S5P_WINCON(win_id));
 239         cfg &= S5P_WINCON_ENWIN_DISABLE;
 240         writel(cfg, ctrl_base + S5P_WINCON(win_id));
 241
 242         /* evt1 */
 243         cfg = readl(ctrl_base + S5P_WINSHMAP);
 244         cfg &= ~S5P_WINSHMAP_CH_DISABLE(win_id);
 245         writel(cfg, ctrl_base + S5P_WINSHMAP);
 246 }
 247
 248 void s5pc_fimd_lcd_init(vidinfo_t *vid)
 249 {
 250         unsigned int cfg = 0, rgb_mode, win_id = 3;
 251
 252         /* store panel info to global variable */
 253         pvid = vid;
 254
 255         /* select register base according to cpu type */
 256         if (cpu_is_s5pc110())
 257                 ctrl_base = S5PC110_LCRB;
 258         else
 259                 ctrl_base = S5PC100_LCRB;
 260
 261         /* set output to RGB */
 262         rgb_mode = MODE_RGB_P;
 263         cfg = readl(ctrl_base + S5P_VIDCON0);
 264         cfg &= ~S5P_VIDCON0_VIDOUT_MASK;
 265
 266         /* clock source is HCLK */
 267         cfg |= 0 << 2;
 268
 269         cfg |= S5P_VIDCON0_VIDOUT_RGB;
 270         writel(cfg, ctrl_base + S5P_VIDCON0);
 271
 272         /* set display mode */
 273         cfg = readl(ctrl_base + S5P_VIDCON0);
 274         cfg &= ~S5P_VIDCON0_PNRMODE_MASK;
 275         cfg |= (rgb_mode << S5P_VIDCON0_PNRMODE_SHIFT);
 276         writel(cfg, ctrl_base + S5P_VIDCON0);
 277
 278         /* set polarity */
 279         cfg = 0;
 280         if (!pvid->vl_clkp)
 281                 cfg |= S5P_VIDCON1_IVCLK_RISING_EDGE;
 282         if (!pvid->vl_hsp)
 283                 cfg |= S5P_VIDCON1_IHSYNC_INVERT;
 284         if (!pvid->vl_vsp)
 285                 cfg |= S5P_VIDCON1_IVSYNC_INVERT;
 286         if (!pvid->vl_dp)
 287                 cfg |= S5P_VIDCON1_IVDEN_INVERT;
 288
 289         writel(cfg, ctrl_base + S5P_VIDCON1);
 290
 291         /* set timing */
 292         cfg = 0;
 293         cfg |= S5P_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
 294         cfg |= S5P_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
 295         cfg |= S5P_VIDTCON0_VSPW(pvid->vl_vspw - 1);
 296         writel(cfg, ctrl_base + S5P_VIDTCON0);
 297         udebug("vidtcon0 = %x\n", cfg);
 298
 299         cfg = 0;
 300         cfg |= S5P_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
 301         cfg |= S5P_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
 302         cfg |= S5P_VIDTCON1_HSPW(pvid->vl_hspw - 1);
 303
 304         writel(cfg, ctrl_base + S5P_VIDTCON1);
 305         udebug("vidtcon1 = %x\n", cfg);
 306
 307         /* set lcd size */
 308         cfg = 0;
 309         cfg |= S5P_VIDTCON2_HOZVAL(pvid->vl_col - 1);
 310         cfg |= S5P_VIDTCON2_LINEVAL(pvid->vl_row - 1);
 311
 312         writel(cfg, ctrl_base + S5P_VIDTCON2);
 313         udebug("vidtcon2 = %x\n", cfg);
 314
 315         /* set par */
 316         s5pc_fimd_set_par(win_id);
 317
 318         /* set memory address */
 319         s5pc_fimd_set_buffer_address(win_id);
 320
 321         /* set buffer size */
 322         cfg = S5P_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
 323         writel(cfg, ctrl_base + S5P_VIDADDR_SIZE(win_id));
 324         udebug("vidaddr_pagewidth = %d\n", cfg);
 325
 326         /* set clock */
 327         s5pc_fimd_set_clock();
 328
 329         /* set rgb mode to dual lcd. */
 330         if (pvid->dual_lcd_enabled)
 331                 s5pc_fimd_set_dualrgb(1);
 332         else
 333                 s5pc_fimd_set_dualrgb(0);
 334
 335         /* display on */
 336         s5pc_fimd_lcd_on(win_id);
 337
 338         /* window on */
 339         s5pc_fimd_window_on(win_id);
 340
 341         udebug("lcd controller init completed.\n");
 342
 343         return;
 344 }
 345
 346 ulong s5pc_fimd_calc_fbsize(void)
 347 {
 348         return (pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8));
 349 }