1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Eric Gao <eric.gao@rock-chips.com>
17 #include <dm/uclass-internal.h>
18 #include <linux/kernel.h>
19 #include <asm/arch-rockchip/clock.h>
20 #include <asm/arch-rockchip/cru.h>
21 #include <asm/arch-rockchip/grf_rk3399.h>
22 #include <asm/arch-rockchip/rockchip_mipi_dsi.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 int rk_mipi_read_timing(struct udevice *dev,
27 struct display_timing *timing)
31 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
33 debug("%s: Failed to decode display timing (ret=%d)\n",
42 * Register write function used only for mipi dsi controller.
44 * @regs: mipi controller address
45 * @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
46 * use define in rk_mipi.h directly for this parameter
47 * @val: value that will be write to specified bits of register
49 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
53 u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
54 u32 bits = (reg >> BITS_SHIFT) & 0xff;
55 uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
57 /* Mask for specifiled bits,the corresponding bits will be clear */
58 mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
60 /* Make sure val in the available range */
61 val &= ~(0xffffffff << bits);
63 /* Get register's original val */
66 /* Clear specified bits */
69 /* Fill specified bits */
75 int rk_mipi_dsi_enable(struct udevice *dev,
76 const struct display_timing *timing)
78 ofnode node, timing_node;
80 struct rk_mipi_priv *priv = dev_get_priv(dev);
81 uintptr_t regs = priv->regs;
82 u32 txbyte_clk = priv->txbyte_clk;
83 u32 txesc_clk = priv->txesc_clk;
85 txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
87 /* Set Display timing parameter */
88 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
89 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
90 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
91 + timing->hback_porch.typ + timing->hactive.typ
92 + timing->hfront_porch.typ));
93 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
94 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
95 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
96 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
98 /* Set Signal Polarity */
99 val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
100 rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
102 val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
103 rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
105 val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
106 rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val);
108 val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
109 rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
112 rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
114 /* Set video mode transmission type as burst mode */
115 rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
117 /* Set pix num in a video package */
118 rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
120 /* Set dpi color coding depth 24 bit */
121 timing_node = ofnode_find_subnode(dev->node, "display-timings");
122 node = ofnode_first_subnode(timing_node);
124 val = ofnode_read_u32_default(node, "bits-per-pixel", -1);
127 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
130 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
133 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
136 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
138 /* Enable low power mode */
139 rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
140 rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
141 rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
142 rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
143 rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
144 rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
146 /* Division for timeout counter clk */
147 rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
149 /* Tx esc clk division from txbyte clk */
150 rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
152 /* Timeout count for hs<->lp transation between Line period */
153 rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
155 /* Phy State transfer timing */
156 rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
157 rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
158 rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
159 rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
160 rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
163 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
168 /* rk mipi dphy write function. It is used to write test data to dphy */
169 static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
170 unsigned char *test_data, unsigned char size)
174 /* Write Test code */
175 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
176 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
177 rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
178 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
179 rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
181 /* Write Test data */
182 for (i = 0; i < size; i++) {
183 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
184 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
185 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
190 * Mipi dphy config function. Calculate the suitable prediv, feedback div,
191 * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
192 * and then enable phy.
194 int rk_mipi_phy_enable(struct udevice *dev)
197 struct rk_mipi_priv *priv = dev_get_priv(dev);
198 uintptr_t regs = priv->regs;
202 u32 max_prediv, min_prediv;
203 u64 ddr_clk = priv->phy_clk;
204 u32 refclk = priv->ref_clk;
206 unsigned char test_data[2] = {0};
208 int freq_rang[][2] = {
209 {90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
210 {140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
211 {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
212 {270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
213 {400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
214 {600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
215 {800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
216 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
217 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
218 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
222 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
223 rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
224 rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
227 rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
229 /* config cp and lfp */
230 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
231 rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
234 rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
236 test_data[0] = 0x80 | 0x40;
237 rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
239 /* select the suitable value for fsfreqrang reg */
240 for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
241 if (ddr_clk / (MHz) <= freq_rang[i][0])
244 if (i == ARRAY_SIZE(freq_rang)) {
245 debug("%s: Dphy freq out of range!\n", __func__);
248 test_data[0] = freq_rang[i][1] << 1;
249 rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
252 * Calculate the best ddrclk and it's corresponding div value. If the
253 * given pixelclock is great than 250M, ddrclk will be fix 1500M.
255 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
258 max_prediv = (refclk / (5 * MHz));
259 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
261 debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
264 if (max_prediv < min_prediv) {
265 debug("%s: Invalid refclk value\n", __func__);
269 /* Calculate the best refclk and feedback division value for dphy pll */
270 for (i = min_prediv; i < max_prediv; i++) {
271 if ((ddr_clk * i % refclk < remain) &&
272 (ddr_clk * i / refclk) < max_fbdiv) {
274 remain = ddr_clk * i % refclk;
277 fbdiv = ddr_clk * prediv / refclk;
278 ddr_clk = refclk * fbdiv / prediv;
279 priv->phy_clk = ddr_clk;
281 debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
282 __func__, refclk, prediv, fbdiv, ddr_clk);
284 /* config prediv and feedback reg */
285 test_data[0] = prediv - 1;
286 rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
287 test_data[0] = (fbdiv - 1) & 0x1f;
288 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
289 test_data[0] = (fbdiv - 1) >> 5 | 0x80;
290 rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
292 rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
296 rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
299 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
302 rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
305 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
307 test_data[0] = 0x80 | 0x7;
308 rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
310 test_data[0] = 0x80 | 15;
311 rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
313 test_data[0] = 0x80 | 85;
314 rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
316 test_data[0] = 0x40 | 10;
317 rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
320 /* enter into stop mode */
321 rk_mipi_dsi_write(regs, N_LANES, 0x03);
322 rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
323 rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
324 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
325 rk_mipi_dsi_write(regs, PHY_RSTZ, 1);