drivers/video/rockchip/rk_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Rockchip Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <display.h>
   8 #include <dm.h>
   9 #include <edid.h>
  10 #include <log.h>
  11 #include <panel.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/grf_rk3288.h>
  18 #include <asm/arch-rockchip/hardware.h>
  19 #include <asm/arch-rockchip/lvds_rk3288.h>
  20 #include <dt-bindings/clock/rk3288-cru.h>
  21 #include <dt-bindings/video/rk3288.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /**
  26  * struct rk_lvds_priv - private rockchip lvds display driver info
  27  *
  28  * @reg: LVDS register address
  29  * @grf: GRF register
  30  * @panel: Panel device that is used in driver
  31  *
  32  * @output: Output mode, decided single or double channel,
  33  *              LVDS or LVTLL
  34  * @format: Data format that RGB data will packing as
  35  */
  36 struct rk_lvds_priv {
  37         void __iomem *regs;
  38         struct rk3288_grf *grf;
  39         struct udevice *panel;
  40
  41         int output;
  42         int format;
  43 };
  44
  45 static inline void lvds_writel(struct rk_lvds_priv *lvds, u32 offset, u32 val)
  46 {
  47         writel(val, lvds->regs + offset);
  48
  49         writel(val, lvds->regs + offset + 0x100);
  50 }
  51
  52 int rk_lvds_enable(struct udevice *dev, int panel_bpp,
  53                    const struct display_timing *edid)
  54 {
  55         struct rk_lvds_priv *priv = dev_get_priv(dev);
  56         struct display_plat *uc_plat = dev_get_uclass_plat(dev);
  57         int ret = 0;
  58         unsigned int val = 0;
  59
  60         ret = panel_enable_backlight(priv->panel);
  61         if (ret) {
  62                 debug("%s: backlight error: %d\n", __func__, ret);
  63                 return ret;
  64         }
  65
  66         /* Select the video source */
  67         if (uc_plat->source_id)
  68                 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT |
  69                     (RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16);
  70         else
  71                 val = RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16;
  72         rk_setreg(&priv->grf->soc_con6, val);
  73
  74         /* Select data transfer format */
  75         val = priv->format;
  76         if (priv->output == LVDS_OUTPUT_DUAL)
  77                 val |= LVDS_DUAL | LVDS_CH0_EN | LVDS_CH1_EN;
  78         else if (priv->output == LVDS_OUTPUT_SINGLE)
  79                 val |= LVDS_CH0_EN;
  80         else if (priv->output == LVDS_OUTPUT_RGB)
  81                 val |= LVDS_TTL_EN | LVDS_CH0_EN | LVDS_CH1_EN;
  82         val |= (0xffff << 16);
  83         rk_setreg(&priv->grf->soc_con7, val);
  84
  85         /* Enable LVDS PHY */
  86         if (priv->output == LVDS_OUTPUT_RGB) {
  87                 lvds_writel(priv, RK3288_LVDS_CH0_REG0,
  88                             RK3288_LVDS_CH0_REG0_TTL_EN |
  89                             RK3288_LVDS_CH0_REG0_LANECK_EN |
  90                             RK3288_LVDS_CH0_REG0_LANE4_EN |
  91                             RK3288_LVDS_CH0_REG0_LANE3_EN |
  92                             RK3288_LVDS_CH0_REG0_LANE2_EN |
  93                             RK3288_LVDS_CH0_REG0_LANE1_EN |
  94                             RK3288_LVDS_CH0_REG0_LANE0_EN);
  95                 lvds_writel(priv, RK3288_LVDS_CH0_REG2,
  96                             RK3288_LVDS_PLL_FBDIV_REG2(0x46));
  97
  98                 lvds_writel(priv, RK3288_LVDS_CH0_REG3,
  99                             RK3288_LVDS_PLL_FBDIV_REG3(0x46));
 100                 lvds_writel(priv, RK3288_LVDS_CH0_REG4,
 101                             RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE |
 102                             RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE |
 103                             RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE |
 104                             RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE |
 105                             RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE |
 106                             RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE);
 107                 lvds_writel(priv, RK3288_LVDS_CH0_REG5,
 108                             RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA |
 109                             RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA |
 110                             RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA |
 111                             RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA |
 112                             RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA |
 113                             RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA);
 114                 lvds_writel(priv, RK3288_LVDS_CH0_REGD,
 115                             RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
 116                 lvds_writel(priv, RK3288_LVDS_CH0_REG20,
 117                             RK3288_LVDS_CH0_REG20_LSB);
 118         } else {
 119                 lvds_writel(priv, RK3288_LVDS_CH0_REG0,
 120                             RK3288_LVDS_CH0_REG0_LVDS_EN |
 121                             RK3288_LVDS_CH0_REG0_LANECK_EN |
 122                             RK3288_LVDS_CH0_REG0_LANE4_EN |
 123                             RK3288_LVDS_CH0_REG0_LANE3_EN |
 124                             RK3288_LVDS_CH0_REG0_LANE2_EN |
 125                             RK3288_LVDS_CH0_REG0_LANE1_EN |
 126                             RK3288_LVDS_CH0_REG0_LANE0_EN);
 127                 lvds_writel(priv, RK3288_LVDS_CH0_REG1,
 128                             RK3288_LVDS_CH0_REG1_LANECK_BIAS |
 129                             RK3288_LVDS_CH0_REG1_LANE4_BIAS |
 130                             RK3288_LVDS_CH0_REG1_LANE3_BIAS |
 131                             RK3288_LVDS_CH0_REG1_LANE2_BIAS |
 132                             RK3288_LVDS_CH0_REG1_LANE1_BIAS |
 133                             RK3288_LVDS_CH0_REG1_LANE0_BIAS);
 134                 lvds_writel(priv, RK3288_LVDS_CH0_REG2,
 135                             RK3288_LVDS_CH0_REG2_RESERVE_ON |
 136                             RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE |
 137                             RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE |
 138                             RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE |
 139                             RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE |
 140                             RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE |
 141                             RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE |
 142                             RK3288_LVDS_PLL_FBDIV_REG2(0x46));
 143                 lvds_writel(priv, RK3288_LVDS_CH0_REG3,
 144                             RK3288_LVDS_PLL_FBDIV_REG3(0x46));
 145                 lvds_writel(priv, RK3288_LVDS_CH0_REG4, 0x00);
 146                 lvds_writel(priv, RK3288_LVDS_CH0_REG5, 0x00);
 147                 lvds_writel(priv, RK3288_LVDS_CH0_REGD,
 148                             RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
 149                 lvds_writel(priv, RK3288_LVDS_CH0_REG20,
 150                             RK3288_LVDS_CH0_REG20_LSB);
 151         }
 152
 153         /* Power on */
 154         writel(RK3288_LVDS_CFG_REGC_PLL_ENABLE,
 155                priv->regs + RK3288_LVDS_CFG_REGC);
 156
 157         writel(RK3288_LVDS_CFG_REG21_TX_ENABLE,
 158                priv->regs + RK3288_LVDS_CFG_REG21);
 159
 160         return 0;
 161 }
 162
 163 int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
 164 {
 165         if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
 166                 debug("%s: Failed to decode display timing\n", __func__);
 167                 return -EINVAL;
 168         }
 169
 170         return 0;
 171 }
 172
 173 static int rk_lvds_of_to_plat(struct udevice *dev)
 174 {
 175         struct rk_lvds_priv *priv = dev_get_priv(dev);
 176         int ret;
 177         priv->regs = dev_read_addr_ptr(dev);
 178         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 179
 180         ret = dev_read_s32_default(dev, "rockchip,output", -1);
 181         if (ret != -1) {
 182                 priv->output = ret;
 183                 debug("LVDS output : %d\n", ret);
 184         } else {
 185                 /* default set it as output rgb */
 186                 priv->output = LVDS_OUTPUT_RGB;
 187         }
 188
 189         ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1);
 190         if (ret != -1) {
 191                 priv->format = ret;
 192                 debug("LVDS data-mapping : %d\n", ret);
 193         } else {
 194                 /* default set it as format jeida */
 195                 priv->format = LVDS_FORMAT_JEIDA;
 196         }
 197
 198         ret = dev_read_s32_default(dev, "rockchip,data-width", -1);
 199         if (ret != -1) {
 200                 debug("LVDS data-width : %d\n", ret);
 201                 if (ret == 24) {
 202                         priv->format |= LVDS_24BIT;
 203                 } else if (ret == 18) {
 204                         priv->format |= LVDS_18BIT;
 205                 } else {
 206                         debug("rockchip-lvds unsupport data-width[%d]\n", ret);
 207                         ret = -EINVAL;
 208                         return ret;
 209                 }
 210         } else {
 211                 priv->format |= LVDS_24BIT;
 212         }
 213
 214         return 0;
 215 }
 216
 217 int rk_lvds_probe(struct udevice *dev)
 218 {
 219         struct rk_lvds_priv *priv = dev_get_priv(dev);
 220         int ret;
 221
 222         ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
 223                                            &priv->panel);
 224         if (ret) {
 225                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
 226                       dev->name, ret);
 227                 return ret;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static const struct dm_display_ops lvds_rockchip_ops = {
 234         .read_timing = rk_lvds_read_timing,
 235         .enable = rk_lvds_enable,
 236 };
 237
 238 static const struct udevice_id rockchip_lvds_ids[] = {
 239         {.compatible = "rockchip,rk3288-lvds"},
 240         {}
 241 };
 242
 243 U_BOOT_DRIVER(lvds_rockchip) = {
 244         .name   = "lvds_rockchip",
 245         .id     = UCLASS_DISPLAY,
 246         .of_match = rockchip_lvds_ids,
 247         .ops    = &lvds_rockchip_ops,
 248         .of_to_plat     = rk_lvds_of_to_plat,
 249         .probe  = rk_lvds_probe,
 250         .priv_auto      = sizeof(struct rk_lvds_priv),
 251 };