1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
19 #include <asm/arch-rockchip/clock.h>
20 #include <asm/arch-rockchip/edp_rk3288.h>
21 #include <asm/arch-rockchip/grf_rk3288.h>
22 #include <asm/arch-rockchip/hardware.h>
23 #include <dt-bindings/clock/rk3288-cru.h>
24 #include <linux/delay.h>
28 #define DP_LINK_STATUS_SIZE 6
30 static const char * const voltage_names[] = {
31 "0.4V", "0.6V", "0.8V", "1.2V"
33 static const char * const pre_emph_names[] = {
34 "0dB", "3.5dB", "6dB", "9.5dB"
37 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
38 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
41 struct rk3288_edp *regs;
42 struct rk3288_grf *grf;
43 struct udevice *panel;
44 struct link_train link_train;
48 static void rk_edp_init_refclk(struct rk3288_edp *regs)
50 writel(SEL_24M, ®s->analog_ctl_2);
51 writel(REF_CLK_24M, ®s->pll_reg_1);
53 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
54 V2L_CUR_SEL_1MA, ®s->pll_reg_2);
56 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
57 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
60 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
61 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
64 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg);
66 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
67 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
70 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
73 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
76 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
80 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
82 /* Set interrupt pin assertion polarity as high */
83 writel(INT_POL, ®s->int_ctl);
85 /* Clear pending registers */
86 writel(0xff, ®s->common_int_sta_1);
87 writel(0x4f, ®s->common_int_sta_2);
88 writel(0xff, ®s->common_int_sta_3);
89 writel(0x27, ®s->common_int_sta_4);
90 writel(0x7f, ®s->dp_int_sta);
92 /* 0:mask,1: unmask */
93 writel(0x00, ®s->common_int_mask_1);
94 writel(0x00, ®s->common_int_mask_2);
95 writel(0x00, ®s->common_int_mask_3);
96 writel(0x00, ®s->common_int_mask_4);
97 writel(0x00, ®s->int_sta_mask);
100 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
102 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
105 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
109 val = readl(®s->dp_debug_ctl);
111 return val & PLL_LOCK;
114 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
118 writel(0x00, ®s->dp_pd);
119 writel(PLL_LOCK_CHG, ®s->common_int_sta_1);
121 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
123 start = get_timer(0);
124 while (!rk_edp_get_pll_locked(regs)) {
125 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
126 printf("%s: PLL is not locked\n", __func__);
131 /* Enable Serdes FIFO function and Link symbol clock domain module */
132 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N |
133 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
139 static void rk_edp_init_aux(struct rk3288_edp *regs)
141 /* Clear inerrupts related to AUX channel */
142 writel(AUX_FUNC_EN_N, ®s->dp_int_sta);
144 /* Disable AUX channel module */
145 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
147 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
148 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl);
150 /* Enable AUX channel module */
151 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
154 static int rk_edp_aux_enable(struct rk3288_edp *regs)
158 setbits_le32(®s->aux_ch_ctl_2, AUX_EN);
159 start = get_timer(0);
161 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN))
163 } while (get_timer(start) < 20);
168 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
172 start = get_timer(0);
173 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) {
174 if (get_timer(start) > 10)
178 writel(RPLY_RECEIV, ®s->dp_int_sta);
183 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
187 /* Enable AUX CH operation */
188 ret = rk_edp_aux_enable(regs);
190 debug("AUX CH enable timeout!\n");
194 /* Is AUX CH command reply received? */
195 if (rk_edp_is_aux_reply(regs)) {
196 debug("AUX CH command reply failed!\n");
200 /* Clear interrupt source for AUX CH access error */
201 val = readl(®s->dp_int_sta);
203 writel(AUX_ERR, ®s->dp_int_sta);
207 /* Check AUX CH error access status */
208 val = readl(®s->dp_int_sta);
209 if (val & AUX_STATUS_MASK) {
210 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
217 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
218 unsigned int val_addr, u8 *in_data,
220 enum dpcd_request request)
229 len = min(length, 16U);
230 for (try_times = 0; try_times < 10; try_times++) {
232 /* Clear AUX CH data buffer */
233 writel(BUF_CLR, ®s->buf_data_ctl);
235 /* Select DPCD device address */
236 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0);
237 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8);
238 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16);
241 * Set DisplayPort transaction and read 1 byte
242 * If bit 3 is 1, DisplayPort transaction.
243 * If Bit 3 is 0, I2C transaction.
245 if (request == DPCD_WRITE) {
246 val = AUX_LENGTH(len) |
247 AUX_TX_COMM_DP_TRANSACTION |
249 for (i = 0; i < len; i++)
250 writel(*data++, ®s->buf_data[i]);
252 val = AUX_LENGTH(len) |
253 AUX_TX_COMM_DP_TRANSACTION |
256 writel(val, ®s->aux_ch_ctl_1);
258 /* Start AUX transaction */
259 ret = rk_edp_start_aux_transaction(regs);
263 printf("read dpcd Aux Transaction fail!\n");
269 if (request == DPCD_READ) {
270 for (i = 0; i < len; i++)
271 *data++ = (u8)readl(®s->buf_data[i]);
282 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
285 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
288 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
291 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
295 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
300 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
301 if (edp->link_train.revision < 0x11)
304 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
308 value &= ~DP_SET_POWER_MASK;
309 value |= DP_SET_POWER_D0;
311 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
316 * According to the DP 1.1 specification, a "Sink Device must exit the
317 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
318 * Control Field" (register 0x600).
325 static int rk_edp_link_configure(struct rk_edp_priv *edp)
329 values[0] = edp->link_train.link_rate;
330 values[1] = edp->link_train.lane_count;
332 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
336 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
337 const u8 *training_values)
341 for (i = 0; i < edp->link_train.lane_count; i++)
342 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
345 static u8 edp_link_status(const u8 *link_status, int r)
347 return link_status[r - DPCD_LANE0_1_STATUS];
350 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
353 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
354 DP_LINK_STATUS_SIZE);
357 static u8 edp_get_lane_status(const u8 *link_status, int lane)
359 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
360 int s = (lane & 1) * 4;
361 u8 l = edp_link_status(link_status, i);
363 return (l >> s) & 0xf;
366 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
371 for (lane = 0; lane < lane_count; lane++) {
372 lane_status = edp_get_lane_status(link_status, lane);
373 if ((lane_status & DP_LANE_CR_DONE) == 0)
380 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
386 lane_align = edp_link_status(link_status,
387 DPCD_LANE_ALIGN_STATUS_UPDATED);
388 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
390 for (lane = 0; lane < lane_count; lane++) {
391 lane_status = edp_get_lane_status(link_status, lane);
392 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
399 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
401 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
402 int s = ((lane & 1) ?
403 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
404 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
405 u8 l = edp_link_status(link_status, i);
407 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
410 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
413 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
414 int s = ((lane & 1) ?
415 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
416 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
417 u8 l = edp_link_status(link_status, i);
419 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
422 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
429 for (lane = 0; lane < lane_count; lane++) {
432 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
433 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
436 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
438 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
439 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
447 if (v >= DP_VOLTAGE_MAX)
448 v |= DP_TRAIN_MAX_SWING_REACHED;
450 if (p >= DP_PRE_EMPHASIS_MAX)
451 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
453 debug("using signal parameters: voltage %s pre_emph %s\n",
454 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
455 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
456 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
457 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
459 for (lane = 0; lane < 4; lane++)
460 train_set[lane] = v | p;
463 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
465 struct rk3288_edp *regs = edp->regs;
467 uint voltage, tries = 0;
468 u8 status[DP_LINK_STATUS_SIZE];
472 value = DP_TRAINING_PATTERN_1;
473 writel(value, ®s->dp_training_ptn_set);
474 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
477 memset(edp->train_set, '\0', sizeof(edp->train_set));
479 /* clock recovery loop */
485 rk_edp_set_link_training(edp, edp->train_set);
486 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
488 edp->link_train.lane_count);
494 ret = rk_edp_dpcd_read_link_status(edp, status);
496 printf("displayport link status failed, ret=%d\n", ret);
500 clock_recovery = rk_edp_clock_recovery(status,
501 edp->link_train.lane_count);
505 for (i = 0; i < edp->link_train.lane_count; i++) {
506 if ((edp->train_set[i] &
507 DP_TRAIN_MAX_SWING_REACHED) == 0)
510 if (i == edp->link_train.lane_count) {
511 printf("clock recovery reached max voltage\n");
515 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
517 if (++tries == MAX_CR_LOOP) {
518 printf("clock recovery tried 5 times\n");
525 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
527 /* Compute new train_set as requested by sink */
528 edp_get_adjust_train(status, edp->link_train.lane_count,
531 if (clock_recovery) {
532 printf("clock recovery failed: %d\n", clock_recovery);
533 return clock_recovery;
535 debug("clock recovery at voltage %d pre-emphasis %d\n",
536 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
537 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
538 DP_TRAIN_PRE_EMPHASIS_SHIFT);
543 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
545 struct rk3288_edp *regs = edp->regs;
549 u8 status[DP_LINK_STATUS_SIZE];
552 value = DP_TRAINING_PATTERN_2;
553 writel(value, ®s->dp_training_ptn_set);
554 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
558 /* channel equalization loop */
560 for (tries = 0; tries < 5; tries++) {
561 rk_edp_set_link_training(edp, edp->train_set);
564 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
565 printf("displayport link status failed\n");
569 channel_eq = rk_edp_channel_eq(status,
570 edp->link_train.lane_count);
573 edp_get_adjust_train(status, edp->link_train.lane_count,
578 printf("channel eq failed, ret=%d\n", channel_eq);
582 debug("channel eq at voltage %d pre-emphasis %d\n",
583 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
584 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
585 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
590 static int rk_edp_init_training(struct rk_edp_priv *edp)
595 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
600 edp->link_train.revision = values[0];
601 edp->link_train.link_rate = values[1];
602 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
604 debug("max link rate:%d.%dGps max number of lanes:%d\n",
605 edp->link_train.link_rate * 27 / 100,
606 edp->link_train.link_rate * 27 % 100,
607 edp->link_train.lane_count);
609 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
610 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
611 debug("Rx Max Link Rate is abnormal :%x\n",
612 edp->link_train.link_rate);
616 if (edp->link_train.lane_count == 0) {
617 debug("Rx Max Lane count is abnormal :%x\n",
618 edp->link_train.lane_count);
622 ret = rk_edp_link_power_up(edp);
626 return rk_edp_link_configure(edp);
629 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
635 /* Set link rate and count as you want to establish */
636 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
637 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
639 ret = rk_edp_link_train_cr(edp);
642 ret = rk_edp_link_train_ce(edp);
646 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
647 start = get_timer(0);
649 val = readl(&edp->regs->dp_hw_link_training);
650 if (!(val & HW_LT_EN))
652 } while (get_timer(start) < 10);
654 if (val & HW_LT_ERR_CODE_MASK) {
655 printf("edp hw link training error: %d\n",
656 val >> HW_LT_ERR_CODE_SHIFT);
663 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
664 unsigned int device_addr,
665 unsigned int val_addr)
669 /* Set EDID device address */
670 writel(device_addr, ®s->aux_addr_7_0);
671 writel(0x0, ®s->aux_addr_15_8);
672 writel(0x0, ®s->aux_addr_19_16);
674 /* Set offset from base address of EDID device */
675 writel(val_addr, ®s->buf_data[0]);
678 * Set I2C transaction and write address
679 * If bit 3 is 1, DisplayPort transaction.
680 * If Bit 3 is 0, I2C transaction.
682 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
683 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1);
685 /* Start AUX transaction */
686 ret = rk_edp_start_aux_transaction(regs);
688 debug("select_i2c_device Aux Transaction fail!\n");
695 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
696 unsigned int val_addr, unsigned int count, u8 edid[])
700 unsigned int cur_data_idx;
701 unsigned int defer = 0;
704 for (i = 0; i < count; i += 16) {
705 for (j = 0; j < 10; j++) { /* try 10 times */
706 /* Clear AUX CH data buffer */
707 writel(BUF_CLR, ®s->buf_data_ctl);
709 /* Set normal AUX CH command */
710 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY);
713 * If Rx sends defer, Tx sends only reads
714 * request without sending addres
717 ret = rk_edp_select_i2c_device(regs,
725 * Set I2C transaction and write data
726 * If bit 3 is 1, DisplayPort transaction.
727 * If Bit 3 is 0, I2C transaction.
729 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
730 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1);
732 /* Start AUX transaction */
733 ret = rk_edp_start_aux_transaction(regs);
737 debug("Aux Transaction fail!\n");
741 /* Check if Rx sends defer */
742 val = readl(®s->aux_rx_comm);
743 if (val == AUX_RX_COMM_AUX_DEFER ||
744 val == AUX_RX_COMM_I2C_DEFER) {
745 debug("Defer: %d\n\n", val);
753 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
754 val = readl(®s->buf_data[cur_data_idx]);
755 edid[i + cur_data_idx] = (u8)val;
762 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
766 ret = rk_edp_init_training(edp);
768 printf("DP LT init failed!\n");
772 ret = rk_edp_hw_link_training(edp);
779 static void rk_edp_init_video(struct rk3288_edp *regs)
781 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
782 ®s->common_int_sta_1);
783 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2);
784 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8);
787 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
789 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
792 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
793 enum clock_recovery_m_value_type type,
797 if (type == REGISTER_M) {
798 setbits_le32(®s->sys_ctl_4, FIX_M_VID);
799 writel(m_value & 0xff, ®s->m_vid_0);
800 writel((m_value >> 8) & 0xff, ®s->m_vid_1);
801 writel((m_value >> 16) & 0xff, ®s->m_vid_2);
803 writel(n_value & 0xf, ®s->n_vid_0);
804 writel((n_value >> 8) & 0xff, ®s->n_vid_1);
805 writel((n_value >> 16) & 0xff, ®s->n_vid_2);
807 clrbits_le32(®s->sys_ctl_4, FIX_M_VID);
809 writel(0x00, ®s->n_vid_0);
810 writel(0x80, ®s->n_vid_1);
811 writel(0x00, ®s->n_vid_2);
815 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
820 start = get_timer(0);
822 val = readl(®s->sys_ctl_1);
824 /* must write value to update DET_STA bit status */
825 writel(val, ®s->sys_ctl_1);
826 val = readl(®s->sys_ctl_1);
827 if (!(val & DET_STA))
830 val = readl(®s->sys_ctl_2);
832 /* must write value to update CHA_STA bit status */
833 writel(val, ®s->sys_ctl_2);
834 val = readl(®s->sys_ctl_2);
835 if (!(val & CHA_STA))
838 } while (get_timer(start) < 100);
843 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
848 start = get_timer(0);
850 val = readl(&edp->regs->sys_ctl_3);
852 /* must write value to update STRM_VALID bit status */
853 writel(val, &edp->regs->sys_ctl_3);
855 val = readl(&edp->regs->sys_ctl_3);
856 if (!(val & STRM_VALID))
858 } while (get_timer(start) < 100);
863 static int rk_edp_config_video(struct rk_edp_priv *edp)
867 rk_edp_config_video_slave_mode(edp->regs);
869 if (!rk_edp_get_pll_locked(edp->regs)) {
870 debug("PLL is not locked yet.\n");
874 ret = rk_edp_is_video_stream_clock_on(edp->regs);
878 /* Set to use the register calculated M/N video */
879 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
881 /* For video bist, Video timing must be generated by register */
882 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
884 /* Disable video mute */
885 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
887 /* Enable video at next frame */
888 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
890 return rk_edp_is_video_stream_on(edp);
893 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
895 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
898 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
902 val = readl(&edp->regs->sys_ctl_3);
903 if (val & HPD_STATUS)
910 * support edp HPD function
911 * some hardware version do not support edp hdp,
912 * we use 200ms to try to get the hpd single now,
913 * if we can not get edp hpd single, it will delay 200ms,
914 * also meet the edp power timing request, to compatible
915 * all of the hardware version
917 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
921 start = get_timer(0);
923 if (rockchip_edp_get_plug_in_status(edp))
926 } while (get_timer(start) < 200);
928 debug("do not get hpd single, force hpd\n");
929 rockchip_edp_force_hpd(edp);
932 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
933 const struct display_timing *edid)
935 struct rk_edp_priv *priv = dev_get_priv(dev);
938 ret = rk_edp_set_link_train(priv);
940 printf("link train failed!\n");
944 rk_edp_init_video(priv->regs);
945 ret = rk_edp_config_video(priv);
947 printf("config video failed\n");
950 ret = panel_enable_backlight(priv->panel);
952 debug("%s: backlight error: %d\n", __func__, ret);
959 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
961 struct rk_edp_priv *priv = dev_get_priv(dev);
962 u32 edid_size = EDID_LENGTH;
966 for (i = 0; i < 3; i++) {
967 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
968 EDID_LENGTH, &buf[EDID_HEADER]);
970 debug("EDID read failed\n");
975 * check if the EDID has an extension flag, and read additional
976 * EDID data if needed
978 if (buf[EDID_EXTENSION_FLAG]) {
979 edid_size += EDID_LENGTH;
980 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
981 EDID_LENGTH, EDID_LENGTH,
984 debug("EDID Read failed!\n");
991 /* After 3 attempts, give up */
998 static int rk_edp_ofdata_to_platdata(struct udevice *dev)
1000 struct rk_edp_priv *priv = dev_get_priv(dev);
1002 priv->regs = dev_read_addr_ptr(dev);
1003 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1008 static int rk_edp_remove(struct udevice *dev)
1010 struct rk_edp_priv *priv = dev_get_priv(dev);
1011 struct rk3288_edp *regs = priv->regs;
1013 setbits_le32(®s->video_ctl_1, VIDEO_MUTE);
1014 clrbits_le32(®s->video_ctl_1, VIDEO_EN);
1015 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL);
1016 setbits_le32(®s->func_en_1, SW_FUNC_EN_N);
1021 static int rk_edp_probe(struct udevice *dev)
1023 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1024 struct rk_edp_priv *priv = dev_get_priv(dev);
1025 struct rk3288_edp *regs = priv->regs;
1029 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1032 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1037 int vop_id = uc_plat->source_id;
1038 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1040 ret = clk_get_by_index(dev, 1, &clk);
1042 ret = clk_set_rate(&clk, 0);
1046 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1050 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1052 ret = clk_set_rate(&clk, 192000000);
1056 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1057 __func__, uc_plat->src_dev->name, ret);
1061 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1062 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1064 /* select epd signal from vop0 or vop1 */
1065 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1067 rockchip_edp_wait_hpd(priv);
1069 rk_edp_init_refclk(regs);
1070 rk_edp_init_interrupt(regs);
1071 rk_edp_enable_sw_function(regs);
1072 ret = rk_edp_init_analog_func(regs);
1075 rk_edp_init_aux(regs);
1080 static const struct dm_display_ops dp_rockchip_ops = {
1081 .read_edid = rk_edp_read_edid,
1082 .enable = rk_edp_enable,
1085 static const struct udevice_id rockchip_dp_ids[] = {
1086 { .compatible = "rockchip,rk3288-edp" },
1090 U_BOOT_DRIVER(dp_rockchip) = {
1091 .name = "edp_rockchip",
1092 .id = UCLASS_DISPLAY,
1093 .of_match = rockchip_dp_ids,
1094 .ops = &dp_rockchip_ops,
1095 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1096 .probe = rk_edp_probe,
1097 .remove = rk_edp_remove,
1098 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),