1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/edp_rk3288.h>
20 #include <asm/arch-rockchip/grf_rk3288.h>
21 #include <asm/arch-rockchip/hardware.h>
22 #include <dt-bindings/clock/rk3288-cru.h>
26 #define DP_LINK_STATUS_SIZE 6
28 static const char * const voltage_names[] = {
29 "0.4V", "0.6V", "0.8V", "1.2V"
31 static const char * const pre_emph_names[] = {
32 "0dB", "3.5dB", "6dB", "9.5dB"
35 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
36 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
39 struct rk3288_edp *regs;
40 struct rk3288_grf *grf;
41 struct udevice *panel;
42 struct link_train link_train;
46 static void rk_edp_init_refclk(struct rk3288_edp *regs)
48 writel(SEL_24M, ®s->analog_ctl_2);
49 writel(REF_CLK_24M, ®s->pll_reg_1);
51 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
52 V2L_CUR_SEL_1MA, ®s->pll_reg_2);
54 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
55 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
58 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
59 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
62 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg);
64 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
65 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
68 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
71 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
74 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
78 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
80 /* Set interrupt pin assertion polarity as high */
81 writel(INT_POL, ®s->int_ctl);
83 /* Clear pending registers */
84 writel(0xff, ®s->common_int_sta_1);
85 writel(0x4f, ®s->common_int_sta_2);
86 writel(0xff, ®s->common_int_sta_3);
87 writel(0x27, ®s->common_int_sta_4);
88 writel(0x7f, ®s->dp_int_sta);
90 /* 0:mask,1: unmask */
91 writel(0x00, ®s->common_int_mask_1);
92 writel(0x00, ®s->common_int_mask_2);
93 writel(0x00, ®s->common_int_mask_3);
94 writel(0x00, ®s->common_int_mask_4);
95 writel(0x00, ®s->int_sta_mask);
98 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
100 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
103 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
107 val = readl(®s->dp_debug_ctl);
109 return val & PLL_LOCK;
112 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
116 writel(0x00, ®s->dp_pd);
117 writel(PLL_LOCK_CHG, ®s->common_int_sta_1);
119 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
121 start = get_timer(0);
122 while (!rk_edp_get_pll_locked(regs)) {
123 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
124 printf("%s: PLL is not locked\n", __func__);
129 /* Enable Serdes FIFO function and Link symbol clock domain module */
130 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N |
131 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
137 static void rk_edp_init_aux(struct rk3288_edp *regs)
139 /* Clear inerrupts related to AUX channel */
140 writel(AUX_FUNC_EN_N, ®s->dp_int_sta);
142 /* Disable AUX channel module */
143 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
145 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
146 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl);
148 /* Enable AUX channel module */
149 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
152 static int rk_edp_aux_enable(struct rk3288_edp *regs)
156 setbits_le32(®s->aux_ch_ctl_2, AUX_EN);
157 start = get_timer(0);
159 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN))
161 } while (get_timer(start) < 20);
166 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
170 start = get_timer(0);
171 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) {
172 if (get_timer(start) > 10)
176 writel(RPLY_RECEIV, ®s->dp_int_sta);
181 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
185 /* Enable AUX CH operation */
186 ret = rk_edp_aux_enable(regs);
188 debug("AUX CH enable timeout!\n");
192 /* Is AUX CH command reply received? */
193 if (rk_edp_is_aux_reply(regs)) {
194 debug("AUX CH command reply failed!\n");
198 /* Clear interrupt source for AUX CH access error */
199 val = readl(®s->dp_int_sta);
201 writel(AUX_ERR, ®s->dp_int_sta);
205 /* Check AUX CH error access status */
206 val = readl(®s->dp_int_sta);
207 if (val & AUX_STATUS_MASK) {
208 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
215 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
216 unsigned int val_addr, u8 *in_data,
218 enum dpcd_request request)
227 len = min(length, 16U);
228 for (try_times = 0; try_times < 10; try_times++) {
230 /* Clear AUX CH data buffer */
231 writel(BUF_CLR, ®s->buf_data_ctl);
233 /* Select DPCD device address */
234 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0);
235 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8);
236 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16);
239 * Set DisplayPort transaction and read 1 byte
240 * If bit 3 is 1, DisplayPort transaction.
241 * If Bit 3 is 0, I2C transaction.
243 if (request == DPCD_WRITE) {
244 val = AUX_LENGTH(len) |
245 AUX_TX_COMM_DP_TRANSACTION |
247 for (i = 0; i < len; i++)
248 writel(*data++, ®s->buf_data[i]);
250 val = AUX_LENGTH(len) |
251 AUX_TX_COMM_DP_TRANSACTION |
254 writel(val, ®s->aux_ch_ctl_1);
256 /* Start AUX transaction */
257 ret = rk_edp_start_aux_transaction(regs);
261 printf("read dpcd Aux Transaction fail!\n");
267 if (request == DPCD_READ) {
268 for (i = 0; i < len; i++)
269 *data++ = (u8)readl(®s->buf_data[i]);
280 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
283 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
286 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
289 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
293 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
298 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
299 if (edp->link_train.revision < 0x11)
302 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
306 value &= ~DP_SET_POWER_MASK;
307 value |= DP_SET_POWER_D0;
309 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
314 * According to the DP 1.1 specification, a "Sink Device must exit the
315 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
316 * Control Field" (register 0x600).
323 static int rk_edp_link_configure(struct rk_edp_priv *edp)
327 values[0] = edp->link_train.link_rate;
328 values[1] = edp->link_train.lane_count;
330 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
334 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
335 const u8 *training_values)
339 for (i = 0; i < edp->link_train.lane_count; i++)
340 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
343 static u8 edp_link_status(const u8 *link_status, int r)
345 return link_status[r - DPCD_LANE0_1_STATUS];
348 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
351 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
352 DP_LINK_STATUS_SIZE);
355 static u8 edp_get_lane_status(const u8 *link_status, int lane)
357 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
358 int s = (lane & 1) * 4;
359 u8 l = edp_link_status(link_status, i);
361 return (l >> s) & 0xf;
364 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
369 for (lane = 0; lane < lane_count; lane++) {
370 lane_status = edp_get_lane_status(link_status, lane);
371 if ((lane_status & DP_LANE_CR_DONE) == 0)
378 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
384 lane_align = edp_link_status(link_status,
385 DPCD_LANE_ALIGN_STATUS_UPDATED);
386 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
388 for (lane = 0; lane < lane_count; lane++) {
389 lane_status = edp_get_lane_status(link_status, lane);
390 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
397 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
399 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
400 int s = ((lane & 1) ?
401 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
402 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
403 u8 l = edp_link_status(link_status, i);
405 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
408 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
411 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
412 int s = ((lane & 1) ?
413 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
414 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
415 u8 l = edp_link_status(link_status, i);
417 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
420 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
427 for (lane = 0; lane < lane_count; lane++) {
430 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
431 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
434 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
436 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
437 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
445 if (v >= DP_VOLTAGE_MAX)
446 v |= DP_TRAIN_MAX_SWING_REACHED;
448 if (p >= DP_PRE_EMPHASIS_MAX)
449 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
451 debug("using signal parameters: voltage %s pre_emph %s\n",
452 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
453 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
454 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
455 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
457 for (lane = 0; lane < 4; lane++)
458 train_set[lane] = v | p;
461 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
463 struct rk3288_edp *regs = edp->regs;
465 uint voltage, tries = 0;
466 u8 status[DP_LINK_STATUS_SIZE];
470 value = DP_TRAINING_PATTERN_1;
471 writel(value, ®s->dp_training_ptn_set);
472 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
475 memset(edp->train_set, '\0', sizeof(edp->train_set));
477 /* clock recovery loop */
483 rk_edp_set_link_training(edp, edp->train_set);
484 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
486 edp->link_train.lane_count);
492 ret = rk_edp_dpcd_read_link_status(edp, status);
494 printf("displayport link status failed, ret=%d\n", ret);
498 clock_recovery = rk_edp_clock_recovery(status,
499 edp->link_train.lane_count);
503 for (i = 0; i < edp->link_train.lane_count; i++) {
504 if ((edp->train_set[i] &
505 DP_TRAIN_MAX_SWING_REACHED) == 0)
508 if (i == edp->link_train.lane_count) {
509 printf("clock recovery reached max voltage\n");
513 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
515 if (++tries == MAX_CR_LOOP) {
516 printf("clock recovery tried 5 times\n");
523 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
525 /* Compute new train_set as requested by sink */
526 edp_get_adjust_train(status, edp->link_train.lane_count,
529 if (clock_recovery) {
530 printf("clock recovery failed: %d\n", clock_recovery);
531 return clock_recovery;
533 debug("clock recovery at voltage %d pre-emphasis %d\n",
534 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
535 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
536 DP_TRAIN_PRE_EMPHASIS_SHIFT);
541 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
543 struct rk3288_edp *regs = edp->regs;
547 u8 status[DP_LINK_STATUS_SIZE];
550 value = DP_TRAINING_PATTERN_2;
551 writel(value, ®s->dp_training_ptn_set);
552 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
556 /* channel equalization loop */
558 for (tries = 0; tries < 5; tries++) {
559 rk_edp_set_link_training(edp, edp->train_set);
562 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
563 printf("displayport link status failed\n");
567 channel_eq = rk_edp_channel_eq(status,
568 edp->link_train.lane_count);
571 edp_get_adjust_train(status, edp->link_train.lane_count,
576 printf("channel eq failed, ret=%d\n", channel_eq);
580 debug("channel eq at voltage %d pre-emphasis %d\n",
581 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
582 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
583 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
588 static int rk_edp_init_training(struct rk_edp_priv *edp)
593 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
598 edp->link_train.revision = values[0];
599 edp->link_train.link_rate = values[1];
600 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
602 debug("max link rate:%d.%dGps max number of lanes:%d\n",
603 edp->link_train.link_rate * 27 / 100,
604 edp->link_train.link_rate * 27 % 100,
605 edp->link_train.lane_count);
607 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
608 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
609 debug("Rx Max Link Rate is abnormal :%x\n",
610 edp->link_train.link_rate);
614 if (edp->link_train.lane_count == 0) {
615 debug("Rx Max Lane count is abnormal :%x\n",
616 edp->link_train.lane_count);
620 ret = rk_edp_link_power_up(edp);
624 return rk_edp_link_configure(edp);
627 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
633 /* Set link rate and count as you want to establish */
634 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
635 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
637 ret = rk_edp_link_train_cr(edp);
640 ret = rk_edp_link_train_ce(edp);
644 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
645 start = get_timer(0);
647 val = readl(&edp->regs->dp_hw_link_training);
648 if (!(val & HW_LT_EN))
650 } while (get_timer(start) < 10);
652 if (val & HW_LT_ERR_CODE_MASK) {
653 printf("edp hw link training error: %d\n",
654 val >> HW_LT_ERR_CODE_SHIFT);
661 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
662 unsigned int device_addr,
663 unsigned int val_addr)
667 /* Set EDID device address */
668 writel(device_addr, ®s->aux_addr_7_0);
669 writel(0x0, ®s->aux_addr_15_8);
670 writel(0x0, ®s->aux_addr_19_16);
672 /* Set offset from base address of EDID device */
673 writel(val_addr, ®s->buf_data[0]);
676 * Set I2C transaction and write address
677 * If bit 3 is 1, DisplayPort transaction.
678 * If Bit 3 is 0, I2C transaction.
680 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
681 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1);
683 /* Start AUX transaction */
684 ret = rk_edp_start_aux_transaction(regs);
686 debug("select_i2c_device Aux Transaction fail!\n");
693 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
694 unsigned int val_addr, unsigned int count, u8 edid[])
698 unsigned int cur_data_idx;
699 unsigned int defer = 0;
702 for (i = 0; i < count; i += 16) {
703 for (j = 0; j < 10; j++) { /* try 10 times */
704 /* Clear AUX CH data buffer */
705 writel(BUF_CLR, ®s->buf_data_ctl);
707 /* Set normal AUX CH command */
708 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY);
711 * If Rx sends defer, Tx sends only reads
712 * request without sending addres
715 ret = rk_edp_select_i2c_device(regs,
723 * Set I2C transaction and write data
724 * If bit 3 is 1, DisplayPort transaction.
725 * If Bit 3 is 0, I2C transaction.
727 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
728 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1);
730 /* Start AUX transaction */
731 ret = rk_edp_start_aux_transaction(regs);
735 debug("Aux Transaction fail!\n");
739 /* Check if Rx sends defer */
740 val = readl(®s->aux_rx_comm);
741 if (val == AUX_RX_COMM_AUX_DEFER ||
742 val == AUX_RX_COMM_I2C_DEFER) {
743 debug("Defer: %d\n\n", val);
751 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
752 val = readl(®s->buf_data[cur_data_idx]);
753 edid[i + cur_data_idx] = (u8)val;
760 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
764 ret = rk_edp_init_training(edp);
766 printf("DP LT init failed!\n");
770 ret = rk_edp_hw_link_training(edp);
777 static void rk_edp_init_video(struct rk3288_edp *regs)
779 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
780 ®s->common_int_sta_1);
781 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2);
782 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8);
785 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
787 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
790 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
791 enum clock_recovery_m_value_type type,
795 if (type == REGISTER_M) {
796 setbits_le32(®s->sys_ctl_4, FIX_M_VID);
797 writel(m_value & 0xff, ®s->m_vid_0);
798 writel((m_value >> 8) & 0xff, ®s->m_vid_1);
799 writel((m_value >> 16) & 0xff, ®s->m_vid_2);
801 writel(n_value & 0xf, ®s->n_vid_0);
802 writel((n_value >> 8) & 0xff, ®s->n_vid_1);
803 writel((n_value >> 16) & 0xff, ®s->n_vid_2);
805 clrbits_le32(®s->sys_ctl_4, FIX_M_VID);
807 writel(0x00, ®s->n_vid_0);
808 writel(0x80, ®s->n_vid_1);
809 writel(0x00, ®s->n_vid_2);
813 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
818 start = get_timer(0);
820 val = readl(®s->sys_ctl_1);
822 /* must write value to update DET_STA bit status */
823 writel(val, ®s->sys_ctl_1);
824 val = readl(®s->sys_ctl_1);
825 if (!(val & DET_STA))
828 val = readl(®s->sys_ctl_2);
830 /* must write value to update CHA_STA bit status */
831 writel(val, ®s->sys_ctl_2);
832 val = readl(®s->sys_ctl_2);
833 if (!(val & CHA_STA))
836 } while (get_timer(start) < 100);
841 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
846 start = get_timer(0);
848 val = readl(&edp->regs->sys_ctl_3);
850 /* must write value to update STRM_VALID bit status */
851 writel(val, &edp->regs->sys_ctl_3);
853 val = readl(&edp->regs->sys_ctl_3);
854 if (!(val & STRM_VALID))
856 } while (get_timer(start) < 100);
861 static int rk_edp_config_video(struct rk_edp_priv *edp)
865 rk_edp_config_video_slave_mode(edp->regs);
867 if (!rk_edp_get_pll_locked(edp->regs)) {
868 debug("PLL is not locked yet.\n");
872 ret = rk_edp_is_video_stream_clock_on(edp->regs);
876 /* Set to use the register calculated M/N video */
877 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
879 /* For video bist, Video timing must be generated by register */
880 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
882 /* Disable video mute */
883 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
885 /* Enable video at next frame */
886 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
888 return rk_edp_is_video_stream_on(edp);
891 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
893 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
896 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
900 val = readl(&edp->regs->sys_ctl_3);
901 if (val & HPD_STATUS)
908 * support edp HPD function
909 * some hardware version do not support edp hdp,
910 * we use 200ms to try to get the hpd single now,
911 * if we can not get edp hpd single, it will delay 200ms,
912 * also meet the edp power timing request, to compatible
913 * all of the hardware version
915 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
919 start = get_timer(0);
921 if (rockchip_edp_get_plug_in_status(edp))
924 } while (get_timer(start) < 200);
926 debug("do not get hpd single, force hpd\n");
927 rockchip_edp_force_hpd(edp);
930 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
931 const struct display_timing *edid)
933 struct rk_edp_priv *priv = dev_get_priv(dev);
936 ret = rk_edp_set_link_train(priv);
938 printf("link train failed!\n");
942 rk_edp_init_video(priv->regs);
943 ret = rk_edp_config_video(priv);
945 printf("config video failed\n");
948 ret = panel_enable_backlight(priv->panel);
950 debug("%s: backlight error: %d\n", __func__, ret);
957 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
959 struct rk_edp_priv *priv = dev_get_priv(dev);
960 u32 edid_size = EDID_LENGTH;
964 for (i = 0; i < 3; i++) {
965 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
966 EDID_LENGTH, &buf[EDID_HEADER]);
968 debug("EDID read failed\n");
973 * check if the EDID has an extension flag, and read additional
974 * EDID data if needed
976 if (buf[EDID_EXTENSION_FLAG]) {
977 edid_size += EDID_LENGTH;
978 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
979 EDID_LENGTH, EDID_LENGTH,
982 debug("EDID Read failed!\n");
989 /* After 3 attempts, give up */
996 static int rk_edp_ofdata_to_platdata(struct udevice *dev)
998 struct rk_edp_priv *priv = dev_get_priv(dev);
1000 priv->regs = dev_read_addr_ptr(dev);
1001 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1006 static int rk_edp_remove(struct udevice *dev)
1008 struct rk_edp_priv *priv = dev_get_priv(dev);
1009 struct rk3288_edp *regs = priv->regs;
1011 setbits_le32(®s->video_ctl_1, VIDEO_MUTE);
1012 clrbits_le32(®s->video_ctl_1, VIDEO_EN);
1013 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL);
1014 setbits_le32(®s->func_en_1, SW_FUNC_EN_N);
1019 static int rk_edp_probe(struct udevice *dev)
1021 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1022 struct rk_edp_priv *priv = dev_get_priv(dev);
1023 struct rk3288_edp *regs = priv->regs;
1027 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1030 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1035 int vop_id = uc_plat->source_id;
1036 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1038 ret = clk_get_by_index(dev, 1, &clk);
1040 ret = clk_set_rate(&clk, 0);
1044 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1048 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1050 ret = clk_set_rate(&clk, 192000000);
1054 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1055 __func__, uc_plat->src_dev->name, ret);
1059 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1060 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1062 /* select epd signal from vop0 or vop1 */
1063 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1065 rockchip_edp_wait_hpd(priv);
1067 rk_edp_init_refclk(regs);
1068 rk_edp_init_interrupt(regs);
1069 rk_edp_enable_sw_function(regs);
1070 ret = rk_edp_init_analog_func(regs);
1073 rk_edp_init_aux(regs);
1078 static const struct dm_display_ops dp_rockchip_ops = {
1079 .read_edid = rk_edp_read_edid,
1080 .enable = rk_edp_enable,
1083 static const struct udevice_id rockchip_dp_ids[] = {
1084 { .compatible = "rockchip,rk3288-edp" },
1088 U_BOOT_DRIVER(dp_rockchip) = {
1089 .name = "edp_rockchip",
1090 .id = UCLASS_DISPLAY,
1091 .of_match = rockchip_dp_ids,
1092 .ops = &dp_rockchip_ops,
1093 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1094 .probe = rk_edp_probe,
1095 .remove = rk_edp_remove,
1096 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),