drivers/video/raydium-rm68200.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
   4  * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   5  *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *
   7  * This rm68200 panel driver is inspired from the Linux Kernel driver
   8  * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
   9  */
  10 #include <common.h>
  11 #include <backlight.h>
  12 #include <dm.h>
  13 #include <mipi_dsi.h>
  14 #include <panel.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/delay.h>
  18 #include <power/regulator.h>
  19
  20 /*** Manufacturer Command Set ***/
  21 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  22 #define MCS_CMD1_UCS    0x00 /* User Command Set (UCS = CMD1) */
  23 #define MCS_CMD2_P0     0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  24 #define MCS_CMD2_P1     0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  25 #define MCS_CMD2_P2     0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  26 #define MCS_CMD2_P3     0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  27
  28 /* CMD2 P0 commands (Display Options and Power) */
  29 #define MCS_STBCTR      0x12 /* TE1 Output Setting Zig-Zag Connection */
  30 #define MCS_SGOPCTR     0x16 /* Source Bias Current */
  31 #define MCS_SDCTR       0x1A /* Source Output Delay Time */
  32 #define MCS_INVCTR      0x1B /* Inversion Type */
  33 #define MCS_EXT_PWR_IC  0x24 /* External PWR IC Control */
  34 #define MCS_SETAVDD     0x27 /* PFM Control for AVDD Output */
  35 #define MCS_SETAVEE     0x29 /* PFM Control for AVEE Output */
  36 #define MCS_BT2CTR      0x2B /* DDVDL Charge Pump Control */
  37 #define MCS_BT3CTR      0x2F /* VGH Charge Pump Control */
  38 #define MCS_BT4CTR      0x34 /* VGL Charge Pump Control */
  39 #define MCS_VCMCTR      0x46 /* VCOM Output Level Control */
  40 #define MCS_SETVGN      0x52 /* VG M/S N Control */
  41 #define MCS_SETVGP      0x54 /* VG M/S P Control */
  42 #define MCS_SW_CTRL     0x5F /* Interface Control for PFM and MIPI */
  43
  44 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  45 #define GOA_VSTV1               0x00
  46 #define GOA_VSTV2               0x07
  47 #define GOA_VCLK1               0x0E
  48 #define GOA_VCLK2               0x17
  49 #define GOA_VCLK_OPT1           0x20
  50 #define GOA_BICLK1              0x2A
  51 #define GOA_BICLK2              0x37
  52 #define GOA_BICLK3              0x44
  53 #define GOA_BICLK4              0x4F
  54 #define GOA_BICLK_OPT1          0x5B
  55 #define GOA_BICLK_OPT2          0x60
  56 #define MCS_GOA_GPO1            0x6D
  57 #define MCS_GOA_GPO2            0x71
  58 #define MCS_GOA_EQ              0x74
  59 #define MCS_GOA_CLK_GALLON      0x7C
  60 #define MCS_GOA_FS_SEL0         0x7E
  61 #define MCS_GOA_FS_SEL1         0x87
  62 #define MCS_GOA_FS_SEL2         0x91
  63 #define MCS_GOA_FS_SEL3         0x9B
  64 #define MCS_GOA_BS_SEL0         0xAC
  65 #define MCS_GOA_BS_SEL1         0xB5
  66 #define MCS_GOA_BS_SEL2         0xBF
  67 #define MCS_GOA_BS_SEL3         0xC9
  68 #define MCS_GOA_BS_SEL4         0xD3
  69
  70 /* CMD2 P3 commands (Gamma) */
  71 #define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
  72 #define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
  73
  74 struct rm68200_panel_priv {
  75         struct udevice *reg;
  76         struct udevice *backlight;
  77         struct gpio_desc reset;
  78 };
  79
  80 static const struct display_timing default_timing = {
  81         .pixelclock.typ         = 54000000,
  82         .hactive.typ            = 720,
  83         .hfront_porch.typ       = 48,
  84         .hback_porch.typ        = 48,
  85         .hsync_len.typ          = 9,
  86         .vactive.typ            = 1280,
  87         .vfront_porch.typ       = 12,
  88         .vback_porch.typ        = 12,
  89         .vsync_len.typ          = 5,
  90 };
  91
  92 static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
  93                                   size_t len)
  94 {
  95         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  96         struct mipi_dsi_device *device = plat->device;
  97         int err;
  98
  99         err = mipi_dsi_dcs_write_buffer(device, data, len);
 100         if (err < 0)
 101                 dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
 102 }
 103
 104 static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
 105 {
 106         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 107         struct mipi_dsi_device *device = plat->device;
 108         int err;
 109
 110         err = mipi_dsi_dcs_write(device, cmd, &value, 1);
 111         if (err < 0)
 112                 dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
 113 }
 114
 115 #define dcs_write_seq(ctx, seq...)                              \
 116 ({                                                              \
 117         static const u8 d[] = { seq };                          \
 118                                                                 \
 119         rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
 120 })
 121
 122 /*
 123  * This panel is not able to auto-increment all cmd addresses so for some of
 124  * them, we need to send them one by one...
 125  */
 126 #define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
 127 ({                                                              \
 128         static const u8 d[] = { seq };                          \
 129         unsigned int i;                                         \
 130                                                                 \
 131         for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
 132                 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
 133 })
 134
 135 static void rm68200_init_sequence(struct udevice *dev)
 136 {
 137         /* Enter CMD2 with page 0 */
 138         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
 139         dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
 140         dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
 141         dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
 142         dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
 143         dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
 144         dcs_write_seq(dev, MCS_BT3CTR, 0x53);
 145         dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
 146         dcs_write_seq(dev, MCS_INVCTR, 0x00);
 147         dcs_write_seq(dev, MCS_STBCTR, 0x0A);
 148         dcs_write_seq(dev, MCS_SDCTR, 0x06);
 149         dcs_write_seq(dev, MCS_VCMCTR, 0x56);
 150         dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
 151         dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
 152         dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 153
 154         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 155         dcs_write_seq(dev, GOA_VSTV1, 0x05);
 156         dcs_write_seq(dev, 0x02, 0x0B);
 157         dcs_write_seq(dev, 0x03, 0x0F);
 158         dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
 159         dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 160                           0x50);
 161         dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 162                           0x00, 0x85, 0x08);
 163         dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 164                           0x00, 0x85, 0x08);
 165         dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 166                       0x00, 0x00, 0x00, 0x00);
 167         dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
 168         dcs_write_seq(dev, 0x2D, 0x01);
 169         dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
 170                       0x00);
 171         dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
 172         dcs_write_seq(dev, 0x3D, 0x40);
 173         dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
 174         dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 175                       0x00, 0x00, 0x00, 0x00, 0x00);
 176         dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 177                       0x00, 0x00);
 178         dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
 179         dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
 180         dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 181                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 182         dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
 183         dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
 184         dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 185                       0x00, 0x00);
 186         dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
 187         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 188                           0x16, 0x12, 0x08, 0x3F);
 189         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 190                           0x0A, 0x0E, 0x3F, 0x3F, 0x00);
 191         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 192                           0x05, 0x01, 0x3F, 0x3F, 0x0F);
 193         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 194                           0x3F);
 195         dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
 196         dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
 197         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 198                           0x15, 0x11, 0x0F, 0x3F);
 199         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 200                           0x0D, 0x09, 0x3F, 0x3F, 0x07);
 201         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 202                           0x02, 0x06, 0x3F, 0x3F, 0x08);
 203         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 204                           0x3F, 0x3F, 0x0E, 0x10, 0x14);
 205         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
 206         dcs_write_seq(dev, 0xDC, 0x02);
 207         dcs_write_seq(dev, 0xDE, 0x12);
 208
 209         dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
 210         dcs_write_seq(dev, 0x01, 0x75);
 211
 212         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
 213         dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 214                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 215                           0x12, 0x0C, 0x00);
 216         dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 217                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 218                           0x12, 0x0C, 0x00);
 219
 220         /* Exit CMD2 */
 221         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 222 }
 223
 224 static int rm68200_panel_enable_backlight(struct udevice *dev)
 225 {
 226         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 227         struct mipi_dsi_device *device = plat->device;
 228         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 229         int ret;
 230
 231         ret = mipi_dsi_attach(device);
 232         if (ret < 0)
 233                 return ret;
 234
 235         rm68200_init_sequence(dev);
 236
 237         ret = mipi_dsi_dcs_exit_sleep_mode(device);
 238         if (ret)
 239                 return ret;
 240
 241         mdelay(125);
 242
 243         ret = mipi_dsi_dcs_set_display_on(device);
 244         if (ret)
 245                 return ret;
 246
 247         mdelay(20);
 248
 249         ret = backlight_enable(priv->backlight);
 250         if (ret)
 251                 return ret;
 252
 253         return 0;
 254 }
 255
 256 static int rm68200_panel_get_display_timing(struct udevice *dev,
 257                                             struct display_timing *timings)
 258 {
 259         memcpy(timings, &default_timing, sizeof(*timings));
 260
 261         return 0;
 262 }
 263
 264 static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
 265 {
 266         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 267         int ret;
 268
 269         if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
 270                 ret =  device_get_supply_regulator(dev, "power-supply",
 271                                                    &priv->reg);
 272                 if (ret && ret != -ENOENT) {
 273                         dev_err(dev, "Warning: cannot get power supply\n");
 274                         return ret;
 275                 }
 276         }
 277
 278         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
 279                                    GPIOD_IS_OUT);
 280         if (ret) {
 281                 dev_err(dev, "Warning: cannot get reset GPIO\n");
 282                 if (ret != -ENOENT)
 283                         return ret;
 284         }
 285
 286         ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
 287                                            "backlight", &priv->backlight);
 288         if (ret) {
 289                 dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
 290                 return ret;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int rm68200_panel_probe(struct udevice *dev)
 297 {
 298         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 299         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 300         int ret;
 301
 302         if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 303                 ret = regulator_set_enable(priv->reg, true);
 304                 if (ret)
 305                         return ret;
 306         }
 307
 308         /* reset panel */
 309         dm_gpio_set_value(&priv->reset, true);
 310         mdelay(1);
 311         dm_gpio_set_value(&priv->reset, false);
 312         mdelay(10);
 313
 314         /* fill characteristics of DSI data link */
 315         plat->lanes = 2;
 316         plat->format = MIPI_DSI_FMT_RGB888;
 317         plat->mode_flags = MIPI_DSI_MODE_VIDEO |
 318                            MIPI_DSI_MODE_VIDEO_BURST |
 319                            MIPI_DSI_MODE_LPM;
 320
 321         return 0;
 322 }
 323
 324 static const struct panel_ops rm68200_panel_ops = {
 325         .enable_backlight = rm68200_panel_enable_backlight,
 326         .get_display_timing = rm68200_panel_get_display_timing,
 327 };
 328
 329 static const struct udevice_id rm68200_panel_ids[] = {
 330         { .compatible = "raydium,rm68200" },
 331         { }
 332 };
 333
 334 U_BOOT_DRIVER(rm68200_panel) = {
 335         .name                     = "rm68200_panel",
 336         .id                       = UCLASS_PANEL,
 337         .of_match                 = rm68200_panel_ids,
 338         .ops                      = &rm68200_panel_ops,
 339         .ofdata_to_platdata       = rm68200_panel_ofdata_to_platdata,
 340         .probe                    = rm68200_panel_probe,
 341         .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
 342         .priv_auto_alloc_size   = sizeof(struct rm68200_panel_priv),
 343 };