drivers/video/orisetech_otm8009a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
   4  * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   5  *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *
   7  * This otm8009a panel driver is inspired from the Linux Kernel driver
   8  * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
   9  */
  10 #include <common.h>
  11 #include <backlight.h>
  12 #include <dm.h>
  13 #include <mipi_dsi.h>
  14 #include <panel.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/delay.h>
  18 #include <power/regulator.h>
  19
  20 #define OTM8009A_BACKLIGHT_DEFAULT      240
  21 #define OTM8009A_BACKLIGHT_MAX          255
  22
  23 /* Manufacturer Command Set */
  24 #define MCS_ADRSFT      0x0000  /* Address Shift Function */
  25 #define MCS_PANSET      0xB3A6  /* Panel Type Setting */
  26 #define MCS_SD_CTRL     0xC0A2  /* Source Driver Timing Setting */
  27 #define MCS_P_DRV_M     0xC0B4  /* Panel Driving Mode */
  28 #define MCS_OSC_ADJ     0xC181  /* Oscillator Adjustment for Idle/Normal mode */
  29 #define MCS_RGB_VID_SET 0xC1A1  /* RGB Video Mode Setting */
  30 #define MCS_SD_PCH_CTRL 0xC480  /* Source Driver Precharge Control */
  31 #define MCS_NO_DOC1     0xC48A  /* Command not documented */
  32 #define MCS_PWR_CTRL1   0xC580  /* Power Control Setting 1 */
  33 #define MCS_PWR_CTRL2   0xC590  /* Power Control Setting 2 for Normal Mode */
  34 #define MCS_PWR_CTRL4   0xC5B0  /* Power Control Setting 4 for DC Voltage */
  35 #define MCS_PANCTRLSET1 0xCB80  /* Panel Control Setting 1 */
  36 #define MCS_PANCTRLSET2 0xCB90  /* Panel Control Setting 2 */
  37 #define MCS_PANCTRLSET3 0xCBA0  /* Panel Control Setting 3 */
  38 #define MCS_PANCTRLSET4 0xCBB0  /* Panel Control Setting 4 */
  39 #define MCS_PANCTRLSET5 0xCBC0  /* Panel Control Setting 5 */
  40 #define MCS_PANCTRLSET6 0xCBD0  /* Panel Control Setting 6 */
  41 #define MCS_PANCTRLSET7 0xCBE0  /* Panel Control Setting 7 */
  42 #define MCS_PANCTRLSET8 0xCBF0  /* Panel Control Setting 8 */
  43 #define MCS_PANU2D1     0xCC80  /* Panel U2D Setting 1 */
  44 #define MCS_PANU2D2     0xCC90  /* Panel U2D Setting 2 */
  45 #define MCS_PANU2D3     0xCCA0  /* Panel U2D Setting 3 */
  46 #define MCS_PAND2U1     0xCCB0  /* Panel D2U Setting 1 */
  47 #define MCS_PAND2U2     0xCCC0  /* Panel D2U Setting 2 */
  48 #define MCS_PAND2U3     0xCCD0  /* Panel D2U Setting 3 */
  49 #define MCS_GOAVST      0xCE80  /* GOA VST Setting */
  50 #define MCS_GOACLKA1    0xCEA0  /* GOA CLKA1 Setting */
  51 #define MCS_GOACLKA3    0xCEB0  /* GOA CLKA3 Setting */
  52 #define MCS_GOAECLK     0xCFC0  /* GOA ECLK Setting */
  53 #define MCS_NO_DOC2     0xCFD0  /* Command not documented */
  54 #define MCS_GVDDSET     0xD800  /* GVDD/NGVDD */
  55 #define MCS_VCOMDC      0xD900  /* VCOM Voltage Setting */
  56 #define MCS_GMCT2_2P    0xE100  /* Gamma Correction 2.2+ Setting */
  57 #define MCS_GMCT2_2N    0xE200  /* Gamma Correction 2.2- Setting */
  58 #define MCS_NO_DOC3     0xF5B6  /* Command not documented */
  59 #define MCS_CMD2_ENA1   0xFF00  /* Enable Access Command2 "CMD2" */
  60 #define MCS_CMD2_ENA2   0xFF80  /* Enable Access Orise Command2 */
  61
  62 struct otm8009a_panel_priv {
  63         struct udevice *reg;
  64         struct gpio_desc reset;
  65         unsigned int lanes;
  66         enum mipi_dsi_pixel_format format;
  67         unsigned long mode_flags;
  68 };
  69
  70 static const struct display_timing default_timing = {
  71         .pixelclock.typ         = 29700000,
  72         .hactive.typ            = 480,
  73         .hfront_porch.typ       = 98,
  74         .hback_porch.typ        = 98,
  75         .hsync_len.typ          = 32,
  76         .vactive.typ            = 800,
  77         .vfront_porch.typ       = 15,
  78         .vback_porch.typ        = 14,
  79         .vsync_len.typ          = 10,
  80 };
  81
  82 static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
  83                                    size_t len)
  84 {
  85         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  86         struct mipi_dsi_device *device = plat->device;
  87
  88         if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
  89                 dev_err(dev, "mipi dsi dcs write buffer failed\n");
  90 }
  91
  92 static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
  93                                       size_t len)
  94 {
  95         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  96         struct mipi_dsi_device *device = plat->device;
  97
  98         /* data will be sent in dsi hs mode (ie. no lpm) */
  99         device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 100
 101         if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
 102                 dev_err(dev, "mipi dsi dcs write buffer failed\n");
 103
 104         /* restore back the dsi lpm mode */
 105         device->mode_flags |= MIPI_DSI_MODE_LPM;
 106 }
 107
 108 #define dcs_write_seq(dev, seq...)                              \
 109 ({                                                              \
 110         static const u8 d[] = { seq };                          \
 111         otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d));          \
 112 })
 113
 114 #define dcs_write_seq_hs(dev, seq...)                           \
 115 ({                                                              \
 116         static const u8 d[] = { seq };                          \
 117         otm8009a_dcs_write_buf_hs(dev, d, ARRAY_SIZE(d));       \
 118 })
 119
 120 #define dcs_write_cmd_at(dev, cmd, seq...)              \
 121 ({                                                      \
 122         static const u16 c = cmd;                       \
 123         struct udevice *device = dev;                   \
 124         dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF);  \
 125         dcs_write_seq(device, (c) >> 8, seq);           \
 126 })
 127
 128 static int otm8009a_init_sequence(struct udevice *dev)
 129 {
 130         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 131         struct mipi_dsi_device *device = plat->device;
 132         int ret;
 133
 134         /* Enter CMD2 */
 135         dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
 136
 137         /* Enter Orise Command2 */
 138         dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09);
 139
 140         dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30);
 141         mdelay(10);
 142
 143         dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40);
 144         mdelay(10);
 145
 146         dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9);
 147         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34);
 148         dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50);
 149         dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E);
 150         dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */
 151         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01);
 152         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34);
 153         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33);
 154         dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79);
 155         dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B);
 156         dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83);
 157         dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83);
 158         dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E);
 159         dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01);
 160
 161         dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
 162         dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
 163                          0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
 164         dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
 165                          0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
 166         dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
 167                          0x01, 0x02, 0x00, 0x00);
 168
 169         dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00);
 170
 171         dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 172         dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 173                          0, 0, 0, 0, 0);
 174         dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 175                          0, 0, 0, 0, 0);
 176         dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 177         dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
 178                          0, 0, 0, 0, 0);
 179         dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
 180                          4, 0, 0, 0, 0);
 181         dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 182         dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 183                          0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
 184
 185         dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
 186                          0x00, 0x00, 0x00, 0x00);
 187         dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 188                          0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
 189         dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
 190                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 191         dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
 192                          0x00, 0x00, 0x00, 0x00);
 193         dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 194                          0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
 195         dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
 196                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 197
 198         dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66);
 199
 200         dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06);
 201
 202         dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 203                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 204                          0x01);
 205         dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 206                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 207                          0x01);
 208
 209         /* Exit CMD2 */
 210         dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
 211
 212         ret =  mipi_dsi_dcs_nop(device);
 213         if (ret)
 214                 return ret;
 215
 216         ret = mipi_dsi_dcs_exit_sleep_mode(device);
 217         if (ret)
 218                 return ret;
 219
 220         /* Wait for sleep out exit */
 221         mdelay(120);
 222
 223         /* Default portrait 480x800 rgb24 */
 224         dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
 225
 226         ret =  mipi_dsi_dcs_set_column_address(device, 0,
 227                                                default_timing.hactive.typ - 1);
 228         if (ret)
 229                 return ret;
 230
 231         ret =  mipi_dsi_dcs_set_page_address(device, 0,
 232                                              default_timing.vactive.typ - 1);
 233         if (ret)
 234                 return ret;
 235
 236         /* See otm8009a driver documentation for pixel format descriptions */
 237         ret =  mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT |
 238                                              MIPI_DCS_PIXEL_FMT_24BIT << 4);
 239         if (ret)
 240                 return ret;
 241
 242         /* Disable CABC feature */
 243         dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
 244
 245         ret = mipi_dsi_dcs_set_display_on(device);
 246         if (ret)
 247                 return ret;
 248
 249         ret = mipi_dsi_dcs_nop(device);
 250         if (ret)
 251                 return ret;
 252
 253         /* Send Command GRAM memory write (no parameters) */
 254         dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START);
 255
 256         return 0;
 257 }
 258
 259 static int otm8009a_panel_enable_backlight(struct udevice *dev)
 260 {
 261         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 262         struct mipi_dsi_device *device = plat->device;
 263         int ret;
 264
 265         ret = mipi_dsi_attach(device);
 266         if (ret < 0)
 267                 return ret;
 268
 269         ret = otm8009a_init_sequence(dev);
 270         if (ret)
 271                 return ret;
 272
 273         /*
 274          * Power on the backlight with the requested brightness
 275          * Note We can not use mipi_dsi_dcs_set_display_brightness()
 276          * as otm8009a driver support only 8-bit brightness (1 param).
 277          */
 278         dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
 279                       OTM8009A_BACKLIGHT_DEFAULT);
 280
 281         /* Update Brightness Control & Backlight */
 282         dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
 283
 284         /* Update Brightness Control & Backlight */
 285         dcs_write_seq_hs(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY);
 286
 287         /* Need to wait a few time before sending the first image */
 288         mdelay(10);
 289
 290         return 0;
 291 }
 292
 293 static int otm8009a_panel_get_display_timing(struct udevice *dev,
 294                                              struct display_timing *timings)
 295 {
 296         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 297         struct mipi_dsi_device *device = plat->device;
 298         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 299
 300         memcpy(timings, &default_timing, sizeof(*timings));
 301
 302         /* fill characteristics of DSI data link */
 303         device->lanes = priv->lanes;
 304         device->format = priv->format;
 305         device->mode_flags = priv->mode_flags;
 306
 307         return 0;
 308 }
 309
 310 static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
 311 {
 312         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 313         int ret;
 314
 315         if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
 316                 ret =  device_get_supply_regulator(dev, "power-supply",
 317                                                    &priv->reg);
 318                 if (ret && ret != -ENOENT) {
 319                         dev_err(dev, "Warning: cannot get power supply\n");
 320                         return ret;
 321                 }
 322         }
 323
 324         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
 325                                    GPIOD_IS_OUT);
 326         if (ret) {
 327                 dev_err(dev, "warning: cannot get reset GPIO\n");
 328                 if (ret != -ENOENT)
 329                         return ret;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int otm8009a_panel_probe(struct udevice *dev)
 336 {
 337         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 338         int ret;
 339
 340         if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 341                 dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
 342                 ret = regulator_set_enable(priv->reg, true);
 343                 if (ret)
 344                         return ret;
 345         }
 346
 347         /* reset panel */
 348         dm_gpio_set_value(&priv->reset, true);
 349         mdelay(1); /* >50us */
 350         dm_gpio_set_value(&priv->reset, false);
 351         mdelay(10); /* >5ms */
 352
 353         priv->lanes = 2;
 354         priv->format = MIPI_DSI_FMT_RGB888;
 355         priv->mode_flags = MIPI_DSI_MODE_VIDEO |
 356                            MIPI_DSI_MODE_VIDEO_BURST |
 357                            MIPI_DSI_MODE_LPM;
 358
 359         return 0;
 360 }
 361
 362 static const struct panel_ops otm8009a_panel_ops = {
 363         .enable_backlight = otm8009a_panel_enable_backlight,
 364         .get_display_timing = otm8009a_panel_get_display_timing,
 365 };
 366
 367 static const struct udevice_id otm8009a_panel_ids[] = {
 368         { .compatible = "orisetech,otm8009a" },
 369         { }
 370 };
 371
 372 U_BOOT_DRIVER(otm8009a_panel) = {
 373         .name                     = "otm8009a_panel",
 374         .id                       = UCLASS_PANEL,
 375         .of_match                 = otm8009a_panel_ids,
 376         .ops                      = &otm8009a_panel_ops,
 377         .ofdata_to_platdata       = otm8009a_panel_ofdata_to_platdata,
 378         .probe                    = otm8009a_panel_probe,
 379         .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
 380         .priv_auto_alloc_size   = sizeof(struct otm8009a_panel_priv),
 381 };