drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef pr_fmt
  27 #undef pr_fmt
  28 #endif
  29
  30 #ifdef DSS_SUBSYS_NAME
  31 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  32 #else
  33 #define pr_fmt(fmt) fmt
  34 #endif
  35
  36 #define DSSDBG(format, ...) \
  37         pr_debug(format, ## __VA_ARGS__)
  38
  39 #ifdef DSS_SUBSYS_NAME
  40 #define DSSERR(format, ...) \
  41         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  42         ## __VA_ARGS__)
  43 #else
  44 #define DSSERR(format, ...) \
  45         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  46 #endif
  47
  48 #ifdef DSS_SUBSYS_NAME
  49 #define DSSINFO(format, ...) \
  50         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  51         ## __VA_ARGS__)
  52 #else
  53 #define DSSINFO(format, ...) \
  54         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  55 #endif
  56
  57 #ifdef DSS_SUBSYS_NAME
  58 #define DSSWARN(format, ...) \
  59         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  60         ## __VA_ARGS__)
  61 #else
  62 #define DSSWARN(format, ...) \
  63         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  64 #endif
  65
  66 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  67    number. For example 7:0 */
  68 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  69 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  70 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  71 #define FLD_MOD(orig, val, start, end) \
  72         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  73
  74 enum dss_io_pad_mode {
  75         DSS_IO_PAD_MODE_RESET,
  76         DSS_IO_PAD_MODE_RFBI,
  77         DSS_IO_PAD_MODE_BYPASS,
  78 };
  79
  80 enum dss_hdmi_venc_clk_source_select {
  81         DSS_VENC_TV_CLK = 0,
  82         DSS_HDMI_M_PCLK = 1,
  83 };
  84
  85 enum dss_dsi_content_type {
  86         DSS_DSI_CONTENT_DCS,
  87         DSS_DSI_CONTENT_GENERIC,
  88 };
  89
  90 enum dss_writeback_channel {
  91         DSS_WB_LCD1_MGR =       0,
  92         DSS_WB_LCD2_MGR =       1,
  93         DSS_WB_TV_MGR =         2,
  94         DSS_WB_OVL0 =           3,
  95         DSS_WB_OVL1 =           4,
  96         DSS_WB_OVL2 =           5,
  97         DSS_WB_OVL3 =           6,
  98         DSS_WB_LCD3_MGR =       7,
  99 };
 100
 101 struct dss_clock_info {
 102         /* rates that we get with dividers below */
 103         unsigned long fck;
 104
 105         /* dividers */
 106         u16 fck_div;
 107 };
 108
 109 struct dispc_clock_info {
 110         /* rates that we get with dividers below */
 111         unsigned long lck;
 112         unsigned long pck;
 113
 114         /* dividers */
 115         u16 lck_div;
 116         u16 pck_div;
 117 };
 118
 119 struct dsi_clock_info {
 120         /* rates that we get with dividers below */
 121         unsigned long fint;
 122         unsigned long clkin4ddr;
 123         unsigned long clkin;
 124         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 125                                                  * OMAP4: PLLx_CLK1 */
 126         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 127                                                  * OMAP4: PLLx_CLK2 */
 128         unsigned long lp_clk;
 129
 130         /* dividers */
 131         u16 regn;
 132         u16 regm;
 133         u16 regm_dispc; /* OMAP3: REGM3
 134                          * OMAP4: REGM4 */
 135         u16 regm_dsi;   /* OMAP3: REGM4
 136                          * OMAP4: REGM5 */
 137         u16 lp_clk_div;
 138 };
 139
 140 struct reg_field {
 141         u16 reg;
 142         u8 high;
 143         u8 low;
 144 };
 145
 146 struct dss_lcd_mgr_config {
 147         enum dss_io_pad_mode io_pad_mode;
 148
 149         bool stallmode;
 150         bool fifohandcheck;
 151
 152         struct dispc_clock_info clock_info;
 153
 154         int video_port_width;
 155
 156         int lcden_sig_polarity;
 157 };
 158
 159 struct seq_file;
 160 struct platform_device;
 161
 162 /* core */
 163 struct platform_device *dss_get_core_pdev(void);
 164 struct bus_type *dss_get_bus(void);
 165 struct regulator *dss_get_vdds_dsi(void);
 166 struct regulator *dss_get_vdds_sdi(void);
 167 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 168 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 169 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 170 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 171
 172 struct omap_dss_device *dss_alloc_and_init_device(struct device *parent);
 173 int dss_add_device(struct omap_dss_device *dssdev);
 174 void dss_unregister_device(struct omap_dss_device *dssdev);
 175 void dss_unregister_child_devices(struct device *parent);
 176 void dss_put_device(struct omap_dss_device *dssdev);
 177 void dss_copy_device_pdata(struct omap_dss_device *dst,
 178                 const struct omap_dss_device *src);
 179
 180 /* apply */
 181 void dss_apply_init(void);
 182 int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr);
 183 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 184 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
 185 int omap_dss_mgr_apply(struct omap_overlay_manager *mgr);
 186
 187 int dss_mgr_enable(struct omap_overlay_manager *mgr);
 188 void dss_mgr_disable(struct omap_overlay_manager *mgr);
 189 int dss_mgr_set_info(struct omap_overlay_manager *mgr,
 190                 struct omap_overlay_manager_info *info);
 191 void dss_mgr_get_info(struct omap_overlay_manager *mgr,
 192                 struct omap_overlay_manager_info *info);
 193 int dss_mgr_set_output(struct omap_overlay_manager *mgr,
 194                 struct omap_dss_output *output);
 195 int dss_mgr_unset_output(struct omap_overlay_manager *mgr);
 196 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
 197                 const struct omap_video_timings *timings);
 198 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
 199                 const struct dss_lcd_mgr_config *config);
 200
 201 bool dss_ovl_is_enabled(struct omap_overlay *ovl);
 202 int dss_ovl_enable(struct omap_overlay *ovl);
 203 int dss_ovl_disable(struct omap_overlay *ovl);
 204 int dss_ovl_set_info(struct omap_overlay *ovl,
 205                 struct omap_overlay_info *info);
 206 void dss_ovl_get_info(struct omap_overlay *ovl,
 207                 struct omap_overlay_info *info);
 208 int dss_ovl_set_manager(struct omap_overlay *ovl,
 209                 struct omap_overlay_manager *mgr);
 210 int dss_ovl_unset_manager(struct omap_overlay *ovl);
 211
 212 /* output */
 213 void dss_register_output(struct omap_dss_output *out);
 214 void dss_unregister_output(struct omap_dss_output *out);
 215
 216 /* display */
 217 int dss_suspend_all_devices(void);
 218 int dss_resume_all_devices(void);
 219 void dss_disable_all_devices(void);
 220
 221 int dss_init_device(struct platform_device *pdev,
 222                 struct omap_dss_device *dssdev);
 223 void dss_uninit_device(struct platform_device *pdev,
 224                 struct omap_dss_device *dssdev);
 225
 226 int display_init_sysfs(struct platform_device *pdev,
 227                 struct omap_dss_device *dssdev);
 228 void display_uninit_sysfs(struct platform_device *pdev,
 229                 struct omap_dss_device *dssdev);
 230
 231 /* manager */
 232 int dss_init_overlay_managers(struct platform_device *pdev);
 233 void dss_uninit_overlay_managers(struct platform_device *pdev);
 234 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 235                 const struct omap_overlay_manager_info *info);
 236 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 237                 const struct omap_video_timings *timings);
 238 int dss_mgr_check(struct omap_overlay_manager *mgr,
 239                 struct omap_overlay_manager_info *info,
 240                 const struct omap_video_timings *mgr_timings,
 241                 const struct dss_lcd_mgr_config *config,
 242                 struct omap_overlay_info **overlay_infos);
 243
 244 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 245 {
 246         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 247                         id == OMAP_DSS_CHANNEL_LCD3)
 248                 return true;
 249         else
 250                 return false;
 251 }
 252
 253 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 254                 struct platform_device *pdev);
 255 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 256
 257 /* overlay */
 258 void dss_init_overlays(struct platform_device *pdev);
 259 void dss_uninit_overlays(struct platform_device *pdev);
 260 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 261 int dss_ovl_simple_check(struct omap_overlay *ovl,
 262                 const struct omap_overlay_info *info);
 263 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 264                 const struct omap_video_timings *mgr_timings);
 265 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 266                 enum omap_color_mode mode);
 267 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 268                 struct platform_device *pdev);
 269 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 270
 271 /* DSS */
 272 int dss_init_platform_driver(void) __init;
 273 void dss_uninit_platform_driver(void);
 274
 275 int dss_dpi_select_source(enum omap_channel channel);
 276 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 277 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 278 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 279 void dss_dump_clocks(struct seq_file *s);
 280
 281 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 282 void dss_debug_dump_clocks(struct seq_file *s);
 283 #endif
 284
 285 int dss_get_ctx_loss_count(void);
 286
 287 void dss_sdi_init(int datapairs);
 288 int dss_sdi_enable(void);
 289 void dss_sdi_disable(void);
 290
 291 void dss_select_dsi_clk_source(int dsi_module,
 292                 enum omap_dss_clk_source clk_src);
 293 void dss_select_lcd_clk_source(enum omap_channel channel,
 294                 enum omap_dss_clk_source clk_src);
 295 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 296 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 297 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 298
 299 void dss_set_venc_output(enum omap_dss_venc_type type);
 300 void dss_set_dac_pwrdn_bgz(bool enable);
 301
 302 unsigned long dss_get_dpll4_rate(void);
 303 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 304 int dss_set_clock_div(struct dss_clock_info *cinfo);
 305 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
 306                 struct dispc_clock_info *dispc_cinfo);
 307
 308 /* SDI */
 309 int sdi_init_platform_driver(void) __init;
 310 void sdi_uninit_platform_driver(void) __exit;
 311
 312 /* DSI */
 313 #ifdef CONFIG_OMAP2_DSS_DSI
 314
 315 struct dentry;
 316 struct file_operations;
 317
 318 int dsi_init_platform_driver(void) __init;
 319 void dsi_uninit_platform_driver(void) __exit;
 320
 321 int dsi_runtime_get(struct platform_device *dsidev);
 322 void dsi_runtime_put(struct platform_device *dsidev);
 323
 324 void dsi_dump_clocks(struct seq_file *s);
 325
 326 void dsi_irq_handler(void);
 327 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 328
 329 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 330 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 331                 struct dsi_clock_info *cinfo);
 332 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 333                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 334                 struct dispc_clock_info *dispc_cinfo);
 335 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 336                 bool enable_hsdiv);
 337 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 338 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 339 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 340 struct platform_device *dsi_get_dsidev_from_id(int module);
 341 #else
 342 static inline int dsi_runtime_get(struct platform_device *dsidev)
 343 {
 344         return 0;
 345 }
 346 static inline void dsi_runtime_put(struct platform_device *dsidev)
 347 {
 348 }
 349 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 350 {
 351         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 352         return 0;
 353 }
 354 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 355 {
 356         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 357         return 0;
 358 }
 359 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 360                 struct dsi_clock_info *cinfo)
 361 {
 362         WARN("%s: DSI not compiled in\n", __func__);
 363         return -ENODEV;
 364 }
 365 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 366                 unsigned long req_pck,
 367                 struct dsi_clock_info *dsi_cinfo,
 368                 struct dispc_clock_info *dispc_cinfo)
 369 {
 370         WARN("%s: DSI not compiled in\n", __func__);
 371         return -ENODEV;
 372 }
 373 static inline int dsi_pll_init(struct platform_device *dsidev,
 374                 bool enable_hsclk, bool enable_hsdiv)
 375 {
 376         WARN("%s: DSI not compiled in\n", __func__);
 377         return -ENODEV;
 378 }
 379 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 380                 bool disconnect_lanes)
 381 {
 382 }
 383 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 384 {
 385 }
 386 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 387 {
 388 }
 389 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 390 {
 391         return NULL;
 392 }
 393 #endif
 394
 395 /* DPI */
 396 int dpi_init_platform_driver(void) __init;
 397 void dpi_uninit_platform_driver(void) __exit;
 398
 399 /* DISPC */
 400 int dispc_init_platform_driver(void) __init;
 401 void dispc_uninit_platform_driver(void) __exit;
 402 void dispc_dump_clocks(struct seq_file *s);
 403 u32 dispc_read_irqstatus(void);
 404 void dispc_clear_irqstatus(u32 mask);
 405 u32 dispc_read_irqenable(void);
 406 void dispc_write_irqenable(u32 mask);
 407
 408 int dispc_runtime_get(void);
 409 void dispc_runtime_put(void);
 410
 411 void dispc_enable_sidle(void);
 412 void dispc_disable_sidle(void);
 413
 414 void dispc_lcd_enable_signal(bool enable);
 415 void dispc_pck_free_enable(bool enable);
 416 void dispc_enable_fifomerge(bool enable);
 417 void dispc_enable_gamma_table(bool enable);
 418 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 419
 420 bool dispc_mgr_timings_ok(enum omap_channel channel,
 421                 const struct omap_video_timings *timings);
 422 unsigned long dispc_fclk_rate(void);
 423 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
 424                 struct dispc_clock_info *cinfo);
 425 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 426                 struct dispc_clock_info *cinfo);
 427
 428
 429 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 430 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 431                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 432                 bool manual_update);
 433 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
 434                 bool replication, const struct omap_video_timings *mgr_timings,
 435                 bool mem_to_mem);
 436 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 437 bool dispc_ovl_enabled(enum omap_plane plane);
 438 void dispc_ovl_set_channel_out(enum omap_plane plane,
 439                 enum omap_channel channel);
 440
 441 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
 442 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
 443 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
 444 bool dispc_mgr_go_busy(enum omap_channel channel);
 445 void dispc_mgr_go(enum omap_channel channel);
 446 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 447 bool dispc_mgr_is_enabled(enum omap_channel channel);
 448 void dispc_mgr_enable_sync(enum omap_channel channel);
 449 void dispc_mgr_disable_sync(enum omap_channel channel);
 450 void dispc_mgr_set_lcd_config(enum omap_channel channel,
 451                 const struct dss_lcd_mgr_config *config);
 452 void dispc_mgr_set_timings(enum omap_channel channel,
 453                 const struct omap_video_timings *timings);
 454 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 455 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 456 unsigned long dispc_core_clk_rate(void);
 457 void dispc_mgr_set_clock_div(enum omap_channel channel,
 458                 const struct dispc_clock_info *cinfo);
 459 int dispc_mgr_get_clock_div(enum omap_channel channel,
 460                 struct dispc_clock_info *cinfo);
 461 void dispc_mgr_setup(enum omap_channel channel,
 462                 const struct omap_overlay_manager_info *info);
 463
 464 u32 dispc_wb_get_framedone_irq(void);
 465 bool dispc_wb_go_busy(void);
 466 void dispc_wb_go(void);
 467 void dispc_wb_enable(bool enable);
 468 bool dispc_wb_is_enabled(void);
 469 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 470 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 471                 bool mem_to_mem, const struct omap_video_timings *timings);
 472
 473 /* VENC */
 474 #ifdef CONFIG_OMAP2_DSS_VENC
 475 int venc_init_platform_driver(void) __init;
 476 void venc_uninit_platform_driver(void) __exit;
 477 unsigned long venc_get_pixel_clock(void);
 478 #else
 479 static inline unsigned long venc_get_pixel_clock(void)
 480 {
 481         WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
 482         return 0;
 483 }
 484 #endif
 485 int omapdss_venc_display_enable(struct omap_dss_device *dssdev);
 486 void omapdss_venc_display_disable(struct omap_dss_device *dssdev);
 487 void omapdss_venc_set_timings(struct omap_dss_device *dssdev,
 488                 struct omap_video_timings *timings);
 489 int omapdss_venc_check_timings(struct omap_dss_device *dssdev,
 490                 struct omap_video_timings *timings);
 491 u32 omapdss_venc_get_wss(struct omap_dss_device *dssdev);
 492 int omapdss_venc_set_wss(struct omap_dss_device *dssdev, u32 wss);
 493 void omapdss_venc_set_type(struct omap_dss_device *dssdev,
 494                 enum omap_dss_venc_type type);
 495 void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
 496                 bool invert_polarity);
 497 int venc_panel_init(void);
 498 void venc_panel_exit(void);
 499
 500 /* HDMI */
 501 #ifdef CONFIG_OMAP4_DSS_HDMI
 502 int hdmi_init_platform_driver(void) __init;
 503 void hdmi_uninit_platform_driver(void) __exit;
 504 unsigned long hdmi_get_pixel_clock(void);
 505 #else
 506 static inline unsigned long hdmi_get_pixel_clock(void)
 507 {
 508         WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
 509         return 0;
 510 }
 511 #endif
 512 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 513 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 514 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev);
 515 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev);
 516 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
 517                 struct omap_video_timings *timings);
 518 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 519                                         struct omap_video_timings *timings);
 520 int omapdss_hdmi_read_edid(u8 *buf, int len);
 521 bool omapdss_hdmi_detect(void);
 522 int hdmi_panel_init(void);
 523 void hdmi_panel_exit(void);
 524 #ifdef CONFIG_OMAP4_DSS_HDMI_AUDIO
 525 int hdmi_audio_enable(void);
 526 void hdmi_audio_disable(void);
 527 int hdmi_audio_start(void);
 528 void hdmi_audio_stop(void);
 529 bool hdmi_mode_has_audio(void);
 530 int hdmi_audio_config(struct omap_dss_audio *audio);
 531 #endif
 532
 533 /* RFBI */
 534 int rfbi_init_platform_driver(void) __init;
 535 void rfbi_uninit_platform_driver(void) __exit;
 536
 537
 538 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 539 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 540 {
 541         int b;
 542         for (b = 0; b < 32; ++b) {
 543                 if (irqstatus & (1 << b))
 544                         irq_arr[b]++;
 545         }
 546 }
 547 #endif
 548
 549 #endif