drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47
  48 #define DSI_CATCH_MISSING_TE
  49
  50 struct dsi_reg { u16 idx; };
  51
  52 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  53
  54 #define DSI_SZ_REGS             SZ_1K
  55 /* DSI Protocol Engine */
  56
  57 #define DSI_REVISION                    DSI_REG(0x0000)
  58 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  59 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  60 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  61 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  62 #define DSI_CTRL                        DSI_REG(0x0040)
  63 #define DSI_GNQ                         DSI_REG(0x0044)
  64 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  65 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  66 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  67 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  68 #define DSI_TIMING1                     DSI_REG(0x0058)
  69 #define DSI_TIMING2                     DSI_REG(0x005C)
  70 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  71 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  72 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  73 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  74 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  75 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  76 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  77 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  78 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  79 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  80 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  81 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  82 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  83 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  84 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  85 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  86 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  87 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  88 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  89 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  90 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  91
  92 /* DSIPHY_SCP */
  93
  94 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  95 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  96 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  97 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
  98 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
  99
 100 /* DSI_PLL_CTRL_SCP */
 101
 102 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 103 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 104 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 105 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 106 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 107
 108 #define REG_GET(dsidev, idx, start, end) \
 109         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 110
 111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 112         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 113
 114 /* Global interrupts */
 115 #define DSI_IRQ_VC0             (1 << 0)
 116 #define DSI_IRQ_VC1             (1 << 1)
 117 #define DSI_IRQ_VC2             (1 << 2)
 118 #define DSI_IRQ_VC3             (1 << 3)
 119 #define DSI_IRQ_WAKEUP          (1 << 4)
 120 #define DSI_IRQ_RESYNC          (1 << 5)
 121 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 122 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 123 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 124 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 125 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 126 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 127 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 128 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 129 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 130 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 131 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 132 #define DSI_IRQ_ERROR_MASK \
 133         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 134         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 135 #define DSI_IRQ_CHANNEL_MASK    0xf
 136
 137 /* Virtual channel interrupts */
 138 #define DSI_VC_IRQ_CS           (1 << 0)
 139 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 140 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 141 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 142 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 143 #define DSI_VC_IRQ_BTA          (1 << 5)
 144 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 145 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 147 #define DSI_VC_IRQ_ERROR_MASK \
 148         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 149         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 150         DSI_VC_IRQ_FIFO_TX_UDF)
 151
 152 /* ComplexIO interrupts */
 153 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 154 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 155 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 156 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 157 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 158 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 159 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 160 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 161 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 162 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 163 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 164 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 165 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 166 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 167 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 168 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 169 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 170 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 171 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 172 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 185 #define DSI_CIO_IRQ_ERROR_MASK \
 186         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 187          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 188          DSI_CIO_IRQ_ERRSYNCESC5 | \
 189          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 190          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 191          DSI_CIO_IRQ_ERRESC5 | \
 192          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 193          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 194          DSI_CIO_IRQ_ERRCONTROL5 | \
 195          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 196          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 200
 201 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 202
 203 #define DSI_MAX_NR_ISRS                2
 204 #define DSI_MAX_NR_LANES        5
 205
 206 enum dsi_lane_function {
 207         DSI_LANE_UNUSED = 0,
 208         DSI_LANE_CLK,
 209         DSI_LANE_DATA1,
 210         DSI_LANE_DATA2,
 211         DSI_LANE_DATA3,
 212         DSI_LANE_DATA4,
 213 };
 214
 215 struct dsi_lane_config {
 216         enum dsi_lane_function function;
 217         u8 polarity;
 218 };
 219
 220 struct dsi_isr_data {
 221         omap_dsi_isr_t  isr;
 222         void            *arg;
 223         u32             mask;
 224 };
 225
 226 enum fifo_size {
 227         DSI_FIFO_SIZE_0         = 0,
 228         DSI_FIFO_SIZE_32        = 1,
 229         DSI_FIFO_SIZE_64        = 2,
 230         DSI_FIFO_SIZE_96        = 3,
 231         DSI_FIFO_SIZE_128       = 4,
 232 };
 233
 234 enum dsi_vc_source {
 235         DSI_VC_SOURCE_L4 = 0,
 236         DSI_VC_SOURCE_VP,
 237 };
 238
 239 struct dsi_irq_stats {
 240         unsigned long last_reset;
 241         unsigned irq_count;
 242         unsigned dsi_irqs[32];
 243         unsigned vc_irqs[4][32];
 244         unsigned cio_irqs[32];
 245 };
 246
 247 struct dsi_isr_tables {
 248         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 249         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 250         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 251 };
 252
 253 struct dsi_data {
 254         struct platform_device *pdev;
 255         void __iomem    *base;
 256
 257         int module_id;
 258
 259         int irq;
 260
 261         struct clk *dss_clk;
 262         struct clk *sys_clk;
 263
 264         struct dsi_clock_info current_cinfo;
 265
 266         bool vdds_dsi_enabled;
 267         struct regulator *vdds_dsi_reg;
 268
 269         struct {
 270                 enum dsi_vc_source source;
 271                 struct omap_dss_device *dssdev;
 272                 enum fifo_size fifo_size;
 273                 int vc_id;
 274         } vc[4];
 275
 276         struct mutex lock;
 277         struct semaphore bus_lock;
 278
 279         unsigned pll_locked;
 280
 281         spinlock_t irq_lock;
 282         struct dsi_isr_tables isr_tables;
 283         /* space for a copy used by the interrupt handler */
 284         struct dsi_isr_tables isr_tables_copy;
 285
 286         int update_channel;
 287 #ifdef DEBUG
 288         unsigned update_bytes;
 289 #endif
 290
 291         bool te_enabled;
 292         bool ulps_enabled;
 293
 294         void (*framedone_callback)(int, void *);
 295         void *framedone_data;
 296
 297         struct delayed_work framedone_timeout_work;
 298
 299 #ifdef DSI_CATCH_MISSING_TE
 300         struct timer_list te_timer;
 301 #endif
 302
 303         unsigned long cache_req_pck;
 304         unsigned long cache_clk_freq;
 305         struct dsi_clock_info cache_cinfo;
 306
 307         u32             errors;
 308         spinlock_t      errors_lock;
 309 #ifdef DEBUG
 310         ktime_t perf_setup_time;
 311         ktime_t perf_start_time;
 312 #endif
 313         int debug_read;
 314         int debug_write;
 315
 316 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 317         spinlock_t irq_stats_lock;
 318         struct dsi_irq_stats irq_stats;
 319 #endif
 320         /* DSI PLL Parameter Ranges */
 321         unsigned long regm_max, regn_max;
 322         unsigned long  regm_dispc_max, regm_dsi_max;
 323         unsigned long  fint_min, fint_max;
 324         unsigned long lpdiv_max;
 325
 326         unsigned num_lanes_supported;
 327
 328         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 329         unsigned num_lanes_used;
 330
 331         unsigned scp_clk_refcount;
 332
 333         struct dss_lcd_mgr_config mgr_config;
 334         struct omap_video_timings timings;
 335         enum omap_dss_dsi_pixel_format pix_fmt;
 336         enum omap_dss_dsi_mode mode;
 337         struct omap_dss_dsi_videomode_timings vm_timings;
 338
 339         struct omap_dss_output output;
 340 };
 341
 342 struct dsi_packet_sent_handler_data {
 343         struct platform_device *dsidev;
 344         struct completion *completion;
 345 };
 346
 347 #ifdef DEBUG
 348 static bool dsi_perf;
 349 module_param(dsi_perf, bool, 0644);
 350 #endif
 351
 352 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 353 {
 354         return dev_get_drvdata(&dsidev->dev);
 355 }
 356
 357 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 358 {
 359         return dssdev->output->pdev;
 360 }
 361
 362 struct platform_device *dsi_get_dsidev_from_id(int module)
 363 {
 364         struct omap_dss_output *out;
 365         enum omap_dss_output_id id;
 366
 367         switch (module) {
 368         case 0:
 369                 id = OMAP_DSS_OUTPUT_DSI1;
 370                 break;
 371         case 1:
 372                 id = OMAP_DSS_OUTPUT_DSI2;
 373                 break;
 374         default:
 375                 return NULL;
 376         }
 377
 378         out = omap_dss_get_output(id);
 379
 380         return out ? out->pdev : NULL;
 381 }
 382
 383 static inline void dsi_write_reg(struct platform_device *dsidev,
 384                 const struct dsi_reg idx, u32 val)
 385 {
 386         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 387
 388         __raw_writel(val, dsi->base + idx.idx);
 389 }
 390
 391 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 392                 const struct dsi_reg idx)
 393 {
 394         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 395
 396         return __raw_readl(dsi->base + idx.idx);
 397 }
 398
 399 void dsi_bus_lock(struct omap_dss_device *dssdev)
 400 {
 401         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 402         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 403
 404         down(&dsi->bus_lock);
 405 }
 406 EXPORT_SYMBOL(dsi_bus_lock);
 407
 408 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 409 {
 410         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 411         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 412
 413         up(&dsi->bus_lock);
 414 }
 415 EXPORT_SYMBOL(dsi_bus_unlock);
 416
 417 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 418 {
 419         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 420
 421         return dsi->bus_lock.count == 0;
 422 }
 423
 424 static void dsi_completion_handler(void *data, u32 mask)
 425 {
 426         complete((struct completion *)data);
 427 }
 428
 429 static inline int wait_for_bit_change(struct platform_device *dsidev,
 430                 const struct dsi_reg idx, int bitnum, int value)
 431 {
 432         unsigned long timeout;
 433         ktime_t wait;
 434         int t;
 435
 436         /* first busyloop to see if the bit changes right away */
 437         t = 100;
 438         while (t-- > 0) {
 439                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 440                         return value;
 441         }
 442
 443         /* then loop for 500ms, sleeping for 1ms in between */
 444         timeout = jiffies + msecs_to_jiffies(500);
 445         while (time_before(jiffies, timeout)) {
 446                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 447                         return value;
 448
 449                 wait = ns_to_ktime(1000 * 1000);
 450                 set_current_state(TASK_UNINTERRUPTIBLE);
 451                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 452         }
 453
 454         return !value;
 455 }
 456
 457 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 458 {
 459         switch (fmt) {
 460         case OMAP_DSS_DSI_FMT_RGB888:
 461         case OMAP_DSS_DSI_FMT_RGB666:
 462                 return 24;
 463         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 464                 return 18;
 465         case OMAP_DSS_DSI_FMT_RGB565:
 466                 return 16;
 467         default:
 468                 BUG();
 469                 return 0;
 470         }
 471 }
 472
 473 #ifdef DEBUG
 474 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 475 {
 476         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 477         dsi->perf_setup_time = ktime_get();
 478 }
 479
 480 static void dsi_perf_mark_start(struct platform_device *dsidev)
 481 {
 482         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 483         dsi->perf_start_time = ktime_get();
 484 }
 485
 486 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 487 {
 488         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 489         ktime_t t, setup_time, trans_time;
 490         u32 total_bytes;
 491         u32 setup_us, trans_us, total_us;
 492
 493         if (!dsi_perf)
 494                 return;
 495
 496         t = ktime_get();
 497
 498         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 499         setup_us = (u32)ktime_to_us(setup_time);
 500         if (setup_us == 0)
 501                 setup_us = 1;
 502
 503         trans_time = ktime_sub(t, dsi->perf_start_time);
 504         trans_us = (u32)ktime_to_us(trans_time);
 505         if (trans_us == 0)
 506                 trans_us = 1;
 507
 508         total_us = setup_us + trans_us;
 509
 510         total_bytes = dsi->update_bytes;
 511
 512         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 513                         "%u bytes, %u kbytes/sec\n",
 514                         name,
 515                         setup_us,
 516                         trans_us,
 517                         total_us,
 518                         1000*1000 / total_us,
 519                         total_bytes,
 520                         total_bytes * 1000 / total_us);
 521 }
 522 #else
 523 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 524 {
 525 }
 526
 527 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 528 {
 529 }
 530
 531 static inline void dsi_perf_show(struct platform_device *dsidev,
 532                 const char *name)
 533 {
 534 }
 535 #endif
 536
 537 static int verbose_irq;
 538
 539 static void print_irq_status(u32 status)
 540 {
 541         if (status == 0)
 542                 return;
 543
 544         if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 545                 return;
 546
 547 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
 548
 549         pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 550                 status,
 551                 verbose_irq ? PIS(VC0) : "",
 552                 verbose_irq ? PIS(VC1) : "",
 553                 verbose_irq ? PIS(VC2) : "",
 554                 verbose_irq ? PIS(VC3) : "",
 555                 PIS(WAKEUP),
 556                 PIS(RESYNC),
 557                 PIS(PLL_LOCK),
 558                 PIS(PLL_UNLOCK),
 559                 PIS(PLL_RECALL),
 560                 PIS(COMPLEXIO_ERR),
 561                 PIS(HS_TX_TIMEOUT),
 562                 PIS(LP_RX_TIMEOUT),
 563                 PIS(TE_TRIGGER),
 564                 PIS(ACK_TRIGGER),
 565                 PIS(SYNC_LOST),
 566                 PIS(LDO_POWER_GOOD),
 567                 PIS(TA_TIMEOUT));
 568 #undef PIS
 569 }
 570
 571 static void print_irq_status_vc(int channel, u32 status)
 572 {
 573         if (status == 0)
 574                 return;
 575
 576         if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 577                 return;
 578
 579 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
 580
 581         pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
 582                 channel,
 583                 status,
 584                 PIS(CS),
 585                 PIS(ECC_CORR),
 586                 PIS(ECC_NO_CORR),
 587                 verbose_irq ? PIS(PACKET_SENT) : "",
 588                 PIS(BTA),
 589                 PIS(FIFO_TX_OVF),
 590                 PIS(FIFO_RX_OVF),
 591                 PIS(FIFO_TX_UDF),
 592                 PIS(PP_BUSY_CHANGE));
 593 #undef PIS
 594 }
 595
 596 static void print_irq_status_cio(u32 status)
 597 {
 598         if (status == 0)
 599                 return;
 600
 601 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
 602
 603         pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 604                 status,
 605                 PIS(ERRSYNCESC1),
 606                 PIS(ERRSYNCESC2),
 607                 PIS(ERRSYNCESC3),
 608                 PIS(ERRESC1),
 609                 PIS(ERRESC2),
 610                 PIS(ERRESC3),
 611                 PIS(ERRCONTROL1),
 612                 PIS(ERRCONTROL2),
 613                 PIS(ERRCONTROL3),
 614                 PIS(STATEULPS1),
 615                 PIS(STATEULPS2),
 616                 PIS(STATEULPS3),
 617                 PIS(ERRCONTENTIONLP0_1),
 618                 PIS(ERRCONTENTIONLP1_1),
 619                 PIS(ERRCONTENTIONLP0_2),
 620                 PIS(ERRCONTENTIONLP1_2),
 621                 PIS(ERRCONTENTIONLP0_3),
 622                 PIS(ERRCONTENTIONLP1_3),
 623                 PIS(ULPSACTIVENOT_ALL0),
 624                 PIS(ULPSACTIVENOT_ALL1));
 625 #undef PIS
 626 }
 627
 628 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 629 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 630                 u32 *vcstatus, u32 ciostatus)
 631 {
 632         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 633         int i;
 634
 635         spin_lock(&dsi->irq_stats_lock);
 636
 637         dsi->irq_stats.irq_count++;
 638         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 639
 640         for (i = 0; i < 4; ++i)
 641                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 642
 643         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 644
 645         spin_unlock(&dsi->irq_stats_lock);
 646 }
 647 #else
 648 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 649 #endif
 650
 651 static int debug_irq;
 652
 653 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 654                 u32 *vcstatus, u32 ciostatus)
 655 {
 656         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 657         int i;
 658
 659         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 660                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 661                 print_irq_status(irqstatus);
 662                 spin_lock(&dsi->errors_lock);
 663                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 664                 spin_unlock(&dsi->errors_lock);
 665         } else if (debug_irq) {
 666                 print_irq_status(irqstatus);
 667         }
 668
 669         for (i = 0; i < 4; ++i) {
 670                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 671                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 672                                        i, vcstatus[i]);
 673                         print_irq_status_vc(i, vcstatus[i]);
 674                 } else if (debug_irq) {
 675                         print_irq_status_vc(i, vcstatus[i]);
 676                 }
 677         }
 678
 679         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 680                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 681                 print_irq_status_cio(ciostatus);
 682         } else if (debug_irq) {
 683                 print_irq_status_cio(ciostatus);
 684         }
 685 }
 686
 687 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 688                 unsigned isr_array_size, u32 irqstatus)
 689 {
 690         struct dsi_isr_data *isr_data;
 691         int i;
 692
 693         for (i = 0; i < isr_array_size; i++) {
 694                 isr_data = &isr_array[i];
 695                 if (isr_data->isr && isr_data->mask & irqstatus)
 696                         isr_data->isr(isr_data->arg, irqstatus);
 697         }
 698 }
 699
 700 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 701                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 702 {
 703         int i;
 704
 705         dsi_call_isrs(isr_tables->isr_table,
 706                         ARRAY_SIZE(isr_tables->isr_table),
 707                         irqstatus);
 708
 709         for (i = 0; i < 4; ++i) {
 710                 if (vcstatus[i] == 0)
 711                         continue;
 712                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 713                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 714                                 vcstatus[i]);
 715         }
 716
 717         if (ciostatus != 0)
 718                 dsi_call_isrs(isr_tables->isr_table_cio,
 719                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 720                                 ciostatus);
 721 }
 722
 723 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 724 {
 725         struct platform_device *dsidev;
 726         struct dsi_data *dsi;
 727         u32 irqstatus, vcstatus[4], ciostatus;
 728         int i;
 729
 730         dsidev = (struct platform_device *) arg;
 731         dsi = dsi_get_dsidrv_data(dsidev);
 732
 733         spin_lock(&dsi->irq_lock);
 734
 735         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 736
 737         /* IRQ is not for us */
 738         if (!irqstatus) {
 739                 spin_unlock(&dsi->irq_lock);
 740                 return IRQ_NONE;
 741         }
 742
 743         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 744         /* flush posted write */
 745         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 746
 747         for (i = 0; i < 4; ++i) {
 748                 if ((irqstatus & (1 << i)) == 0) {
 749                         vcstatus[i] = 0;
 750                         continue;
 751                 }
 752
 753                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 754
 755                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 756                 /* flush posted write */
 757                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 758         }
 759
 760         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 761                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 762
 763                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 764                 /* flush posted write */
 765                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 766         } else {
 767                 ciostatus = 0;
 768         }
 769
 770 #ifdef DSI_CATCH_MISSING_TE
 771         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 772                 del_timer(&dsi->te_timer);
 773 #endif
 774
 775         /* make a copy and unlock, so that isrs can unregister
 776          * themselves */
 777         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 778                 sizeof(dsi->isr_tables));
 779
 780         spin_unlock(&dsi->irq_lock);
 781
 782         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 783
 784         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 785
 786         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 787
 788         return IRQ_HANDLED;
 789 }
 790
 791 /* dsi->irq_lock has to be locked by the caller */
 792 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 793                 struct dsi_isr_data *isr_array,
 794                 unsigned isr_array_size, u32 default_mask,
 795                 const struct dsi_reg enable_reg,
 796                 const struct dsi_reg status_reg)
 797 {
 798         struct dsi_isr_data *isr_data;
 799         u32 mask;
 800         u32 old_mask;
 801         int i;
 802
 803         mask = default_mask;
 804
 805         for (i = 0; i < isr_array_size; i++) {
 806                 isr_data = &isr_array[i];
 807
 808                 if (isr_data->isr == NULL)
 809                         continue;
 810
 811                 mask |= isr_data->mask;
 812         }
 813
 814         old_mask = dsi_read_reg(dsidev, enable_reg);
 815         /* clear the irqstatus for newly enabled irqs */
 816         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 817         dsi_write_reg(dsidev, enable_reg, mask);
 818
 819         /* flush posted writes */
 820         dsi_read_reg(dsidev, enable_reg);
 821         dsi_read_reg(dsidev, status_reg);
 822 }
 823
 824 /* dsi->irq_lock has to be locked by the caller */
 825 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 826 {
 827         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 828         u32 mask = DSI_IRQ_ERROR_MASK;
 829 #ifdef DSI_CATCH_MISSING_TE
 830         mask |= DSI_IRQ_TE_TRIGGER;
 831 #endif
 832         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 833                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 834                         DSI_IRQENABLE, DSI_IRQSTATUS);
 835 }
 836
 837 /* dsi->irq_lock has to be locked by the caller */
 838 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 839 {
 840         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 841
 842         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 843                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 844                         DSI_VC_IRQ_ERROR_MASK,
 845                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 846 }
 847
 848 /* dsi->irq_lock has to be locked by the caller */
 849 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 850 {
 851         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 852
 853         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 854                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 855                         DSI_CIO_IRQ_ERROR_MASK,
 856                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 857 }
 858
 859 static void _dsi_initialize_irq(struct platform_device *dsidev)
 860 {
 861         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 862         unsigned long flags;
 863         int vc;
 864
 865         spin_lock_irqsave(&dsi->irq_lock, flags);
 866
 867         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 868
 869         _omap_dsi_set_irqs(dsidev);
 870         for (vc = 0; vc < 4; ++vc)
 871                 _omap_dsi_set_irqs_vc(dsidev, vc);
 872         _omap_dsi_set_irqs_cio(dsidev);
 873
 874         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 875 }
 876
 877 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 878                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 879 {
 880         struct dsi_isr_data *isr_data;
 881         int free_idx;
 882         int i;
 883
 884         BUG_ON(isr == NULL);
 885
 886         /* check for duplicate entry and find a free slot */
 887         free_idx = -1;
 888         for (i = 0; i < isr_array_size; i++) {
 889                 isr_data = &isr_array[i];
 890
 891                 if (isr_data->isr == isr && isr_data->arg == arg &&
 892                                 isr_data->mask == mask) {
 893                         return -EINVAL;
 894                 }
 895
 896                 if (isr_data->isr == NULL && free_idx == -1)
 897                         free_idx = i;
 898         }
 899
 900         if (free_idx == -1)
 901                 return -EBUSY;
 902
 903         isr_data = &isr_array[free_idx];
 904         isr_data->isr = isr;
 905         isr_data->arg = arg;
 906         isr_data->mask = mask;
 907
 908         return 0;
 909 }
 910
 911 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 912                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 913 {
 914         struct dsi_isr_data *isr_data;
 915         int i;
 916
 917         for (i = 0; i < isr_array_size; i++) {
 918                 isr_data = &isr_array[i];
 919                 if (isr_data->isr != isr || isr_data->arg != arg ||
 920                                 isr_data->mask != mask)
 921                         continue;
 922
 923                 isr_data->isr = NULL;
 924                 isr_data->arg = NULL;
 925                 isr_data->mask = 0;
 926
 927                 return 0;
 928         }
 929
 930         return -EINVAL;
 931 }
 932
 933 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 934                 void *arg, u32 mask)
 935 {
 936         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 937         unsigned long flags;
 938         int r;
 939
 940         spin_lock_irqsave(&dsi->irq_lock, flags);
 941
 942         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 943                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 944
 945         if (r == 0)
 946                 _omap_dsi_set_irqs(dsidev);
 947
 948         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 949
 950         return r;
 951 }
 952
 953 static int dsi_unregister_isr(struct platform_device *dsidev,
 954                 omap_dsi_isr_t isr, void *arg, u32 mask)
 955 {
 956         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 957         unsigned long flags;
 958         int r;
 959
 960         spin_lock_irqsave(&dsi->irq_lock, flags);
 961
 962         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 963                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 964
 965         if (r == 0)
 966                 _omap_dsi_set_irqs(dsidev);
 967
 968         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 969
 970         return r;
 971 }
 972
 973 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 974                 omap_dsi_isr_t isr, void *arg, u32 mask)
 975 {
 976         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 977         unsigned long flags;
 978         int r;
 979
 980         spin_lock_irqsave(&dsi->irq_lock, flags);
 981
 982         r = _dsi_register_isr(isr, arg, mask,
 983                         dsi->isr_tables.isr_table_vc[channel],
 984                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 985
 986         if (r == 0)
 987                 _omap_dsi_set_irqs_vc(dsidev, channel);
 988
 989         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 990
 991         return r;
 992 }
 993
 994 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 995                 omap_dsi_isr_t isr, void *arg, u32 mask)
 996 {
 997         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 998         unsigned long flags;
 999         int r;
1000
1001         spin_lock_irqsave(&dsi->irq_lock, flags);
1002
1003         r = _dsi_unregister_isr(isr, arg, mask,
1004                         dsi->isr_tables.isr_table_vc[channel],
1005                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1006
1007         if (r == 0)
1008                 _omap_dsi_set_irqs_vc(dsidev, channel);
1009
1010         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1011
1012         return r;
1013 }
1014
1015 static int dsi_register_isr_cio(struct platform_device *dsidev,
1016                 omap_dsi_isr_t isr, void *arg, u32 mask)
1017 {
1018         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1019         unsigned long flags;
1020         int r;
1021
1022         spin_lock_irqsave(&dsi->irq_lock, flags);
1023
1024         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1025                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1026
1027         if (r == 0)
1028                 _omap_dsi_set_irqs_cio(dsidev);
1029
1030         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1031
1032         return r;
1033 }
1034
1035 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1036                 omap_dsi_isr_t isr, void *arg, u32 mask)
1037 {
1038         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1039         unsigned long flags;
1040         int r;
1041
1042         spin_lock_irqsave(&dsi->irq_lock, flags);
1043
1044         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1045                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1046
1047         if (r == 0)
1048                 _omap_dsi_set_irqs_cio(dsidev);
1049
1050         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1051
1052         return r;
1053 }
1054
1055 static u32 dsi_get_errors(struct platform_device *dsidev)
1056 {
1057         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1058         unsigned long flags;
1059         u32 e;
1060         spin_lock_irqsave(&dsi->errors_lock, flags);
1061         e = dsi->errors;
1062         dsi->errors = 0;
1063         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1064         return e;
1065 }
1066
1067 int dsi_runtime_get(struct platform_device *dsidev)
1068 {
1069         int r;
1070         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1071
1072         DSSDBG("dsi_runtime_get\n");
1073
1074         r = pm_runtime_get_sync(&dsi->pdev->dev);
1075         WARN_ON(r < 0);
1076         return r < 0 ? r : 0;
1077 }
1078
1079 void dsi_runtime_put(struct platform_device *dsidev)
1080 {
1081         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1082         int r;
1083
1084         DSSDBG("dsi_runtime_put\n");
1085
1086         r = pm_runtime_put_sync(&dsi->pdev->dev);
1087         WARN_ON(r < 0 && r != -ENOSYS);
1088 }
1089
1090 /* source clock for DSI PLL. this could also be PCLKFREE */
1091 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1092                 bool enable)
1093 {
1094         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1095
1096         if (enable)
1097                 clk_prepare_enable(dsi->sys_clk);
1098         else
1099                 clk_disable_unprepare(dsi->sys_clk);
1100
1101         if (enable && dsi->pll_locked) {
1102                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1103                         DSSERR("cannot lock PLL when enabling clocks\n");
1104         }
1105 }
1106
1107 static void _dsi_print_reset_status(struct platform_device *dsidev)
1108 {
1109         u32 l;
1110         int b0, b1, b2;
1111
1112         /* A dummy read using the SCP interface to any DSIPHY register is
1113          * required after DSIPHY reset to complete the reset of the DSI complex
1114          * I/O. */
1115         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1116
1117         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1118                 b0 = 28;
1119                 b1 = 27;
1120                 b2 = 26;
1121         } else {
1122                 b0 = 24;
1123                 b1 = 25;
1124                 b2 = 26;
1125         }
1126
1127 #define DSI_FLD_GET(fld, start, end)\
1128         FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1129
1130         pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1131                 DSI_FLD_GET(PLL_STATUS, 0, 0),
1132                 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1133                 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1134                 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1135                 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1136                 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1137                 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1138                 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1139
1140 #undef DSI_FLD_GET
1141 }
1142
1143 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1144 {
1145         DSSDBG("dsi_if_enable(%d)\n", enable);
1146
1147         enable = enable ? 1 : 0;
1148         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1149
1150         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1151                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1152                         return -EIO;
1153         }
1154
1155         return 0;
1156 }
1157
1158 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1159 {
1160         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1161
1162         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1163 }
1164
1165 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1166 {
1167         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1168
1169         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1170 }
1171
1172 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1173 {
1174         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1175
1176         return dsi->current_cinfo.clkin4ddr / 16;
1177 }
1178
1179 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1180 {
1181         unsigned long r;
1182         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1183
1184         if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1185                 /* DSI FCLK source is DSS_CLK_FCK */
1186                 r = clk_get_rate(dsi->dss_clk);
1187         } else {
1188                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1189                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1190         }
1191
1192         return r;
1193 }
1194
1195 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1196 {
1197         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1198         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1199         unsigned long dsi_fclk;
1200         unsigned lp_clk_div;
1201         unsigned long lp_clk;
1202
1203         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1204
1205         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1206                 return -EINVAL;
1207
1208         dsi_fclk = dsi_fclk_rate(dsidev);
1209
1210         lp_clk = dsi_fclk / 2 / lp_clk_div;
1211
1212         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1213         dsi->current_cinfo.lp_clk = lp_clk;
1214         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1215
1216         /* LP_CLK_DIVISOR */
1217         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1218
1219         /* LP_RX_SYNCHRO_ENABLE */
1220         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1221
1222         return 0;
1223 }
1224
1225 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1226 {
1227         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1228
1229         if (dsi->scp_clk_refcount++ == 0)
1230                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1231 }
1232
1233 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1234 {
1235         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1236
1237         WARN_ON(dsi->scp_clk_refcount == 0);
1238         if (--dsi->scp_clk_refcount == 0)
1239                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1240 }
1241
1242 enum dsi_pll_power_state {
1243         DSI_PLL_POWER_OFF       = 0x0,
1244         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1245         DSI_PLL_POWER_ON_ALL    = 0x2,
1246         DSI_PLL_POWER_ON_DIV    = 0x3,
1247 };
1248
1249 static int dsi_pll_power(struct platform_device *dsidev,
1250                 enum dsi_pll_power_state state)
1251 {
1252         int t = 0;
1253
1254         /* DSI-PLL power command 0x3 is not working */
1255         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1256                         state == DSI_PLL_POWER_ON_DIV)
1257                 state = DSI_PLL_POWER_ON_ALL;
1258
1259         /* PLL_PWR_CMD */
1260         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1261
1262         /* PLL_PWR_STATUS */
1263         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1264                 if (++t > 1000) {
1265                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1266                                         state);
1267                         return -ENODEV;
1268                 }
1269                 udelay(1);
1270         }
1271
1272         return 0;
1273 }
1274
1275 /* calculate clock rates using dividers in cinfo */
1276 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1277                 struct dsi_clock_info *cinfo)
1278 {
1279         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1280
1281         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1282                 return -EINVAL;
1283
1284         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1285                 return -EINVAL;
1286
1287         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1288                 return -EINVAL;
1289
1290         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1291                 return -EINVAL;
1292
1293         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1294         cinfo->fint = cinfo->clkin / cinfo->regn;
1295
1296         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1297                 return -EINVAL;
1298
1299         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1300
1301         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1302                 return -EINVAL;
1303
1304         if (cinfo->regm_dispc > 0)
1305                 cinfo->dsi_pll_hsdiv_dispc_clk =
1306                         cinfo->clkin4ddr / cinfo->regm_dispc;
1307         else
1308                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1309
1310         if (cinfo->regm_dsi > 0)
1311                 cinfo->dsi_pll_hsdiv_dsi_clk =
1312                         cinfo->clkin4ddr / cinfo->regm_dsi;
1313         else
1314                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1315
1316         return 0;
1317 }
1318
1319 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1320                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1321                 struct dispc_clock_info *dispc_cinfo)
1322 {
1323         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1324         struct dsi_clock_info cur, best;
1325         struct dispc_clock_info best_dispc;
1326         int min_fck_per_pck;
1327         int match = 0;
1328         unsigned long dss_sys_clk, max_dss_fck;
1329
1330         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1331
1332         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1333
1334         if (req_pck == dsi->cache_req_pck &&
1335                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1336                 DSSDBG("DSI clock info found from cache\n");
1337                 *dsi_cinfo = dsi->cache_cinfo;
1338                 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1339                         dispc_cinfo);
1340                 return 0;
1341         }
1342
1343         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1344
1345         if (min_fck_per_pck &&
1346                 req_pck * min_fck_per_pck > max_dss_fck) {
1347                 DSSERR("Requested pixel clock not possible with the current "
1348                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1349                                 "the constraint off.\n");
1350                 min_fck_per_pck = 0;
1351         }
1352
1353         DSSDBG("dsi_pll_calc\n");
1354
1355 retry:
1356         memset(&best, 0, sizeof(best));
1357         memset(&best_dispc, 0, sizeof(best_dispc));
1358
1359         memset(&cur, 0, sizeof(cur));
1360         cur.clkin = dss_sys_clk;
1361
1362         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1363         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1364         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1365                 cur.fint = cur.clkin / cur.regn;
1366
1367                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1368                         continue;
1369
1370                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1371                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1372                         unsigned long a, b;
1373
1374                         a = 2 * cur.regm * (cur.clkin/1000);
1375                         b = cur.regn;
1376                         cur.clkin4ddr = a / b * 1000;
1377
1378                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1379                                 break;
1380
1381                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1382                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1383                         for (cur.regm_dispc = 1; cur.regm_dispc <
1384                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1385                                 struct dispc_clock_info cur_dispc;
1386                                 cur.dsi_pll_hsdiv_dispc_clk =
1387                                         cur.clkin4ddr / cur.regm_dispc;
1388
1389                                 if (cur.regm_dispc > 1 &&
1390                                                 cur.regm_dispc % 2 != 0 &&
1391                                                 req_pck >= 1000000)
1392                                         continue;
1393
1394                                 /* this will narrow down the search a bit,
1395                                  * but still give pixclocks below what was
1396                                  * requested */
1397                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1398                                         break;
1399
1400                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1401                                         continue;
1402
1403                                 if (min_fck_per_pck &&
1404                                         cur.dsi_pll_hsdiv_dispc_clk <
1405                                                 req_pck * min_fck_per_pck)
1406                                         continue;
1407
1408                                 match = 1;
1409
1410                                 dispc_find_clk_divs(req_pck,
1411                                                 cur.dsi_pll_hsdiv_dispc_clk,
1412                                                 &cur_dispc);
1413
1414                                 if (abs(cur_dispc.pck - req_pck) <
1415                                                 abs(best_dispc.pck - req_pck)) {
1416                                         best = cur;
1417                                         best_dispc = cur_dispc;
1418
1419                                         if (cur_dispc.pck == req_pck)
1420                                                 goto found;
1421                                 }
1422                         }
1423                 }
1424         }
1425 found:
1426         if (!match) {
1427                 if (min_fck_per_pck) {
1428                         DSSERR("Could not find suitable clock settings.\n"
1429                                         "Turning FCK/PCK constraint off and"
1430                                         "trying again.\n");
1431                         min_fck_per_pck = 0;
1432                         goto retry;
1433                 }
1434
1435                 DSSERR("Could not find suitable clock settings.\n");
1436
1437                 return -EINVAL;
1438         }
1439
1440         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1441         best.regm_dsi = 0;
1442         best.dsi_pll_hsdiv_dsi_clk = 0;
1443
1444         if (dsi_cinfo)
1445                 *dsi_cinfo = best;
1446         if (dispc_cinfo)
1447                 *dispc_cinfo = best_dispc;
1448
1449         dsi->cache_req_pck = req_pck;
1450         dsi->cache_clk_freq = 0;
1451         dsi->cache_cinfo = best;
1452
1453         return 0;
1454 }
1455
1456 static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
1457                 unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
1458 {
1459         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1460         struct dsi_clock_info cur, best;
1461
1462         DSSDBG("dsi_pll_calc_ddrfreq\n");
1463
1464         memset(&best, 0, sizeof(best));
1465         memset(&cur, 0, sizeof(cur));
1466
1467         cur.clkin = clk_get_rate(dsi->sys_clk);
1468
1469         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1470                 cur.fint = cur.clkin / cur.regn;
1471
1472                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1473                         continue;
1474
1475                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1476                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1477                         unsigned long a, b;
1478
1479                         a = 2 * cur.regm * (cur.clkin/1000);
1480                         b = cur.regn;
1481                         cur.clkin4ddr = a / b * 1000;
1482
1483                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1484                                 break;
1485
1486                         if (abs(cur.clkin4ddr - req_clkin4ddr) <
1487                                         abs(best.clkin4ddr - req_clkin4ddr)) {
1488                                 best = cur;
1489                                 DSSDBG("best %ld\n", best.clkin4ddr);
1490                         }
1491
1492                         if (cur.clkin4ddr == req_clkin4ddr)
1493                                 goto found;
1494                 }
1495         }
1496 found:
1497         if (cinfo)
1498                 *cinfo = best;
1499
1500         return 0;
1501 }
1502
1503 static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
1504                 struct dsi_clock_info *cinfo)
1505 {
1506         unsigned long max_dsi_fck;
1507
1508         max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1509
1510         cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1511         cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1512 }
1513
1514 static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
1515                 unsigned long req_pck, struct dsi_clock_info *cinfo,
1516                 struct dispc_clock_info *dispc_cinfo)
1517 {
1518         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1519         unsigned regm_dispc, best_regm_dispc;
1520         unsigned long dispc_clk, best_dispc_clk;
1521         int min_fck_per_pck;
1522         unsigned long max_dss_fck;
1523         struct dispc_clock_info best_dispc;
1524         bool match;
1525
1526         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1527
1528         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1529
1530         if (min_fck_per_pck &&
1531                         req_pck * min_fck_per_pck > max_dss_fck) {
1532                 DSSERR("Requested pixel clock not possible with the current "
1533                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1534                                 "the constraint off.\n");
1535                 min_fck_per_pck = 0;
1536         }
1537
1538 retry:
1539         best_regm_dispc = 0;
1540         best_dispc_clk = 0;
1541         memset(&best_dispc, 0, sizeof(best_dispc));
1542         match = false;
1543
1544         for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
1545                 struct dispc_clock_info cur_dispc;
1546
1547                 dispc_clk = cinfo->clkin4ddr / regm_dispc;
1548
1549                 /* this will narrow down the search a bit,
1550                  * but still give pixclocks below what was
1551                  * requested */
1552                 if (dispc_clk  < req_pck)
1553                         break;
1554
1555                 if (dispc_clk > max_dss_fck)
1556                         continue;
1557
1558                 if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
1559                         continue;
1560
1561                 match = true;
1562
1563                 dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
1564
1565                 if (abs(cur_dispc.pck - req_pck) <
1566                                 abs(best_dispc.pck - req_pck)) {
1567                         best_regm_dispc = regm_dispc;
1568                         best_dispc_clk = dispc_clk;
1569                         best_dispc = cur_dispc;
1570
1571                         if (cur_dispc.pck == req_pck)
1572                                 goto found;
1573                 }
1574         }
1575
1576         if (!match) {
1577                 if (min_fck_per_pck) {
1578                         DSSERR("Could not find suitable clock settings.\n"
1579                                         "Turning FCK/PCK constraint off and"
1580                                         "trying again.\n");
1581                         min_fck_per_pck = 0;
1582                         goto retry;
1583                 }
1584
1585                 DSSERR("Could not find suitable clock settings.\n");
1586
1587                 return -EINVAL;
1588         }
1589 found:
1590         cinfo->regm_dispc = best_regm_dispc;
1591         cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
1592
1593         *dispc_cinfo = best_dispc;
1594
1595         return 0;
1596 }
1597
1598 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1599                 struct dsi_clock_info *cinfo)
1600 {
1601         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1602         int r = 0;
1603         u32 l;
1604         int f = 0;
1605         u8 regn_start, regn_end, regm_start, regm_end;
1606         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1607
1608         DSSDBG("DSI PLL clock config starts");
1609
1610         dsi->current_cinfo.clkin = cinfo->clkin;
1611         dsi->current_cinfo.fint = cinfo->fint;
1612         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1613         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1614                         cinfo->dsi_pll_hsdiv_dispc_clk;
1615         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1616                         cinfo->dsi_pll_hsdiv_dsi_clk;
1617
1618         dsi->current_cinfo.regn = cinfo->regn;
1619         dsi->current_cinfo.regm = cinfo->regm;
1620         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1621         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1622
1623         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1624
1625         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1626
1627         /* DSIPHY == CLKIN4DDR */
1628         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1629                         cinfo->regm,
1630                         cinfo->regn,
1631                         cinfo->clkin,
1632                         cinfo->clkin4ddr);
1633
1634         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1635                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1636
1637         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1638
1639         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1640                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1641                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1642                 cinfo->dsi_pll_hsdiv_dispc_clk);
1643         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1644                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1645                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1646                 cinfo->dsi_pll_hsdiv_dsi_clk);
1647
1648         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1649         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1650         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1651                         &regm_dispc_end);
1652         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1653                         &regm_dsi_end);
1654
1655         /* DSI_PLL_AUTOMODE = manual */
1656         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1657
1658         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1659         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1660         /* DSI_PLL_REGN */
1661         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1662         /* DSI_PLL_REGM */
1663         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1664         /* DSI_CLOCK_DIV */
1665         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1666                         regm_dispc_start, regm_dispc_end);
1667         /* DSIPROTO_CLOCK_DIV */
1668         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1669                         regm_dsi_start, regm_dsi_end);
1670         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1671
1672         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1673
1674         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1675
1676         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1677                 f = cinfo->fint < 1000000 ? 0x3 :
1678                         cinfo->fint < 1250000 ? 0x4 :
1679                         cinfo->fint < 1500000 ? 0x5 :
1680                         cinfo->fint < 1750000 ? 0x6 :
1681                         0x7;
1682
1683                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1684         } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1685                 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1686
1687                 l = FLD_MOD(l, f, 4, 1);        /* PLL_SELFREQDCO */
1688         }
1689
1690         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1691         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1692         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1693         if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1694                 l = FLD_MOD(l, 3, 22, 21);      /* REF_SYSCLK = sysclk */
1695         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1696
1697         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1698
1699         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1700                 DSSERR("dsi pll go bit not going down.\n");
1701                 r = -EIO;
1702                 goto err;
1703         }
1704
1705         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1706                 DSSERR("cannot lock PLL\n");
1707                 r = -EIO;
1708                 goto err;
1709         }
1710
1711         dsi->pll_locked = 1;
1712
1713         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1714         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1715         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1716         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1717         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1718         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1719         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1720         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1721         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1722         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1723         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1724         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1725         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1726         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1727         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1728         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1729
1730         DSSDBG("PLL config done\n");
1731 err:
1732         return r;
1733 }
1734
1735 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1736                 bool enable_hsdiv)
1737 {
1738         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1739         int r = 0;
1740         enum dsi_pll_power_state pwstate;
1741
1742         DSSDBG("PLL init\n");
1743
1744         /*
1745          * It seems that on many OMAPs we need to enable both to have a
1746          * functional HSDivider.
1747          */
1748         enable_hsclk = enable_hsdiv = true;
1749
1750         if (dsi->vdds_dsi_reg == NULL) {
1751                 struct regulator *vdds_dsi;
1752
1753                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1754
1755                 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1756                 if (IS_ERR(vdds_dsi))
1757                         vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
1758
1759                 if (IS_ERR(vdds_dsi)) {
1760                         DSSERR("can't get VDDS_DSI regulator\n");
1761                         return PTR_ERR(vdds_dsi);
1762                 }
1763
1764                 dsi->vdds_dsi_reg = vdds_dsi;
1765         }
1766
1767         dsi_enable_pll_clock(dsidev, 1);
1768         /*
1769          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1770          */
1771         dsi_enable_scp_clk(dsidev);
1772
1773         if (!dsi->vdds_dsi_enabled) {
1774                 r = regulator_enable(dsi->vdds_dsi_reg);
1775                 if (r)
1776                         goto err0;
1777                 dsi->vdds_dsi_enabled = true;
1778         }
1779
1780         /* XXX PLL does not come out of reset without this... */
1781         dispc_pck_free_enable(1);
1782
1783         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1784                 DSSERR("PLL not coming out of reset.\n");
1785                 r = -ENODEV;
1786                 dispc_pck_free_enable(0);
1787                 goto err1;
1788         }
1789
1790         /* XXX ... but if left on, we get problems when planes do not
1791          * fill the whole display. No idea about this */
1792         dispc_pck_free_enable(0);
1793
1794         if (enable_hsclk && enable_hsdiv)
1795                 pwstate = DSI_PLL_POWER_ON_ALL;
1796         else if (enable_hsclk)
1797                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1798         else if (enable_hsdiv)
1799                 pwstate = DSI_PLL_POWER_ON_DIV;
1800         else
1801                 pwstate = DSI_PLL_POWER_OFF;
1802
1803         r = dsi_pll_power(dsidev, pwstate);
1804
1805         if (r)
1806                 goto err1;
1807
1808         DSSDBG("PLL init done\n");
1809
1810         return 0;
1811 err1:
1812         if (dsi->vdds_dsi_enabled) {
1813                 regulator_disable(dsi->vdds_dsi_reg);
1814                 dsi->vdds_dsi_enabled = false;
1815         }
1816 err0:
1817         dsi_disable_scp_clk(dsidev);
1818         dsi_enable_pll_clock(dsidev, 0);
1819         return r;
1820 }
1821
1822 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1823 {
1824         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1825
1826         dsi->pll_locked = 0;
1827         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1828         if (disconnect_lanes) {
1829                 WARN_ON(!dsi->vdds_dsi_enabled);
1830                 regulator_disable(dsi->vdds_dsi_reg);
1831                 dsi->vdds_dsi_enabled = false;
1832         }
1833
1834         dsi_disable_scp_clk(dsidev);
1835         dsi_enable_pll_clock(dsidev, 0);
1836
1837         DSSDBG("PLL uninit done\n");
1838 }
1839
1840 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1841                 struct seq_file *s)
1842 {
1843         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1844         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1845         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1846         int dsi_module = dsi->module_id;
1847
1848         dispc_clk_src = dss_get_dispc_clk_source();
1849         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1850
1851         if (dsi_runtime_get(dsidev))
1852                 return;
1853
1854         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1855
1856         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1857
1858         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1859
1860         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1861                         cinfo->clkin4ddr, cinfo->regm);
1862
1863         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1864                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1865                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1866                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1867                         cinfo->dsi_pll_hsdiv_dispc_clk,
1868                         cinfo->regm_dispc,
1869                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1870                         "off" : "on");
1871
1872         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1873                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1874                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1875                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1876                         cinfo->dsi_pll_hsdiv_dsi_clk,
1877                         cinfo->regm_dsi,
1878                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1879                         "off" : "on");
1880
1881         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1882
1883         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1884                         dss_get_generic_clk_source_name(dsi_clk_src),
1885                         dss_feat_get_clk_source_name(dsi_clk_src));
1886
1887         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1888
1889         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1890                         cinfo->clkin4ddr / 4);
1891
1892         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1893
1894         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1895
1896         dsi_runtime_put(dsidev);
1897 }
1898
1899 void dsi_dump_clocks(struct seq_file *s)
1900 {
1901         struct platform_device *dsidev;
1902         int i;
1903
1904         for  (i = 0; i < MAX_NUM_DSI; i++) {
1905                 dsidev = dsi_get_dsidev_from_id(i);
1906                 if (dsidev)
1907                         dsi_dump_dsidev_clocks(dsidev, s);
1908         }
1909 }
1910
1911 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1912 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1913                 struct seq_file *s)
1914 {
1915         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1916         unsigned long flags;
1917         struct dsi_irq_stats stats;
1918
1919         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1920
1921         stats = dsi->irq_stats;
1922         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1923         dsi->irq_stats.last_reset = jiffies;
1924
1925         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1926
1927         seq_printf(s, "period %u ms\n",
1928                         jiffies_to_msecs(jiffies - stats.last_reset));
1929
1930         seq_printf(s, "irqs %d\n", stats.irq_count);
1931 #define PIS(x) \
1932         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1933
1934         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1935         PIS(VC0);
1936         PIS(VC1);
1937         PIS(VC2);
1938         PIS(VC3);
1939         PIS(WAKEUP);
1940         PIS(RESYNC);
1941         PIS(PLL_LOCK);
1942         PIS(PLL_UNLOCK);
1943         PIS(PLL_RECALL);
1944         PIS(COMPLEXIO_ERR);
1945         PIS(HS_TX_TIMEOUT);
1946         PIS(LP_RX_TIMEOUT);
1947         PIS(TE_TRIGGER);
1948         PIS(ACK_TRIGGER);
1949         PIS(SYNC_LOST);
1950         PIS(LDO_POWER_GOOD);
1951         PIS(TA_TIMEOUT);
1952 #undef PIS
1953
1954 #define PIS(x) \
1955         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1956                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1957                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1958                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1959                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1960
1961         seq_printf(s, "-- VC interrupts --\n");
1962         PIS(CS);
1963         PIS(ECC_CORR);
1964         PIS(PACKET_SENT);
1965         PIS(FIFO_TX_OVF);
1966         PIS(FIFO_RX_OVF);
1967         PIS(BTA);
1968         PIS(ECC_NO_CORR);
1969         PIS(FIFO_TX_UDF);
1970         PIS(PP_BUSY_CHANGE);
1971 #undef PIS
1972
1973 #define PIS(x) \
1974         seq_printf(s, "%-20s %10d\n", #x, \
1975                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1976
1977         seq_printf(s, "-- CIO interrupts --\n");
1978         PIS(ERRSYNCESC1);
1979         PIS(ERRSYNCESC2);
1980         PIS(ERRSYNCESC3);
1981         PIS(ERRESC1);
1982         PIS(ERRESC2);
1983         PIS(ERRESC3);
1984         PIS(ERRCONTROL1);
1985         PIS(ERRCONTROL2);
1986         PIS(ERRCONTROL3);
1987         PIS(STATEULPS1);
1988         PIS(STATEULPS2);
1989         PIS(STATEULPS3);
1990         PIS(ERRCONTENTIONLP0_1);
1991         PIS(ERRCONTENTIONLP1_1);
1992         PIS(ERRCONTENTIONLP0_2);
1993         PIS(ERRCONTENTIONLP1_2);
1994         PIS(ERRCONTENTIONLP0_3);
1995         PIS(ERRCONTENTIONLP1_3);
1996         PIS(ULPSACTIVENOT_ALL0);
1997         PIS(ULPSACTIVENOT_ALL1);
1998 #undef PIS
1999 }
2000
2001 static void dsi1_dump_irqs(struct seq_file *s)
2002 {
2003         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2004
2005         dsi_dump_dsidev_irqs(dsidev, s);
2006 }
2007
2008 static void dsi2_dump_irqs(struct seq_file *s)
2009 {
2010         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2011
2012         dsi_dump_dsidev_irqs(dsidev, s);
2013 }
2014 #endif
2015
2016 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
2017                 struct seq_file *s)
2018 {
2019 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
2020
2021         if (dsi_runtime_get(dsidev))
2022                 return;
2023         dsi_enable_scp_clk(dsidev);
2024
2025         DUMPREG(DSI_REVISION);
2026         DUMPREG(DSI_SYSCONFIG);
2027         DUMPREG(DSI_SYSSTATUS);
2028         DUMPREG(DSI_IRQSTATUS);
2029         DUMPREG(DSI_IRQENABLE);
2030         DUMPREG(DSI_CTRL);
2031         DUMPREG(DSI_COMPLEXIO_CFG1);
2032         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
2033         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
2034         DUMPREG(DSI_CLK_CTRL);
2035         DUMPREG(DSI_TIMING1);
2036         DUMPREG(DSI_TIMING2);
2037         DUMPREG(DSI_VM_TIMING1);
2038         DUMPREG(DSI_VM_TIMING2);
2039         DUMPREG(DSI_VM_TIMING3);
2040         DUMPREG(DSI_CLK_TIMING);
2041         DUMPREG(DSI_TX_FIFO_VC_SIZE);
2042         DUMPREG(DSI_RX_FIFO_VC_SIZE);
2043         DUMPREG(DSI_COMPLEXIO_CFG2);
2044         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
2045         DUMPREG(DSI_VM_TIMING4);
2046         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
2047         DUMPREG(DSI_VM_TIMING5);
2048         DUMPREG(DSI_VM_TIMING6);
2049         DUMPREG(DSI_VM_TIMING7);
2050         DUMPREG(DSI_STOPCLK_TIMING);
2051
2052         DUMPREG(DSI_VC_CTRL(0));
2053         DUMPREG(DSI_VC_TE(0));
2054         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
2055         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
2056         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
2057         DUMPREG(DSI_VC_IRQSTATUS(0));
2058         DUMPREG(DSI_VC_IRQENABLE(0));
2059
2060         DUMPREG(DSI_VC_CTRL(1));
2061         DUMPREG(DSI_VC_TE(1));
2062         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
2063         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
2064         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
2065         DUMPREG(DSI_VC_IRQSTATUS(1));
2066         DUMPREG(DSI_VC_IRQENABLE(1));
2067
2068         DUMPREG(DSI_VC_CTRL(2));
2069         DUMPREG(DSI_VC_TE(2));
2070         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
2071         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
2072         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
2073         DUMPREG(DSI_VC_IRQSTATUS(2));
2074         DUMPREG(DSI_VC_IRQENABLE(2));
2075
2076         DUMPREG(DSI_VC_CTRL(3));
2077         DUMPREG(DSI_VC_TE(3));
2078         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
2079         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
2080         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
2081         DUMPREG(DSI_VC_IRQSTATUS(3));
2082         DUMPREG(DSI_VC_IRQENABLE(3));
2083
2084         DUMPREG(DSI_DSIPHY_CFG0);
2085         DUMPREG(DSI_DSIPHY_CFG1);
2086         DUMPREG(DSI_DSIPHY_CFG2);
2087         DUMPREG(DSI_DSIPHY_CFG5);
2088
2089         DUMPREG(DSI_PLL_CONTROL);
2090         DUMPREG(DSI_PLL_STATUS);
2091         DUMPREG(DSI_PLL_GO);
2092         DUMPREG(DSI_PLL_CONFIGURATION1);
2093         DUMPREG(DSI_PLL_CONFIGURATION2);
2094
2095         dsi_disable_scp_clk(dsidev);
2096         dsi_runtime_put(dsidev);
2097 #undef DUMPREG
2098 }
2099
2100 static void dsi1_dump_regs(struct seq_file *s)
2101 {
2102         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2103
2104         dsi_dump_dsidev_regs(dsidev, s);
2105 }
2106
2107 static void dsi2_dump_regs(struct seq_file *s)
2108 {
2109         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2110
2111         dsi_dump_dsidev_regs(dsidev, s);
2112 }
2113
2114 enum dsi_cio_power_state {
2115         DSI_COMPLEXIO_POWER_OFF         = 0x0,
2116         DSI_COMPLEXIO_POWER_ON          = 0x1,
2117         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
2118 };
2119
2120 static int dsi_cio_power(struct platform_device *dsidev,
2121                 enum dsi_cio_power_state state)
2122 {
2123         int t = 0;
2124
2125         /* PWR_CMD */
2126         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2127
2128         /* PWR_STATUS */
2129         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2130                         26, 25) != state) {
2131                 if (++t > 1000) {
2132                         DSSERR("failed to set complexio power state to "
2133                                         "%d\n", state);
2134                         return -ENODEV;
2135                 }
2136                 udelay(1);
2137         }
2138
2139         return 0;
2140 }
2141
2142 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2143 {
2144         int val;
2145
2146         /* line buffer on OMAP3 is 1024 x 24bits */
2147         /* XXX: for some reason using full buffer size causes
2148          * considerable TX slowdown with update sizes that fill the
2149          * whole buffer */
2150         if (!dss_has_feature(FEAT_DSI_GNQ))
2151                 return 1023 * 3;
2152
2153         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2154
2155         switch (val) {
2156         case 1:
2157                 return 512 * 3;         /* 512x24 bits */
2158         case 2:
2159                 return 682 * 3;         /* 682x24 bits */
2160         case 3:
2161                 return 853 * 3;         /* 853x24 bits */
2162         case 4:
2163                 return 1024 * 3;        /* 1024x24 bits */
2164         case 5:
2165                 return 1194 * 3;        /* 1194x24 bits */
2166         case 6:
2167                 return 1365 * 3;        /* 1365x24 bits */
2168         case 7:
2169                 return 1920 * 3;        /* 1920x24 bits */
2170         default:
2171                 BUG();
2172                 return 0;
2173         }
2174 }
2175
2176 static int dsi_set_lane_config(struct platform_device *dsidev)
2177 {
2178         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2179         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2180         static const enum dsi_lane_function functions[] = {
2181                 DSI_LANE_CLK,
2182                 DSI_LANE_DATA1,
2183                 DSI_LANE_DATA2,
2184                 DSI_LANE_DATA3,
2185                 DSI_LANE_DATA4,
2186         };
2187         u32 r;
2188         int i;
2189
2190         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2191
2192         for (i = 0; i < dsi->num_lanes_used; ++i) {
2193                 unsigned offset = offsets[i];
2194                 unsigned polarity, lane_number;
2195                 unsigned t;
2196
2197                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2198                         if (dsi->lanes[t].function == functions[i])
2199                                 break;
2200
2201                 if (t == dsi->num_lanes_supported)
2202                         return -EINVAL;
2203
2204                 lane_number = t;
2205                 polarity = dsi->lanes[t].polarity;
2206
2207                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2208                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2209         }
2210
2211         /* clear the unused lanes */
2212         for (; i < dsi->num_lanes_supported; ++i) {
2213                 unsigned offset = offsets[i];
2214
2215                 r = FLD_MOD(r, 0, offset + 2, offset);
2216                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2217         }
2218
2219         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2220
2221         return 0;
2222 }
2223
2224 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2225 {
2226         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2227
2228         /* convert time in ns to ddr ticks, rounding up */
2229         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2230         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2231 }
2232
2233 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2234 {
2235         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2236
2237         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2238         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2239 }
2240
2241 static void dsi_cio_timings(struct platform_device *dsidev)
2242 {
2243         u32 r;
2244         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2245         u32 tlpx_half, tclk_trail, tclk_zero;
2246         u32 tclk_prepare;
2247
2248         /* calculate timings */
2249
2250         /* 1 * DDR_CLK = 2 * UI */
2251
2252         /* min 40ns + 4*UI      max 85ns + 6*UI */
2253         ths_prepare = ns2ddr(dsidev, 70) + 2;
2254
2255         /* min 145ns + 10*UI */
2256         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2257
2258         /* min max(8*UI, 60ns+4*UI) */
2259         ths_trail = ns2ddr(dsidev, 60) + 5;
2260
2261         /* min 100ns */
2262         ths_exit = ns2ddr(dsidev, 145);
2263
2264         /* tlpx min 50n */
2265         tlpx_half = ns2ddr(dsidev, 25);
2266
2267         /* min 60ns */
2268         tclk_trail = ns2ddr(dsidev, 60) + 2;
2269
2270         /* min 38ns, max 95ns */
2271         tclk_prepare = ns2ddr(dsidev, 65);
2272
2273         /* min tclk-prepare + tclk-zero = 300ns */
2274         tclk_zero = ns2ddr(dsidev, 260);
2275
2276         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2277                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2278                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2279         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2280                         ths_trail, ddr2ns(dsidev, ths_trail),
2281                         ths_exit, ddr2ns(dsidev, ths_exit));
2282
2283         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2284                         "tclk_zero %u (%uns)\n",
2285                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2286                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2287                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2288         DSSDBG("tclk_prepare %u (%uns)\n",
2289                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2290
2291         /* program timings */
2292
2293         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2294         r = FLD_MOD(r, ths_prepare, 31, 24);
2295         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2296         r = FLD_MOD(r, ths_trail, 15, 8);
2297         r = FLD_MOD(r, ths_exit, 7, 0);
2298         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2299
2300         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2301         r = FLD_MOD(r, tlpx_half, 20, 16);
2302         r = FLD_MOD(r, tclk_trail, 15, 8);
2303         r = FLD_MOD(r, tclk_zero, 7, 0);
2304
2305         if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2306                 r = FLD_MOD(r, 0, 21, 21);      /* DCCEN = disable */
2307                 r = FLD_MOD(r, 1, 22, 22);      /* CLKINP_DIVBY2EN = enable */
2308                 r = FLD_MOD(r, 1, 23, 23);      /* CLKINP_SEL = enable */
2309         }
2310
2311         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2312
2313         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2314         r = FLD_MOD(r, tclk_prepare, 7, 0);
2315         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2316 }
2317
2318 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2319 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2320                 unsigned mask_p, unsigned mask_n)
2321 {
2322         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2323         int i;
2324         u32 l;
2325         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2326
2327         l = 0;
2328
2329         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2330                 unsigned p = dsi->lanes[i].polarity;
2331
2332                 if (mask_p & (1 << i))
2333                         l |= 1 << (i * 2 + (p ? 0 : 1));
2334
2335                 if (mask_n & (1 << i))
2336                         l |= 1 << (i * 2 + (p ? 1 : 0));
2337         }
2338
2339         /*
2340          * Bits in REGLPTXSCPDAT4TO0DXDY:
2341          * 17: DY0 18: DX0
2342          * 19: DY1 20: DX1
2343          * 21: DY2 22: DX2
2344          * 23: DY3 24: DX3
2345          * 25: DY4 26: DX4
2346          */
2347
2348         /* Set the lane override configuration */
2349
2350         /* REGLPTXSCPDAT4TO0DXDY */
2351         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2352
2353         /* Enable lane override */
2354
2355         /* ENLPTXSCPDAT */
2356         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2357 }
2358
2359 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2360 {
2361         /* Disable lane override */
2362         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2363         /* Reset the lane override configuration */
2364         /* REGLPTXSCPDAT4TO0DXDY */
2365         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2366 }
2367
2368 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2369 {
2370         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2371         int t, i;
2372         bool in_use[DSI_MAX_NR_LANES];
2373         static const u8 offsets_old[] = { 28, 27, 26 };
2374         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2375         const u8 *offsets;
2376
2377         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2378                 offsets = offsets_old;
2379         else
2380                 offsets = offsets_new;
2381
2382         for (i = 0; i < dsi->num_lanes_supported; ++i)
2383                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2384
2385         t = 100000;
2386         while (true) {
2387                 u32 l;
2388                 int ok;
2389
2390                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2391
2392                 ok = 0;
2393                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2394                         if (!in_use[i] || (l & (1 << offsets[i])))
2395                                 ok++;
2396                 }
2397
2398                 if (ok == dsi->num_lanes_supported)
2399                         break;
2400
2401                 if (--t == 0) {
2402                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2403                                 if (!in_use[i] || (l & (1 << offsets[i])))
2404                                         continue;
2405
2406                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2407                                                 "out of reset\n", i);
2408                         }
2409                         return -EIO;
2410                 }
2411         }
2412
2413         return 0;
2414 }
2415
2416 /* return bitmask of enabled lanes, lane0 being the lsb */
2417 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2418 {
2419         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2420         unsigned mask = 0;
2421         int i;
2422
2423         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2424                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2425                         mask |= 1 << i;
2426         }
2427
2428         return mask;
2429 }
2430
2431 static int dsi_cio_init(struct platform_device *dsidev)
2432 {
2433         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2434         int r;
2435         u32 l;
2436
2437         DSSDBG("DSI CIO init starts");
2438
2439         r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2440         if (r)
2441                 return r;
2442
2443         dsi_enable_scp_clk(dsidev);
2444
2445         /* A dummy read using the SCP interface to any DSIPHY register is
2446          * required after DSIPHY reset to complete the reset of the DSI complex
2447          * I/O. */
2448         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2449
2450         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2451                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2452                 r = -EIO;
2453                 goto err_scp_clk_dom;
2454         }
2455
2456         r = dsi_set_lane_config(dsidev);
2457         if (r)
2458                 goto err_scp_clk_dom;
2459
2460         /* set TX STOP MODE timer to maximum for this operation */
2461         l = dsi_read_reg(dsidev, DSI_TIMING1);
2462         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2463         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2464         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2465         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2466         dsi_write_reg(dsidev, DSI_TIMING1, l);
2467
2468         if (dsi->ulps_enabled) {
2469                 unsigned mask_p;
2470                 int i;
2471
2472                 DSSDBG("manual ulps exit\n");
2473
2474                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2475                  * stop state. DSS HW cannot do this via the normal
2476                  * ULPS exit sequence, as after reset the DSS HW thinks
2477                  * that we are not in ULPS mode, and refuses to send the
2478                  * sequence. So we need to send the ULPS exit sequence
2479                  * manually by setting positive lines high and negative lines
2480                  * low for 1ms.
2481                  */
2482
2483                 mask_p = 0;
2484
2485                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2486                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2487                                 continue;
2488                         mask_p |= 1 << i;
2489                 }
2490
2491                 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2492         }
2493
2494         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2495         if (r)
2496                 goto err_cio_pwr;
2497
2498         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2499                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2500                 r = -ENODEV;
2501                 goto err_cio_pwr_dom;
2502         }
2503
2504         dsi_if_enable(dsidev, true);
2505         dsi_if_enable(dsidev, false);
2506         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2507
2508         r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2509         if (r)
2510                 goto err_tx_clk_esc_rst;
2511
2512         if (dsi->ulps_enabled) {
2513                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2514                 ktime_t wait = ns_to_ktime(1000 * 1000);
2515                 set_current_state(TASK_UNINTERRUPTIBLE);
2516                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2517
2518                 /* Disable the override. The lanes should be set to Mark-11
2519                  * state by the HW */
2520                 dsi_cio_disable_lane_override(dsidev);
2521         }
2522
2523         /* FORCE_TX_STOP_MODE_IO */
2524         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2525
2526         dsi_cio_timings(dsidev);
2527
2528         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2529                 /* DDR_CLK_ALWAYS_ON */
2530                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2531                         dsi->vm_timings.ddr_clk_always_on, 13, 13);
2532         }
2533
2534         dsi->ulps_enabled = false;
2535
2536         DSSDBG("CIO init done\n");
2537
2538         return 0;
2539
2540 err_tx_clk_esc_rst:
2541         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2542 err_cio_pwr_dom:
2543         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2544 err_cio_pwr:
2545         if (dsi->ulps_enabled)
2546                 dsi_cio_disable_lane_override(dsidev);
2547 err_scp_clk_dom:
2548         dsi_disable_scp_clk(dsidev);
2549         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2550         return r;
2551 }
2552
2553 static void dsi_cio_uninit(struct platform_device *dsidev)
2554 {
2555         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2556
2557         /* DDR_CLK_ALWAYS_ON */
2558         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2559
2560         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2561         dsi_disable_scp_clk(dsidev);
2562         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2563 }
2564
2565 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2566                 enum fifo_size size1, enum fifo_size size2,
2567                 enum fifo_size size3, enum fifo_size size4)
2568 {
2569         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2570         u32 r = 0;
2571         int add = 0;
2572         int i;
2573
2574         dsi->vc[0].fifo_size = size1;
2575         dsi->vc[1].fifo_size = size2;
2576         dsi->vc[2].fifo_size = size3;
2577         dsi->vc[3].fifo_size = size4;
2578
2579         for (i = 0; i < 4; i++) {
2580                 u8 v;
2581                 int size = dsi->vc[i].fifo_size;
2582
2583                 if (add + size > 4) {
2584                         DSSERR("Illegal FIFO configuration\n");
2585                         BUG();
2586                         return;
2587                 }
2588
2589                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2590                 r |= v << (8 * i);
2591                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2592                 add += size;
2593         }
2594
2595         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2596 }
2597
2598 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2599                 enum fifo_size size1, enum fifo_size size2,
2600                 enum fifo_size size3, enum fifo_size size4)
2601 {
2602         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2603         u32 r = 0;
2604         int add = 0;
2605         int i;
2606
2607         dsi->vc[0].fifo_size = size1;
2608         dsi->vc[1].fifo_size = size2;
2609         dsi->vc[2].fifo_size = size3;
2610         dsi->vc[3].fifo_size = size4;
2611
2612         for (i = 0; i < 4; i++) {
2613                 u8 v;
2614                 int size = dsi->vc[i].fifo_size;
2615
2616                 if (add + size > 4) {
2617                         DSSERR("Illegal FIFO configuration\n");
2618                         BUG();
2619                         return;
2620                 }
2621
2622                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2623                 r |= v << (8 * i);
2624                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2625                 add += size;
2626         }
2627
2628         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2629 }
2630
2631 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2632 {
2633         u32 r;
2634
2635         r = dsi_read_reg(dsidev, DSI_TIMING1);
2636         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2637         dsi_write_reg(dsidev, DSI_TIMING1, r);
2638
2639         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2640                 DSSERR("TX_STOP bit not going down\n");
2641                 return -EIO;
2642         }
2643
2644         return 0;
2645 }
2646
2647 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2648 {
2649         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2650 }
2651
2652 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2653 {
2654         struct dsi_packet_sent_handler_data *vp_data =
2655                 (struct dsi_packet_sent_handler_data *) data;
2656         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2657         const int channel = dsi->update_channel;
2658         u8 bit = dsi->te_enabled ? 30 : 31;
2659
2660         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2661                 complete(vp_data->completion);
2662 }
2663
2664 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2665 {
2666         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2667         DECLARE_COMPLETION_ONSTACK(completion);
2668         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2669         int r = 0;
2670         u8 bit;
2671
2672         bit = dsi->te_enabled ? 30 : 31;
2673
2674         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2675                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2676         if (r)
2677                 goto err0;
2678
2679         /* Wait for completion only if TE_EN/TE_START is still set */
2680         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2681                 if (wait_for_completion_timeout(&completion,
2682                                 msecs_to_jiffies(10)) == 0) {
2683                         DSSERR("Failed to complete previous frame transfer\n");
2684                         r = -EIO;
2685                         goto err1;
2686                 }
2687         }
2688
2689         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2690                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2691
2692         return 0;
2693 err1:
2694         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2695                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2696 err0:
2697         return r;
2698 }
2699
2700 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2701 {
2702         struct dsi_packet_sent_handler_data *l4_data =
2703                 (struct dsi_packet_sent_handler_data *) data;
2704         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2705         const int channel = dsi->update_channel;
2706
2707         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2708                 complete(l4_data->completion);
2709 }
2710
2711 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2712 {
2713         DECLARE_COMPLETION_ONSTACK(completion);
2714         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2715         int r = 0;
2716
2717         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2718                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2719         if (r)
2720                 goto err0;
2721
2722         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2723         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2724                 if (wait_for_completion_timeout(&completion,
2725                                 msecs_to_jiffies(10)) == 0) {
2726                         DSSERR("Failed to complete previous l4 transfer\n");
2727                         r = -EIO;
2728                         goto err1;
2729                 }
2730         }
2731
2732         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2733                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2734
2735         return 0;
2736 err1:
2737         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2738                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2739 err0:
2740         return r;
2741 }
2742
2743 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2744 {
2745         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2746
2747         WARN_ON(!dsi_bus_is_locked(dsidev));
2748
2749         WARN_ON(in_interrupt());
2750
2751         if (!dsi_vc_is_enabled(dsidev, channel))
2752                 return 0;
2753
2754         switch (dsi->vc[channel].source) {
2755         case DSI_VC_SOURCE_VP:
2756                 return dsi_sync_vc_vp(dsidev, channel);
2757         case DSI_VC_SOURCE_L4:
2758                 return dsi_sync_vc_l4(dsidev, channel);
2759         default:
2760                 BUG();
2761                 return -EINVAL;
2762         }
2763 }
2764
2765 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2766                 bool enable)
2767 {
2768         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2769                         channel, enable);
2770
2771         enable = enable ? 1 : 0;
2772
2773         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2774
2775         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2776                 0, enable) != enable) {
2777                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2778                         return -EIO;
2779         }
2780
2781         return 0;
2782 }
2783
2784 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2785 {
2786         u32 r;
2787
2788         DSSDBG("Initial config of virtual channel %d", channel);
2789
2790         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2791
2792         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2793                 DSSERR("VC(%d) busy when trying to configure it!\n",
2794                                 channel);
2795
2796         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2797         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2798         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2799         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2800         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2801         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2802         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2803         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2804                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2805
2806         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2807         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2808
2809         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2810 }
2811
2812 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2813                 enum dsi_vc_source source)
2814 {
2815         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2816
2817         if (dsi->vc[channel].source == source)
2818                 return 0;
2819
2820         DSSDBG("Source config of virtual channel %d", channel);
2821
2822         dsi_sync_vc(dsidev, channel);
2823
2824         dsi_vc_enable(dsidev, channel, 0);
2825
2826         /* VC_BUSY */
2827         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2828                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2829                 return -EIO;
2830         }
2831
2832         /* SOURCE, 0 = L4, 1 = video port */
2833         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2834
2835         /* DCS_CMD_ENABLE */
2836         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2837                 bool enable = source == DSI_VC_SOURCE_VP;
2838                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2839         }
2840
2841         dsi_vc_enable(dsidev, channel, 1);
2842
2843         dsi->vc[channel].source = source;
2844
2845         return 0;
2846 }
2847
2848 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2849                 bool enable)
2850 {
2851         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2852         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2853
2854         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2855
2856         WARN_ON(!dsi_bus_is_locked(dsidev));
2857
2858         dsi_vc_enable(dsidev, channel, 0);
2859         dsi_if_enable(dsidev, 0);
2860
2861         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2862
2863         dsi_vc_enable(dsidev, channel, 1);
2864         dsi_if_enable(dsidev, 1);
2865
2866         dsi_force_tx_stop_mode_io(dsidev);
2867
2868         /* start the DDR clock by sending a NULL packet */
2869         if (dsi->vm_timings.ddr_clk_always_on && enable)
2870                 dsi_vc_send_null(dssdev, channel);
2871 }
2872 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2873
2874 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2875 {
2876         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2877                 u32 val;
2878                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2879                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2880                                 (val >> 0) & 0xff,
2881                                 (val >> 8) & 0xff,
2882                                 (val >> 16) & 0xff,
2883                                 (val >> 24) & 0xff);
2884         }
2885 }
2886
2887 static void dsi_show_rx_ack_with_err(u16 err)
2888 {
2889         DSSERR("\tACK with ERROR (%#x):\n", err);
2890         if (err & (1 << 0))
2891                 DSSERR("\t\tSoT Error\n");
2892         if (err & (1 << 1))
2893                 DSSERR("\t\tSoT Sync Error\n");
2894         if (err & (1 << 2))
2895                 DSSERR("\t\tEoT Sync Error\n");
2896         if (err & (1 << 3))
2897                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2898         if (err & (1 << 4))
2899                 DSSERR("\t\tLP Transmit Sync Error\n");
2900         if (err & (1 << 5))
2901                 DSSERR("\t\tHS Receive Timeout Error\n");
2902         if (err & (1 << 6))
2903                 DSSERR("\t\tFalse Control Error\n");
2904         if (err & (1 << 7))
2905                 DSSERR("\t\t(reserved7)\n");
2906         if (err & (1 << 8))
2907                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2908         if (err & (1 << 9))
2909                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2910         if (err & (1 << 10))
2911                 DSSERR("\t\tChecksum Error\n");
2912         if (err & (1 << 11))
2913                 DSSERR("\t\tData type not recognized\n");
2914         if (err & (1 << 12))
2915                 DSSERR("\t\tInvalid VC ID\n");
2916         if (err & (1 << 13))
2917                 DSSERR("\t\tInvalid Transmission Length\n");
2918         if (err & (1 << 14))
2919                 DSSERR("\t\t(reserved14)\n");
2920         if (err & (1 << 15))
2921                 DSSERR("\t\tDSI Protocol Violation\n");
2922 }
2923
2924 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2925                 int channel)
2926 {
2927         /* RX_FIFO_NOT_EMPTY */
2928         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2929                 u32 val;
2930                 u8 dt;
2931                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2932                 DSSERR("\trawval %#08x\n", val);
2933                 dt = FLD_GET(val, 5, 0);
2934                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2935                         u16 err = FLD_GET(val, 23, 8);
2936                         dsi_show_rx_ack_with_err(err);
2937                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2938                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2939                                         FLD_GET(val, 23, 8));
2940                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2941                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2942                                         FLD_GET(val, 23, 8));
2943                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2944                         DSSERR("\tDCS long response, len %d\n",
2945                                         FLD_GET(val, 23, 8));
2946                         dsi_vc_flush_long_data(dsidev, channel);
2947                 } else {
2948                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2949                 }
2950         }
2951         return 0;
2952 }
2953
2954 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2955 {
2956         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2957
2958         if (dsi->debug_write || dsi->debug_read)
2959                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2960
2961         WARN_ON(!dsi_bus_is_locked(dsidev));
2962
2963         /* RX_FIFO_NOT_EMPTY */
2964         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2965                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2966                 dsi_vc_flush_receive_data(dsidev, channel);
2967         }
2968
2969         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2970
2971         /* flush posted write */
2972         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2973
2974         return 0;
2975 }
2976
2977 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2978 {
2979         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2980         DECLARE_COMPLETION_ONSTACK(completion);
2981         int r = 0;
2982         u32 err;
2983
2984         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2985                         &completion, DSI_VC_IRQ_BTA);
2986         if (r)
2987                 goto err0;
2988
2989         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2990                         DSI_IRQ_ERROR_MASK);
2991         if (r)
2992                 goto err1;
2993
2994         r = dsi_vc_send_bta(dsidev, channel);
2995         if (r)
2996                 goto err2;
2997
2998         if (wait_for_completion_timeout(&completion,
2999                                 msecs_to_jiffies(500)) == 0) {
3000                 DSSERR("Failed to receive BTA\n");
3001                 r = -EIO;
3002                 goto err2;
3003         }
3004
3005         err = dsi_get_errors(dsidev);
3006         if (err) {
3007                 DSSERR("Error while sending BTA: %x\n", err);
3008                 r = -EIO;
3009                 goto err2;
3010         }
3011 err2:
3012         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
3013                         DSI_IRQ_ERROR_MASK);
3014 err1:
3015         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
3016                         &completion, DSI_VC_IRQ_BTA);
3017 err0:
3018         return r;
3019 }
3020 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
3021
3022 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
3023                 int channel, u8 data_type, u16 len, u8 ecc)
3024 {
3025         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3026         u32 val;
3027         u8 data_id;
3028
3029         WARN_ON(!dsi_bus_is_locked(dsidev));
3030
3031         data_id = data_type | dsi->vc[channel].vc_id << 6;
3032
3033         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
3034                 FLD_VAL(ecc, 31, 24);
3035
3036         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
3037 }
3038
3039 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
3040                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
3041 {
3042         u32 val;
3043
3044         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
3045
3046 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3047                         b1, b2, b3, b4, val); */
3048
3049         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3050 }
3051
3052 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3053                 u8 data_type, u8 *data, u16 len, u8 ecc)
3054 {
3055         /*u32 val; */
3056         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3057         int i;
3058         u8 *p;
3059         int r = 0;
3060         u8 b1, b2, b3, b4;
3061
3062         if (dsi->debug_write)
3063                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3064
3065         /* len + header */
3066         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3067                 DSSERR("unable to send long packet: packet too long.\n");
3068                 return -EINVAL;
3069         }
3070
3071         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3072
3073         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3074
3075         p = data;
3076         for (i = 0; i < len >> 2; i++) {
3077                 if (dsi->debug_write)
3078                         DSSDBG("\tsending full packet %d\n", i);
3079
3080                 b1 = *p++;
3081                 b2 = *p++;
3082                 b3 = *p++;
3083                 b4 = *p++;
3084
3085                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3086         }
3087
3088         i = len % 4;
3089         if (i) {
3090                 b1 = 0; b2 = 0; b3 = 0;
3091
3092                 if (dsi->debug_write)
3093                         DSSDBG("\tsending remainder bytes %d\n", i);
3094
3095                 switch (i) {
3096                 case 3:
3097                         b1 = *p++;
3098                         b2 = *p++;
3099                         b3 = *p++;
3100                         break;
3101                 case 2:
3102                         b1 = *p++;
3103                         b2 = *p++;
3104                         break;
3105                 case 1:
3106                         b1 = *p++;
3107                         break;
3108                 }
3109
3110                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3111         }
3112
3113         return r;
3114 }
3115
3116 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3117                 u8 data_type, u16 data, u8 ecc)
3118 {
3119         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3120         u32 r;
3121         u8 data_id;
3122
3123         WARN_ON(!dsi_bus_is_locked(dsidev));
3124
3125         if (dsi->debug_write)
3126                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3127                                 channel,
3128                                 data_type, data & 0xff, (data >> 8) & 0xff);
3129
3130         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3131
3132         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3133                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3134                 return -EINVAL;
3135         }
3136
3137         data_id = data_type | dsi->vc[channel].vc_id << 6;
3138
3139         r = (data_id << 0) | (data << 8) | (ecc << 24);
3140
3141         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3142
3143         return 0;
3144 }
3145
3146 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3147 {
3148         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3149
3150         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3151                 0, 0);
3152 }
3153 EXPORT_SYMBOL(dsi_vc_send_null);
3154
3155 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3156                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3157 {
3158         int r;
3159
3160         if (len == 0) {
3161                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3162                 r = dsi_vc_send_short(dsidev, channel,
3163                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3164         } else if (len == 1) {
3165                 r = dsi_vc_send_short(dsidev, channel,
3166                                 type == DSS_DSI_CONTENT_GENERIC ?
3167                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3168                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3169         } else if (len == 2) {
3170                 r = dsi_vc_send_short(dsidev, channel,
3171                                 type == DSS_DSI_CONTENT_GENERIC ?
3172                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3173                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3174                                 data[0] | (data[1] << 8), 0);
3175         } else {
3176                 r = dsi_vc_send_long(dsidev, channel,
3177                                 type == DSS_DSI_CONTENT_GENERIC ?
3178                                 MIPI_DSI_GENERIC_LONG_WRITE :
3179                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3180         }
3181
3182         return r;
3183 }
3184
3185 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3186                 u8 *data, int len)
3187 {
3188         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3189
3190         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3191                         DSS_DSI_CONTENT_DCS);
3192 }
3193 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3194
3195 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3196                 u8 *data, int len)
3197 {
3198         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3199
3200         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3201                         DSS_DSI_CONTENT_GENERIC);
3202 }
3203 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3204
3205 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3206                 u8 *data, int len, enum dss_dsi_content_type type)
3207 {
3208         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3209         int r;
3210
3211         r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3212         if (r)
3213                 goto err;
3214
3215         r = dsi_vc_send_bta_sync(dssdev, channel);
3216         if (r)
3217                 goto err;
3218
3219         /* RX_FIFO_NOT_EMPTY */
3220         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3221                 DSSERR("rx fifo not empty after write, dumping data:\n");
3222                 dsi_vc_flush_receive_data(dsidev, channel);
3223                 r = -EIO;
3224                 goto err;
3225         }
3226
3227         return 0;
3228 err:
3229         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3230                         channel, data[0], len);
3231         return r;
3232 }
3233
3234 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3235                 int len)
3236 {
3237         return dsi_vc_write_common(dssdev, channel, data, len,
3238                         DSS_DSI_CONTENT_DCS);
3239 }
3240 EXPORT_SYMBOL(dsi_vc_dcs_write);
3241
3242 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3243                 int len)
3244 {
3245         return dsi_vc_write_common(dssdev, channel, data, len,
3246                         DSS_DSI_CONTENT_GENERIC);
3247 }
3248 EXPORT_SYMBOL(dsi_vc_generic_write);
3249
3250 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3251 {
3252         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3253 }
3254 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3255
3256 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3257 {
3258         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3259 }
3260 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3261
3262 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3263                 u8 param)
3264 {
3265         u8 buf[2];
3266         buf[0] = dcs_cmd;
3267         buf[1] = param;
3268         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3269 }
3270 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3271
3272 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3273                 u8 param)
3274 {
3275         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3276 }
3277 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3278
3279 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3280                 u8 param1, u8 param2)
3281 {
3282         u8 buf[2];
3283         buf[0] = param1;
3284         buf[1] = param2;
3285         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3286 }
3287 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3288
3289 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3290                 int channel, u8 dcs_cmd)
3291 {
3292         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3293         int r;
3294
3295         if (dsi->debug_read)
3296                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3297                         channel, dcs_cmd);
3298
3299         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3300         if (r) {
3301                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3302                         " failed\n", channel, dcs_cmd);
3303                 return r;
3304         }
3305
3306         return 0;
3307 }
3308
3309 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3310                 int channel, u8 *reqdata, int reqlen)
3311 {
3312         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3313         u16 data;
3314         u8 data_type;
3315         int r;
3316
3317         if (dsi->debug_read)
3318                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3319                         channel, reqlen);
3320
3321         if (reqlen == 0) {
3322                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3323                 data = 0;
3324         } else if (reqlen == 1) {
3325                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3326                 data = reqdata[0];
3327         } else if (reqlen == 2) {
3328                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3329                 data = reqdata[0] | (reqdata[1] << 8);
3330         } else {
3331                 BUG();
3332                 return -EINVAL;
3333         }
3334
3335         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3336         if (r) {
3337                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3338                         " failed\n", channel, reqlen);
3339                 return r;
3340         }
3341
3342         return 0;
3343 }
3344
3345 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3346                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3347 {
3348         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3349         u32 val;
3350         u8 dt;
3351         int r;
3352
3353         /* RX_FIFO_NOT_EMPTY */
3354         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3355                 DSSERR("RX fifo empty when trying to read.\n");
3356                 r = -EIO;
3357                 goto err;
3358         }
3359
3360         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3361         if (dsi->debug_read)
3362                 DSSDBG("\theader: %08x\n", val);
3363         dt = FLD_GET(val, 5, 0);
3364         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3365                 u16 err = FLD_GET(val, 23, 8);
3366                 dsi_show_rx_ack_with_err(err);
3367                 r = -EIO;
3368                 goto err;
3369
3370         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3371                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3372                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3373                 u8 data = FLD_GET(val, 15, 8);
3374                 if (dsi->debug_read)
3375                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3376                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3377                                 "DCS", data);
3378
3379                 if (buflen < 1) {
3380                         r = -EIO;
3381                         goto err;
3382                 }
3383
3384                 buf[0] = data;
3385
3386                 return 1;
3387         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3388                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3389                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3390                 u16 data = FLD_GET(val, 23, 8);
3391                 if (dsi->debug_read)
3392                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3393                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3394                                 "DCS", data);
3395
3396                 if (buflen < 2) {
3397                         r = -EIO;
3398                         goto err;
3399                 }
3400
3401                 buf[0] = data & 0xff;
3402                 buf[1] = (data >> 8) & 0xff;
3403
3404                 return 2;
3405         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3406                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3407                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3408                 int w;
3409                 int len = FLD_GET(val, 23, 8);
3410                 if (dsi->debug_read)
3411                         DSSDBG("\t%s long response, len %d\n",
3412                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3413                                 "DCS", len);
3414
3415                 if (len > buflen) {
3416                         r = -EIO;
3417                         goto err;
3418                 }
3419
3420                 /* two byte checksum ends the packet, not included in len */
3421                 for (w = 0; w < len + 2;) {
3422                         int b;
3423                         val = dsi_read_reg(dsidev,
3424                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3425                         if (dsi->debug_read)
3426                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3427                                                 (val >> 0) & 0xff,
3428                                                 (val >> 8) & 0xff,
3429                                                 (val >> 16) & 0xff,
3430                                                 (val >> 24) & 0xff);
3431
3432                         for (b = 0; b < 4; ++b) {
3433                                 if (w < len)
3434                                         buf[w] = (val >> (b * 8)) & 0xff;
3435                                 /* we discard the 2 byte checksum */
3436                                 ++w;
3437                         }
3438                 }
3439
3440                 return len;
3441         } else {
3442                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3443                 r = -EIO;
3444                 goto err;
3445         }
3446
3447 err:
3448         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3449                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3450
3451         return r;
3452 }
3453
3454 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3455                 u8 *buf, int buflen)
3456 {
3457         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3458         int r;
3459
3460         r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3461         if (r)
3462                 goto err;
3463
3464         r = dsi_vc_send_bta_sync(dssdev, channel);
3465         if (r)
3466                 goto err;
3467
3468         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3469                 DSS_DSI_CONTENT_DCS);
3470         if (r < 0)
3471                 goto err;
3472
3473         if (r != buflen) {
3474                 r = -EIO;
3475                 goto err;
3476         }
3477
3478         return 0;
3479 err:
3480         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3481         return r;
3482 }
3483 EXPORT_SYMBOL(dsi_vc_dcs_read);
3484
3485 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3486                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3487 {
3488         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3489         int r;
3490
3491         r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3492         if (r)
3493                 return r;
3494
3495         r = dsi_vc_send_bta_sync(dssdev, channel);
3496         if (r)
3497                 return r;
3498
3499         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3500                 DSS_DSI_CONTENT_GENERIC);
3501         if (r < 0)
3502                 return r;
3503
3504         if (r != buflen) {
3505                 r = -EIO;
3506                 return r;
3507         }
3508
3509         return 0;
3510 }
3511
3512 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3513                 int buflen)
3514 {
3515         int r;
3516
3517         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3518         if (r) {
3519                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3520                 return r;
3521         }
3522
3523         return 0;
3524 }
3525 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3526
3527 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3528                 u8 *buf, int buflen)
3529 {
3530         int r;
3531
3532         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3533         if (r) {
3534                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3535                 return r;
3536         }
3537
3538         return 0;
3539 }
3540 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3541
3542 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3543                 u8 param1, u8 param2, u8 *buf, int buflen)
3544 {
3545         int r;
3546         u8 reqdata[2];
3547
3548         reqdata[0] = param1;
3549         reqdata[1] = param2;
3550
3551         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3552         if (r) {
3553                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3554                 return r;
3555         }
3556
3557         return 0;
3558 }
3559 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3560
3561 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3562                 u16 len)
3563 {
3564         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3565
3566         return dsi_vc_send_short(dsidev, channel,
3567                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3568 }
3569 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3570
3571 static int dsi_enter_ulps(struct platform_device *dsidev)
3572 {
3573         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3574         DECLARE_COMPLETION_ONSTACK(completion);
3575         int r, i;
3576         unsigned mask;
3577
3578         DSSDBG("Entering ULPS");
3579
3580         WARN_ON(!dsi_bus_is_locked(dsidev));
3581
3582         WARN_ON(dsi->ulps_enabled);
3583
3584         if (dsi->ulps_enabled)
3585                 return 0;
3586
3587         /* DDR_CLK_ALWAYS_ON */
3588         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3589                 dsi_if_enable(dsidev, 0);
3590                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3591                 dsi_if_enable(dsidev, 1);
3592         }
3593
3594         dsi_sync_vc(dsidev, 0);
3595         dsi_sync_vc(dsidev, 1);
3596         dsi_sync_vc(dsidev, 2);
3597         dsi_sync_vc(dsidev, 3);
3598
3599         dsi_force_tx_stop_mode_io(dsidev);
3600
3601         dsi_vc_enable(dsidev, 0, false);
3602         dsi_vc_enable(dsidev, 1, false);
3603         dsi_vc_enable(dsidev, 2, false);
3604         dsi_vc_enable(dsidev, 3, false);
3605
3606         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3607                 DSSERR("HS busy when enabling ULPS\n");
3608                 return -EIO;
3609         }
3610
3611         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3612                 DSSERR("LP busy when enabling ULPS\n");
3613                 return -EIO;
3614         }
3615
3616         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3617                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3618         if (r)
3619                 return r;
3620
3621         mask = 0;
3622
3623         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3624                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3625                         continue;
3626                 mask |= 1 << i;
3627         }
3628         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3629         /* LANEx_ULPS_SIG2 */
3630         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3631
3632         /* flush posted write and wait for SCP interface to finish the write */
3633         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3634
3635         if (wait_for_completion_timeout(&completion,
3636                                 msecs_to_jiffies(1000)) == 0) {
3637                 DSSERR("ULPS enable timeout\n");
3638                 r = -EIO;
3639                 goto err;
3640         }
3641
3642         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3643                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3644
3645         /* Reset LANEx_ULPS_SIG2 */
3646         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3647
3648         /* flush posted write and wait for SCP interface to finish the write */
3649         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3650
3651         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3652
3653         dsi_if_enable(dsidev, false);
3654
3655         dsi->ulps_enabled = true;
3656
3657         return 0;
3658
3659 err:
3660         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3661                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3662         return r;
3663 }
3664
3665 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3666                 unsigned ticks, bool x4, bool x16)
3667 {
3668         unsigned long fck;
3669         unsigned long total_ticks;
3670         u32 r;
3671
3672         BUG_ON(ticks > 0x1fff);
3673
3674         /* ticks in DSI_FCK */
3675         fck = dsi_fclk_rate(dsidev);
3676
3677         r = dsi_read_reg(dsidev, DSI_TIMING2);
3678         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3679         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3680         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3681         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3682         dsi_write_reg(dsidev, DSI_TIMING2, r);
3683
3684         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3685
3686         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3687                         total_ticks,
3688                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3689                         (total_ticks * 1000) / (fck / 1000 / 1000));
3690 }
3691
3692 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3693                 bool x8, bool x16)
3694 {
3695         unsigned long fck;
3696         unsigned long total_ticks;
3697         u32 r;
3698
3699         BUG_ON(ticks > 0x1fff);
3700
3701         /* ticks in DSI_FCK */
3702         fck = dsi_fclk_rate(dsidev);
3703
3704         r = dsi_read_reg(dsidev, DSI_TIMING1);
3705         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3706         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3707         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3708         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3709         dsi_write_reg(dsidev, DSI_TIMING1, r);
3710
3711         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3712
3713         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3714                         total_ticks,
3715                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3716                         (total_ticks * 1000) / (fck / 1000 / 1000));
3717 }
3718
3719 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3720                 unsigned ticks, bool x4, bool x16)
3721 {
3722         unsigned long fck;
3723         unsigned long total_ticks;
3724         u32 r;
3725
3726         BUG_ON(ticks > 0x1fff);
3727
3728         /* ticks in DSI_FCK */
3729         fck = dsi_fclk_rate(dsidev);
3730
3731         r = dsi_read_reg(dsidev, DSI_TIMING1);
3732         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3733         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3734         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3735         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3736         dsi_write_reg(dsidev, DSI_TIMING1, r);
3737
3738         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3739
3740         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3741                         total_ticks,
3742                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3743                         (total_ticks * 1000) / (fck / 1000 / 1000));
3744 }
3745
3746 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3747                 unsigned ticks, bool x4, bool x16)
3748 {
3749         unsigned long fck;
3750         unsigned long total_ticks;
3751         u32 r;
3752
3753         BUG_ON(ticks > 0x1fff);
3754
3755         /* ticks in TxByteClkHS */
3756         fck = dsi_get_txbyteclkhs(dsidev);
3757
3758         r = dsi_read_reg(dsidev, DSI_TIMING2);
3759         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3760         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3761         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3762         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3763         dsi_write_reg(dsidev, DSI_TIMING2, r);
3764
3765         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3766
3767         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3768                         total_ticks,
3769                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3770                         (total_ticks * 1000) / (fck / 1000 / 1000));
3771 }
3772
3773 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3774 {
3775         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3776         int num_line_buffers;
3777
3778         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3779                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3780                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3781                 struct omap_video_timings *timings = &dsi->timings;
3782                 /*
3783                  * Don't use line buffers if width is greater than the video
3784                  * port's line buffer size
3785                  */
3786                 if (line_buf_size <= timings->x_res * bpp / 8)
3787                         num_line_buffers = 0;
3788                 else
3789                         num_line_buffers = 2;
3790         } else {
3791                 /* Use maximum number of line buffers in command mode */
3792                 num_line_buffers = 2;
3793         }
3794
3795         /* LINE_BUFFER */
3796         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3797 }
3798
3799 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3800 {
3801         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3802         bool vsync_end = dsi->vm_timings.vp_vsync_end;
3803         bool hsync_end = dsi->vm_timings.vp_hsync_end;
3804         u32 r;
3805
3806         r = dsi_read_reg(dsidev, DSI_CTRL);
3807         r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
3808         r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
3809         r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
3810         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3811         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3812         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3813         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3814         dsi_write_reg(dsidev, DSI_CTRL, r);
3815 }
3816
3817 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3818 {
3819         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3820         int blanking_mode = dsi->vm_timings.blanking_mode;
3821         int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3822         int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3823         int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3824         u32 r;
3825
3826         /*
3827          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3828          * 1 = Long blanking packets are sent in corresponding blanking periods
3829          */
3830         r = dsi_read_reg(dsidev, DSI_CTRL);
3831         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3832         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3833         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3834         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3835         dsi_write_reg(dsidev, DSI_CTRL, r);
3836 }
3837
3838 /*
3839  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3840  * results in maximum transition time for data and clock lanes to enter and
3841  * exit HS mode. Hence, this is the scenario where the least amount of command
3842  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3843  * clock cycles that can be used to interleave command mode data in HS so that
3844  * all scenarios are satisfied.
3845  */
3846 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3847                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3848 {
3849         int transition;
3850
3851         /*
3852          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3853          * time of data lanes only, if it isn't set, we need to consider HS
3854          * transition time of both data and clock lanes. HS transition time
3855          * of Scenario 3 is considered.
3856          */
3857         if (ddr_alwon) {
3858                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3859         } else {
3860                 int trans1, trans2;
3861                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3862                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3863                                 enter_hs + 1;
3864                 transition = max(trans1, trans2);
3865         }
3866
3867         return blank > transition ? blank - transition : 0;
3868 }
3869
3870 /*
3871  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3872  * results in maximum transition time for data lanes to enter and exit LP mode.
3873  * Hence, this is the scenario where the least amount of command mode data can
3874  * be interleaved. We program the minimum amount of bytes that can be
3875  * interleaved in LP so that all scenarios are satisfied.
3876  */
3877 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3878                 int lp_clk_div, int tdsi_fclk)
3879 {
3880         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3881         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3882         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3883         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3884         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3885
3886         /* maximum LP transition time according to Scenario 1 */
3887         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3888
3889         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3890         tlp_avail = thsbyte_clk * (blank - trans_lp);
3891
3892         ttxclkesc = tdsi_fclk * lp_clk_div;
3893
3894         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3895                         26) / 16;
3896
3897         return max(lp_inter, 0);
3898 }
3899
3900 static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
3901 {
3902         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3903         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3904         int blanking_mode;
3905         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3906         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3907         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3908         int tclk_trail, ths_exit, exiths_clk;
3909         bool ddr_alwon;
3910         struct omap_video_timings *timings = &dsi->timings;
3911         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3912         int ndl = dsi->num_lanes_used - 1;
3913         int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
3914         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3915         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3916         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3917         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3918         u32 r;
3919
3920         r = dsi_read_reg(dsidev, DSI_CTRL);
3921         blanking_mode = FLD_GET(r, 20, 20);
3922         hfp_blanking_mode = FLD_GET(r, 21, 21);
3923         hbp_blanking_mode = FLD_GET(r, 22, 22);
3924         hsa_blanking_mode = FLD_GET(r, 23, 23);
3925
3926         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3927         hbp = FLD_GET(r, 11, 0);
3928         hfp = FLD_GET(r, 23, 12);
3929         hsa = FLD_GET(r, 31, 24);
3930
3931         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3932         ddr_clk_post = FLD_GET(r, 7, 0);
3933         ddr_clk_pre = FLD_GET(r, 15, 8);
3934
3935         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3936         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3937         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3938
3939         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3940         lp_clk_div = FLD_GET(r, 12, 0);
3941         ddr_alwon = FLD_GET(r, 13, 13);
3942
3943         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3944         ths_exit = FLD_GET(r, 7, 0);
3945
3946         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3947         tclk_trail = FLD_GET(r, 15, 8);
3948
3949         exiths_clk = ths_exit + tclk_trail;
3950
3951         width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3952         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3953
3954         if (!hsa_blanking_mode) {
3955                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3956                                         enter_hs_mode_lat, exit_hs_mode_lat,
3957                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3958                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3959                                         enter_hs_mode_lat, exit_hs_mode_lat,
3960                                         lp_clk_div, dsi_fclk_hsdiv);
3961         }
3962
3963         if (!hfp_blanking_mode) {
3964                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3965                                         enter_hs_mode_lat, exit_hs_mode_lat,
3966                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3967                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3968                                         enter_hs_mode_lat, exit_hs_mode_lat,
3969                                         lp_clk_div, dsi_fclk_hsdiv);
3970         }
3971
3972         if (!hbp_blanking_mode) {
3973                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3974                                         enter_hs_mode_lat, exit_hs_mode_lat,
3975                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3976
3977                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3978                                         enter_hs_mode_lat, exit_hs_mode_lat,
3979                                         lp_clk_div, dsi_fclk_hsdiv);
3980         }
3981
3982         if (!blanking_mode) {
3983                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3984                                         enter_hs_mode_lat, exit_hs_mode_lat,
3985                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3986
3987                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3988                                         enter_hs_mode_lat, exit_hs_mode_lat,
3989                                         lp_clk_div, dsi_fclk_hsdiv);
3990         }
3991
3992         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3993                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3994                 bl_interleave_hs);
3995
3996         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3997                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3998                 bl_interleave_lp);
3999
4000         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
4001         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
4002         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
4003         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
4004         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
4005
4006         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
4007         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
4008         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
4009         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
4010         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
4011
4012         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
4013         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
4014         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
4015         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
4016 }
4017
4018 static int dsi_proto_config(struct omap_dss_device *dssdev)
4019 {
4020         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4021         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4022         u32 r;
4023         int buswidth = 0;
4024
4025         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
4026                         DSI_FIFO_SIZE_32,
4027                         DSI_FIFO_SIZE_32,
4028                         DSI_FIFO_SIZE_32);
4029
4030         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
4031                         DSI_FIFO_SIZE_32,
4032                         DSI_FIFO_SIZE_32,
4033                         DSI_FIFO_SIZE_32);
4034
4035         /* XXX what values for the timeouts? */
4036         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
4037         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
4038         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
4039         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
4040
4041         switch (dsi_get_pixel_size(dsi->pix_fmt)) {
4042         case 16:
4043                 buswidth = 0;
4044                 break;
4045         case 18:
4046                 buswidth = 1;
4047                 break;
4048         case 24:
4049                 buswidth = 2;
4050                 break;
4051         default:
4052                 BUG();
4053                 return -EINVAL;
4054         }
4055
4056         r = dsi_read_reg(dsidev, DSI_CTRL);
4057         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
4058         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
4059         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
4060         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
4061         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
4062         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
4063         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
4064         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
4065         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
4066                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
4067                 /* DCS_CMD_CODE, 1=start, 0=continue */
4068                 r = FLD_MOD(r, 0, 25, 25);
4069         }
4070
4071         dsi_write_reg(dsidev, DSI_CTRL, r);
4072
4073         dsi_config_vp_num_line_buffers(dsidev);
4074
4075         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4076                 dsi_config_vp_sync_events(dsidev);
4077                 dsi_config_blanking_modes(dsidev);
4078                 dsi_config_cmd_mode_interleaving(dssdev);
4079         }
4080
4081         dsi_vc_initial_config(dsidev, 0);
4082         dsi_vc_initial_config(dsidev, 1);
4083         dsi_vc_initial_config(dsidev, 2);
4084         dsi_vc_initial_config(dsidev, 3);
4085
4086         return 0;
4087 }
4088
4089 static void dsi_proto_timings(struct platform_device *dsidev)
4090 {
4091         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4092         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
4093         unsigned tclk_pre, tclk_post;
4094         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
4095         unsigned ths_trail, ths_exit;
4096         unsigned ddr_clk_pre, ddr_clk_post;
4097         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
4098         unsigned ths_eot;
4099         int ndl = dsi->num_lanes_used - 1;
4100         u32 r;
4101
4102         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
4103         ths_prepare = FLD_GET(r, 31, 24);
4104         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
4105         ths_zero = ths_prepare_ths_zero - ths_prepare;
4106         ths_trail = FLD_GET(r, 15, 8);
4107         ths_exit = FLD_GET(r, 7, 0);
4108
4109         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
4110         tlpx = FLD_GET(r, 20, 16) * 2;
4111         tclk_trail = FLD_GET(r, 15, 8);
4112         tclk_zero = FLD_GET(r, 7, 0);
4113
4114         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
4115         tclk_prepare = FLD_GET(r, 7, 0);
4116
4117         /* min 8*UI */
4118         tclk_pre = 20;
4119         /* min 60ns + 52*UI */
4120         tclk_post = ns2ddr(dsidev, 60) + 26;
4121
4122         ths_eot = DIV_ROUND_UP(4, ndl);
4123
4124         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4125                         4);
4126         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
4127
4128         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
4129         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
4130
4131         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
4132         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
4133         r = FLD_MOD(r, ddr_clk_post, 7, 0);
4134         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
4135
4136         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
4137                         ddr_clk_pre,
4138                         ddr_clk_post);
4139
4140         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
4141                 DIV_ROUND_UP(ths_prepare, 4) +
4142                 DIV_ROUND_UP(ths_zero + 3, 4);
4143
4144         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
4145
4146         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
4147                 FLD_VAL(exit_hs_mode_lat, 15, 0);
4148         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
4149
4150         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4151                         enter_hs_mode_lat, exit_hs_mode_lat);
4152
4153          if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4154                 /* TODO: Implement a video mode check_timings function */
4155                 int hsa = dsi->vm_timings.hsa;
4156                 int hfp = dsi->vm_timings.hfp;
4157                 int hbp = dsi->vm_timings.hbp;
4158                 int vsa = dsi->vm_timings.vsa;
4159                 int vfp = dsi->vm_timings.vfp;
4160                 int vbp = dsi->vm_timings.vbp;
4161                 int window_sync = dsi->vm_timings.window_sync;
4162                 bool hsync_end = dsi->vm_timings.vp_hsync_end;
4163                 struct omap_video_timings *timings = &dsi->timings;
4164                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4165                 int tl, t_he, width_bytes;
4166
4167                 t_he = hsync_end ?
4168                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4169
4170                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4171
4172                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4173                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4174                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4175
4176                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4177                         hfp, hsync_end ? hsa : 0, tl);
4178                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4179                         vsa, timings->y_res);
4180
4181                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4182                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
4183                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
4184                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
4185                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4186
4187                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4188                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
4189                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
4190                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
4191                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
4192                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4193
4194                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4195                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
4196                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
4197                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4198         }
4199 }
4200
4201 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4202                 const struct omap_dsi_pin_config *pin_cfg)
4203 {
4204         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4205         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4206         int num_pins;
4207         const int *pins;
4208         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4209         int num_lanes;
4210         int i;
4211
4212         static const enum dsi_lane_function functions[] = {
4213                 DSI_LANE_CLK,
4214                 DSI_LANE_DATA1,
4215                 DSI_LANE_DATA2,
4216                 DSI_LANE_DATA3,
4217                 DSI_LANE_DATA4,
4218         };
4219
4220         num_pins = pin_cfg->num_pins;
4221         pins = pin_cfg->pins;
4222
4223         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4224                         || num_pins % 2 != 0)
4225                 return -EINVAL;
4226
4227         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4228                 lanes[i].function = DSI_LANE_UNUSED;
4229
4230         num_lanes = 0;
4231
4232         for (i = 0; i < num_pins; i += 2) {
4233                 u8 lane, pol;
4234                 int dx, dy;
4235
4236                 dx = pins[i];
4237                 dy = pins[i + 1];
4238
4239                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4240                         return -EINVAL;
4241
4242                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4243                         return -EINVAL;
4244
4245                 if (dx & 1) {
4246                         if (dy != dx - 1)
4247                                 return -EINVAL;
4248                         pol = 1;
4249                 } else {
4250                         if (dy != dx + 1)
4251                                 return -EINVAL;
4252                         pol = 0;
4253                 }
4254
4255                 lane = dx / 2;
4256
4257                 lanes[lane].function = functions[i / 2];
4258                 lanes[lane].polarity = pol;
4259                 num_lanes++;
4260         }
4261
4262         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4263         dsi->num_lanes_used = num_lanes;
4264
4265         return 0;
4266 }
4267 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4268
4269 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
4270                 unsigned long ddr_clk, unsigned long lp_clk)
4271 {
4272         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4273         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4274         struct dsi_clock_info cinfo;
4275         struct dispc_clock_info dispc_cinfo;
4276         unsigned lp_clk_div;
4277         unsigned long dsi_fclk;
4278         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4279         unsigned long pck;
4280         int r;
4281
4282         DSSDBG("Setting DSI clocks: ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
4283
4284         mutex_lock(&dsi->lock);
4285
4286         /* Calculate PLL output clock */
4287         r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
4288         if (r)
4289                 goto err;
4290
4291         /* Calculate PLL's DSI clock */
4292         dsi_pll_calc_dsi_fck(dsidev, &cinfo);
4293
4294         /* Calculate PLL's DISPC clock and pck & lck divs */
4295         pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
4296         DSSDBG("finding dispc dividers for pck %lu\n", pck);
4297         r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
4298         if (r)
4299                 goto err;
4300
4301         /* Calculate LP clock */
4302         dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
4303         lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
4304
4305         dssdev->clocks.dsi.regn = cinfo.regn;
4306         dssdev->clocks.dsi.regm = cinfo.regm;
4307         dssdev->clocks.dsi.regm_dispc = cinfo.regm_dispc;
4308         dssdev->clocks.dsi.regm_dsi = cinfo.regm_dsi;
4309
4310         dssdev->clocks.dsi.lp_clk_div = lp_clk_div;
4311
4312         dssdev->clocks.dispc.channel.lck_div = dispc_cinfo.lck_div;
4313         dssdev->clocks.dispc.channel.pck_div = dispc_cinfo.pck_div;
4314
4315         dssdev->clocks.dispc.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
4316
4317         dssdev->clocks.dispc.channel.lcd_clk_src =
4318                 dsi->module_id == 0 ?
4319                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4320                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
4321
4322         dssdev->clocks.dsi.dsi_fclk_src =
4323                 dsi->module_id == 0 ?
4324                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4325                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI;
4326
4327         mutex_unlock(&dsi->lock);
4328         return 0;
4329 err:
4330         mutex_unlock(&dsi->lock);
4331         return r;
4332 }
4333 EXPORT_SYMBOL(omapdss_dsi_set_clocks);
4334
4335 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4336 {
4337         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4338         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4339         struct omap_overlay_manager *mgr = dssdev->output->manager;
4340         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4341         u8 data_type;
4342         u16 word_count;
4343         int r;
4344
4345         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4346                 switch (dsi->pix_fmt) {
4347                 case OMAP_DSS_DSI_FMT_RGB888:
4348                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4349                         break;
4350                 case OMAP_DSS_DSI_FMT_RGB666:
4351                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4352                         break;
4353                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4354                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4355                         break;
4356                 case OMAP_DSS_DSI_FMT_RGB565:
4357                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4358                         break;
4359                 default:
4360                         BUG();
4361                         return -EINVAL;
4362                 };
4363
4364                 dsi_if_enable(dsidev, false);
4365                 dsi_vc_enable(dsidev, channel, false);
4366
4367                 /* MODE, 1 = video mode */
4368                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4369
4370                 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4371
4372                 dsi_vc_write_long_header(dsidev, channel, data_type,
4373                                 word_count, 0);
4374
4375                 dsi_vc_enable(dsidev, channel, true);
4376                 dsi_if_enable(dsidev, true);
4377         }
4378
4379         r = dss_mgr_enable(mgr);
4380         if (r) {
4381                 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4382                         dsi_if_enable(dsidev, false);
4383                         dsi_vc_enable(dsidev, channel, false);
4384                 }
4385
4386                 return r;
4387         }
4388
4389         return 0;
4390 }
4391 EXPORT_SYMBOL(dsi_enable_video_output);
4392
4393 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4394 {
4395         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4396         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4397         struct omap_overlay_manager *mgr = dssdev->output->manager;
4398
4399         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4400                 dsi_if_enable(dsidev, false);
4401                 dsi_vc_enable(dsidev, channel, false);
4402
4403                 /* MODE, 0 = command mode */
4404                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4405
4406                 dsi_vc_enable(dsidev, channel, true);
4407                 dsi_if_enable(dsidev, true);
4408         }
4409
4410         dss_mgr_disable(mgr);
4411 }
4412 EXPORT_SYMBOL(dsi_disable_video_output);
4413
4414 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev)
4415 {
4416         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4417         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4418         struct omap_overlay_manager *mgr = dssdev->output->manager;
4419         unsigned bytespp;
4420         unsigned bytespl;
4421         unsigned bytespf;
4422         unsigned total_len;
4423         unsigned packet_payload;
4424         unsigned packet_len;
4425         u32 l;
4426         int r;
4427         const unsigned channel = dsi->update_channel;
4428         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4429         u16 w = dsi->timings.x_res;
4430         u16 h = dsi->timings.y_res;
4431
4432         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4433
4434         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4435
4436         bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4437         bytespl = w * bytespp;
4438         bytespf = bytespl * h;
4439
4440         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4441          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4442
4443         if (bytespf < line_buf_size)
4444                 packet_payload = bytespf;
4445         else
4446                 packet_payload = (line_buf_size) / bytespl * bytespl;
4447
4448         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4449         total_len = (bytespf / packet_payload) * packet_len;
4450
4451         if (bytespf % packet_payload)
4452                 total_len += (bytespf % packet_payload) + 1;
4453
4454         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4455         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4456
4457         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4458                 packet_len, 0);
4459
4460         if (dsi->te_enabled)
4461                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4462         else
4463                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4464         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4465
4466         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4467          * because DSS interrupts are not capable of waking up the CPU and the
4468          * framedone interrupt could be delayed for quite a long time. I think
4469          * the same goes for any DSS interrupts, but for some reason I have not
4470          * seen the problem anywhere else than here.
4471          */
4472         dispc_disable_sidle();
4473
4474         dsi_perf_mark_start(dsidev);
4475
4476         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4477                 msecs_to_jiffies(250));
4478         BUG_ON(r == 0);
4479
4480         dss_mgr_set_timings(mgr, &dsi->timings);
4481
4482         dss_mgr_start_update(mgr);
4483
4484         if (dsi->te_enabled) {
4485                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4486                  * for TE is longer than the timer allows */
4487                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4488
4489                 dsi_vc_send_bta(dsidev, channel);
4490
4491 #ifdef DSI_CATCH_MISSING_TE
4492                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4493 #endif
4494         }
4495 }
4496
4497 #ifdef DSI_CATCH_MISSING_TE
4498 static void dsi_te_timeout(unsigned long arg)
4499 {
4500         DSSERR("TE not received for 250ms!\n");
4501 }
4502 #endif
4503
4504 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4505 {
4506         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4507
4508         /* SIDLEMODE back to smart-idle */
4509         dispc_enable_sidle();
4510
4511         if (dsi->te_enabled) {
4512                 /* enable LP_RX_TO again after the TE */
4513                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4514         }
4515
4516         dsi->framedone_callback(error, dsi->framedone_data);
4517
4518         if (!error)
4519                 dsi_perf_show(dsidev, "DISPC");
4520 }
4521
4522 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4523 {
4524         struct dsi_data *dsi = container_of(work, struct dsi_data,
4525                         framedone_timeout_work.work);
4526         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4527          * 250ms which would conflict with this timeout work. What should be
4528          * done is first cancel the transfer on the HW, and then cancel the
4529          * possibly scheduled framedone work. However, cancelling the transfer
4530          * on the HW is buggy, and would probably require resetting the whole
4531          * DSI */
4532
4533         DSSERR("Framedone not received for 250ms!\n");
4534
4535         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4536 }
4537
4538 static void dsi_framedone_irq_callback(void *data, u32 mask)
4539 {
4540         struct platform_device *dsidev = (struct platform_device *) data;
4541         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4542
4543         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4544          * turns itself off. However, DSI still has the pixels in its buffers,
4545          * and is sending the data.
4546          */
4547
4548         cancel_delayed_work(&dsi->framedone_timeout_work);
4549
4550         dsi_handle_framedone(dsidev, 0);
4551 }
4552
4553 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4554                 void (*callback)(int, void *), void *data)
4555 {
4556         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4557         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4558         u16 dw, dh;
4559
4560         dsi_perf_mark_setup(dsidev);
4561
4562         dsi->update_channel = channel;
4563
4564         dsi->framedone_callback = callback;
4565         dsi->framedone_data = data;
4566
4567         dw = dsi->timings.x_res;
4568         dh = dsi->timings.y_res;
4569
4570 #ifdef DEBUG
4571         dsi->update_bytes = dw * dh *
4572                 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4573 #endif
4574         dsi_update_screen_dispc(dssdev);
4575
4576         return 0;
4577 }
4578 EXPORT_SYMBOL(omap_dsi_update);
4579
4580 /* Display funcs */
4581
4582 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4583 {
4584         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4585         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4586         struct dispc_clock_info dispc_cinfo;
4587         int r;
4588         unsigned long long fck;
4589
4590         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4591
4592         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4593         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4594
4595         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4596         if (r) {
4597                 DSSERR("Failed to calc dispc clocks\n");
4598                 return r;
4599         }
4600
4601         dsi->mgr_config.clock_info = dispc_cinfo;
4602
4603         return 0;
4604 }
4605
4606 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4607 {
4608         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4609         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4610         struct omap_overlay_manager *mgr = dssdev->output->manager;
4611         int r;
4612         u32 irq = 0;
4613
4614         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4615                 dsi->timings.hsw = 1;
4616                 dsi->timings.hfp = 1;
4617                 dsi->timings.hbp = 1;
4618                 dsi->timings.vsw = 1;
4619                 dsi->timings.vfp = 0;
4620                 dsi->timings.vbp = 0;
4621
4622                 irq = dispc_mgr_get_framedone_irq(mgr->id);
4623
4624                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4625                         (void *) dsidev, irq);
4626                 if (r) {
4627                         DSSERR("can't get FRAMEDONE irq\n");
4628                         goto err;
4629                 }
4630
4631                 dsi->mgr_config.stallmode = true;
4632                 dsi->mgr_config.fifohandcheck = true;
4633         } else {
4634                 dsi->mgr_config.stallmode = false;
4635                 dsi->mgr_config.fifohandcheck = false;
4636         }
4637
4638         /*
4639          * override interlace, logic level and edge related parameters in
4640          * omap_video_timings with default values
4641          */
4642         dsi->timings.interlace = false;
4643         dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4644         dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4645         dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4646         dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4647         dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4648
4649         dss_mgr_set_timings(mgr, &dsi->timings);
4650
4651         r = dsi_configure_dispc_clocks(dssdev);
4652         if (r)
4653                 goto err1;
4654
4655         dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4656         dsi->mgr_config.video_port_width =
4657                         dsi_get_pixel_size(dsi->pix_fmt);
4658         dsi->mgr_config.lcden_sig_polarity = 0;
4659
4660         dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4661
4662         return 0;
4663 err1:
4664         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4665                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4666                         (void *) dsidev, irq);
4667 err:
4668         return r;
4669 }
4670
4671 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4672 {
4673         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4674         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4675         struct omap_overlay_manager *mgr = dssdev->output->manager;
4676
4677         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4678                 u32 irq;
4679
4680                 irq = dispc_mgr_get_framedone_irq(mgr->id);
4681
4682                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4683                         (void *) dsidev, irq);
4684         }
4685 }
4686
4687 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4688 {
4689         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4690         struct dsi_clock_info cinfo;
4691         int r;
4692
4693         cinfo.regn  = dssdev->clocks.dsi.regn;
4694         cinfo.regm  = dssdev->clocks.dsi.regm;
4695         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4696         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4697         r = dsi_calc_clock_rates(dsidev, &cinfo);
4698         if (r) {
4699                 DSSERR("Failed to calc dsi clocks\n");
4700                 return r;
4701         }
4702
4703         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4704         if (r) {
4705                 DSSERR("Failed to set dsi clocks\n");
4706                 return r;
4707         }
4708
4709         return 0;
4710 }
4711
4712 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4713 {
4714         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4715         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4716         struct omap_overlay_manager *mgr = dssdev->output->manager;
4717         int r;
4718
4719         r = dsi_pll_init(dsidev, true, true);
4720         if (r)
4721                 goto err0;
4722
4723         r = dsi_configure_dsi_clocks(dssdev);
4724         if (r)
4725                 goto err1;
4726
4727         dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
4728         dss_select_lcd_clk_source(mgr->id,
4729                         dssdev->clocks.dispc.channel.lcd_clk_src);
4730
4731         DSSDBG("PLL OK\n");
4732
4733         r = dsi_cio_init(dsidev);
4734         if (r)
4735                 goto err2;
4736
4737         _dsi_print_reset_status(dsidev);
4738
4739         dsi_proto_timings(dsidev);
4740         dsi_set_lp_clk_divisor(dssdev);
4741
4742         if (1)
4743                 _dsi_print_reset_status(dsidev);
4744
4745         r = dsi_proto_config(dssdev);
4746         if (r)
4747                 goto err3;
4748
4749         /* enable interface */
4750         dsi_vc_enable(dsidev, 0, 1);
4751         dsi_vc_enable(dsidev, 1, 1);
4752         dsi_vc_enable(dsidev, 2, 1);
4753         dsi_vc_enable(dsidev, 3, 1);
4754         dsi_if_enable(dsidev, 1);
4755         dsi_force_tx_stop_mode_io(dsidev);
4756
4757         return 0;
4758 err3:
4759         dsi_cio_uninit(dsidev);
4760 err2:
4761         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4762         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4763
4764 err1:
4765         dsi_pll_uninit(dsidev, true);
4766 err0:
4767         return r;
4768 }
4769
4770 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4771                 bool disconnect_lanes, bool enter_ulps)
4772 {
4773         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4774         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4775         struct omap_overlay_manager *mgr = dssdev->output->manager;
4776
4777         if (enter_ulps && !dsi->ulps_enabled)
4778                 dsi_enter_ulps(dsidev);
4779
4780         /* disable interface */
4781         dsi_if_enable(dsidev, 0);
4782         dsi_vc_enable(dsidev, 0, 0);
4783         dsi_vc_enable(dsidev, 1, 0);
4784         dsi_vc_enable(dsidev, 2, 0);
4785         dsi_vc_enable(dsidev, 3, 0);
4786
4787         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4788         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4789         dsi_cio_uninit(dsidev);
4790         dsi_pll_uninit(dsidev, disconnect_lanes);
4791 }
4792
4793 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4794 {
4795         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4796         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4797         struct omap_dss_output *out = dssdev->output;
4798         int r = 0;
4799
4800         DSSDBG("dsi_display_enable\n");
4801
4802         WARN_ON(!dsi_bus_is_locked(dsidev));
4803
4804         mutex_lock(&dsi->lock);
4805
4806         if (out == NULL || out->manager == NULL) {
4807                 DSSERR("failed to enable display: no output/manager\n");
4808                 r = -ENODEV;
4809                 goto err_start_dev;
4810         }
4811
4812         r = omap_dss_start_device(dssdev);
4813         if (r) {
4814                 DSSERR("failed to start device\n");
4815                 goto err_start_dev;
4816         }
4817
4818         r = dsi_runtime_get(dsidev);
4819         if (r)
4820                 goto err_get_dsi;
4821
4822         dsi_enable_pll_clock(dsidev, 1);
4823
4824         _dsi_initialize_irq(dsidev);
4825
4826         r = dsi_display_init_dispc(dssdev);
4827         if (r)
4828                 goto err_init_dispc;
4829
4830         r = dsi_display_init_dsi(dssdev);
4831         if (r)
4832                 goto err_init_dsi;
4833
4834         mutex_unlock(&dsi->lock);
4835
4836         return 0;
4837
4838 err_init_dsi:
4839         dsi_display_uninit_dispc(dssdev);
4840 err_init_dispc:
4841         dsi_enable_pll_clock(dsidev, 0);
4842         dsi_runtime_put(dsidev);
4843 err_get_dsi:
4844         omap_dss_stop_device(dssdev);
4845 err_start_dev:
4846         mutex_unlock(&dsi->lock);
4847         DSSDBG("dsi_display_enable FAILED\n");
4848         return r;
4849 }
4850 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4851
4852 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4853                 bool disconnect_lanes, bool enter_ulps)
4854 {
4855         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4856         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4857
4858         DSSDBG("dsi_display_disable\n");
4859
4860         WARN_ON(!dsi_bus_is_locked(dsidev));
4861
4862         mutex_lock(&dsi->lock);
4863
4864         dsi_sync_vc(dsidev, 0);
4865         dsi_sync_vc(dsidev, 1);
4866         dsi_sync_vc(dsidev, 2);
4867         dsi_sync_vc(dsidev, 3);
4868
4869         dsi_display_uninit_dispc(dssdev);
4870
4871         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4872
4873         dsi_runtime_put(dsidev);
4874         dsi_enable_pll_clock(dsidev, 0);
4875
4876         omap_dss_stop_device(dssdev);
4877
4878         mutex_unlock(&dsi->lock);
4879 }
4880 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4881
4882 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4883 {
4884         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4885         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4886
4887         dsi->te_enabled = enable;
4888         return 0;
4889 }
4890 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4891
4892 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
4893                 struct omap_video_timings *timings)
4894 {
4895         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4896         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4897
4898         mutex_lock(&dsi->lock);
4899
4900         dsi->timings = *timings;
4901
4902         mutex_unlock(&dsi->lock);
4903 }
4904 EXPORT_SYMBOL(omapdss_dsi_set_timings);
4905
4906 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
4907 {
4908         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4909         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4910
4911         mutex_lock(&dsi->lock);
4912
4913         dsi->timings.x_res = w;
4914         dsi->timings.y_res = h;
4915
4916         mutex_unlock(&dsi->lock);
4917 }
4918 EXPORT_SYMBOL(omapdss_dsi_set_size);
4919
4920 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
4921                 enum omap_dss_dsi_pixel_format fmt)
4922 {
4923         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4924         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4925
4926         mutex_lock(&dsi->lock);
4927
4928         dsi->pix_fmt = fmt;
4929
4930         mutex_unlock(&dsi->lock);
4931 }
4932 EXPORT_SYMBOL(omapdss_dsi_set_pixel_format);
4933
4934 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
4935                 enum omap_dss_dsi_mode mode)
4936 {
4937         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4938         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4939
4940         mutex_lock(&dsi->lock);
4941
4942         dsi->mode = mode;
4943
4944         mutex_unlock(&dsi->lock);
4945 }
4946 EXPORT_SYMBOL(omapdss_dsi_set_operation_mode);
4947
4948 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
4949                 struct omap_dss_dsi_videomode_timings *timings)
4950 {
4951         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4952         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4953
4954         mutex_lock(&dsi->lock);
4955
4956         dsi->vm_timings = *timings;
4957
4958         mutex_unlock(&dsi->lock);
4959 }
4960 EXPORT_SYMBOL(omapdss_dsi_set_videomode_timings);
4961
4962 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4963 {
4964         struct platform_device *dsidev =
4965                         dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
4966         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4967
4968         DSSDBG("DSI init\n");
4969
4970         if (dsi->vdds_dsi_reg == NULL) {
4971                 struct regulator *vdds_dsi;
4972
4973                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4974
4975                 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
4976                 if (IS_ERR(vdds_dsi))
4977                         vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
4978
4979                 if (IS_ERR(vdds_dsi)) {
4980                         DSSERR("can't get VDDS_DSI regulator\n");
4981                         return PTR_ERR(vdds_dsi);
4982                 }
4983
4984                 dsi->vdds_dsi_reg = vdds_dsi;
4985         }
4986
4987         return 0;
4988 }
4989
4990 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4991 {
4992         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4993         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4994         int i;
4995
4996         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4997                 if (!dsi->vc[i].dssdev) {
4998                         dsi->vc[i].dssdev = dssdev;
4999                         *channel = i;
5000                         return 0;
5001                 }
5002         }
5003
5004         DSSERR("cannot get VC for display %s", dssdev->name);
5005         return -ENOSPC;
5006 }
5007 EXPORT_SYMBOL(omap_dsi_request_vc);
5008
5009 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5010 {
5011         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5012         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5013
5014         if (vc_id < 0 || vc_id > 3) {
5015                 DSSERR("VC ID out of range\n");
5016                 return -EINVAL;
5017         }
5018
5019         if (channel < 0 || channel > 3) {
5020                 DSSERR("Virtual Channel out of range\n");
5021                 return -EINVAL;
5022         }
5023
5024         if (dsi->vc[channel].dssdev != dssdev) {
5025                 DSSERR("Virtual Channel not allocated to display %s\n",
5026                         dssdev->name);
5027                 return -EINVAL;
5028         }
5029
5030         dsi->vc[channel].vc_id = vc_id;
5031
5032         return 0;
5033 }
5034 EXPORT_SYMBOL(omap_dsi_set_vc_id);
5035
5036 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5037 {
5038         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5039         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5040
5041         if ((channel >= 0 && channel <= 3) &&
5042                 dsi->vc[channel].dssdev == dssdev) {
5043                 dsi->vc[channel].dssdev = NULL;
5044                 dsi->vc[channel].vc_id = 0;
5045         }
5046 }
5047 EXPORT_SYMBOL(omap_dsi_release_vc);
5048
5049 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5050 {
5051         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5052                 DSSERR("%s (%s) not active\n",
5053                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5054                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5055 }
5056
5057 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5058 {
5059         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5060                 DSSERR("%s (%s) not active\n",
5061                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5062                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5063 }
5064
5065 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5066 {
5067         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5068
5069         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5070         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5071         dsi->regm_dispc_max =
5072                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5073         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5074         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5075         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5076         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5077 }
5078
5079 static int dsi_get_clocks(struct platform_device *dsidev)
5080 {
5081         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5082         struct clk *clk;
5083
5084         clk = clk_get(&dsidev->dev, "fck");
5085         if (IS_ERR(clk)) {
5086                 DSSERR("can't get fck\n");
5087                 return PTR_ERR(clk);
5088         }
5089
5090         dsi->dss_clk = clk;
5091
5092         clk = clk_get(&dsidev->dev, "sys_clk");
5093         if (IS_ERR(clk)) {
5094                 DSSERR("can't get sys_clk\n");
5095                 clk_put(dsi->dss_clk);
5096                 dsi->dss_clk = NULL;
5097                 return PTR_ERR(clk);
5098         }
5099
5100         dsi->sys_clk = clk;
5101
5102         return 0;
5103 }
5104
5105 static void dsi_put_clocks(struct platform_device *dsidev)
5106 {
5107         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5108
5109         if (dsi->dss_clk)
5110                 clk_put(dsi->dss_clk);
5111         if (dsi->sys_clk)
5112                 clk_put(dsi->sys_clk);
5113 }
5114
5115 static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev)
5116 {
5117         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5118         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5119         const char *def_disp_name = omapdss_get_default_display_name();
5120         struct omap_dss_device *def_dssdev;
5121         int i;
5122
5123         def_dssdev = NULL;
5124
5125         for (i = 0; i < pdata->num_devices; ++i) {
5126                 struct omap_dss_device *dssdev = pdata->devices[i];
5127
5128                 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5129                         continue;
5130
5131                 if (dssdev->phy.dsi.module != dsi->module_id)
5132                         continue;
5133
5134                 if (def_dssdev == NULL)
5135                         def_dssdev = dssdev;
5136
5137                 if (def_disp_name != NULL &&
5138                                 strcmp(dssdev->name, def_disp_name) == 0) {
5139                         def_dssdev = dssdev;
5140                         break;
5141                 }
5142         }
5143
5144         return def_dssdev;
5145 }
5146
5147 static void __init dsi_probe_pdata(struct platform_device *dsidev)
5148 {
5149         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5150         struct omap_dss_device *plat_dssdev;
5151         struct omap_dss_device *dssdev;
5152         int r;
5153
5154         plat_dssdev = dsi_find_dssdev(dsidev);
5155
5156         if (!plat_dssdev)
5157                 return;
5158
5159         dssdev = dss_alloc_and_init_device(&dsidev->dev);
5160         if (!dssdev)
5161                 return;
5162
5163         dss_copy_device_pdata(dssdev, plat_dssdev);
5164
5165         r = dsi_init_display(dssdev);
5166         if (r) {
5167                 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5168                 dss_put_device(dssdev);
5169                 return;
5170         }
5171
5172         r = omapdss_output_set_device(&dsi->output, dssdev);
5173         if (r) {
5174                 DSSERR("failed to connect output to new device: %s\n",
5175                                 dssdev->name);
5176                 dss_put_device(dssdev);
5177                 return;
5178         }
5179
5180         r = dss_add_device(dssdev);
5181         if (r) {
5182                 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5183                 omapdss_output_unset_device(&dsi->output);
5184                 dss_put_device(dssdev);
5185                 return;
5186         }
5187 }
5188
5189 static void __init dsi_init_output(struct platform_device *dsidev)
5190 {
5191         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5192         struct omap_dss_output *out = &dsi->output;
5193
5194         out->pdev = dsidev;
5195         out->id = dsi->module_id == 0 ?
5196                         OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5197
5198         out->type = OMAP_DISPLAY_TYPE_DSI;
5199
5200         dss_register_output(out);
5201 }
5202
5203 static void __exit dsi_uninit_output(struct platform_device *dsidev)
5204 {
5205         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5206         struct omap_dss_output *out = &dsi->output;
5207
5208         dss_unregister_output(out);
5209 }
5210
5211 /* DSI1 HW IP initialisation */
5212 static int __init omap_dsihw_probe(struct platform_device *dsidev)
5213 {
5214         u32 rev;
5215         int r, i;
5216         struct resource *dsi_mem;
5217         struct dsi_data *dsi;
5218
5219         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5220         if (!dsi)
5221                 return -ENOMEM;
5222
5223         dsi->module_id = dsidev->id;
5224         dsi->pdev = dsidev;
5225         dev_set_drvdata(&dsidev->dev, dsi);
5226
5227         spin_lock_init(&dsi->irq_lock);
5228         spin_lock_init(&dsi->errors_lock);
5229         dsi->errors = 0;
5230
5231 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5232         spin_lock_init(&dsi->irq_stats_lock);
5233         dsi->irq_stats.last_reset = jiffies;
5234 #endif
5235
5236         mutex_init(&dsi->lock);
5237         sema_init(&dsi->bus_lock, 1);
5238
5239         INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5240                              dsi_framedone_timeout_work_callback);
5241
5242 #ifdef DSI_CATCH_MISSING_TE
5243         init_timer(&dsi->te_timer);
5244         dsi->te_timer.function = dsi_te_timeout;
5245         dsi->te_timer.data = 0;
5246 #endif
5247         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5248         if (!dsi_mem) {
5249                 DSSERR("can't get IORESOURCE_MEM DSI\n");
5250                 return -EINVAL;
5251         }
5252
5253         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5254                                  resource_size(dsi_mem));
5255         if (!dsi->base) {
5256                 DSSERR("can't ioremap DSI\n");
5257                 return -ENOMEM;
5258         }
5259
5260         dsi->irq = platform_get_irq(dsi->pdev, 0);
5261         if (dsi->irq < 0) {
5262                 DSSERR("platform_get_irq failed\n");
5263                 return -ENODEV;
5264         }
5265
5266         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5267                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5268         if (r < 0) {
5269                 DSSERR("request_irq failed\n");
5270                 return r;
5271         }
5272
5273         /* DSI VCs initialization */
5274         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5275                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5276                 dsi->vc[i].dssdev = NULL;
5277                 dsi->vc[i].vc_id = 0;
5278         }
5279
5280         dsi_calc_clock_param_ranges(dsidev);
5281
5282         r = dsi_get_clocks(dsidev);
5283         if (r)
5284                 return r;
5285
5286         pm_runtime_enable(&dsidev->dev);
5287
5288         r = dsi_runtime_get(dsidev);
5289         if (r)
5290                 goto err_runtime_get;
5291
5292         rev = dsi_read_reg(dsidev, DSI_REVISION);
5293         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5294                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5295
5296         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5297          * of data to 3 by default */
5298         if (dss_has_feature(FEAT_DSI_GNQ))
5299                 /* NB_DATA_LANES */
5300                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5301         else
5302                 dsi->num_lanes_supported = 3;
5303
5304         dsi_init_output(dsidev);
5305
5306         dsi_probe_pdata(dsidev);
5307
5308         dsi_runtime_put(dsidev);
5309
5310         if (dsi->module_id == 0)
5311                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5312         else if (dsi->module_id == 1)
5313                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5314
5315 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5316         if (dsi->module_id == 0)
5317                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5318         else if (dsi->module_id == 1)
5319                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5320 #endif
5321         return 0;
5322
5323 err_runtime_get:
5324         pm_runtime_disable(&dsidev->dev);
5325         dsi_put_clocks(dsidev);
5326         return r;
5327 }
5328
5329 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5330 {
5331         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5332
5333         WARN_ON(dsi->scp_clk_refcount > 0);
5334
5335         dss_unregister_child_devices(&dsidev->dev);
5336
5337         dsi_uninit_output(dsidev);
5338
5339         pm_runtime_disable(&dsidev->dev);
5340
5341         dsi_put_clocks(dsidev);
5342
5343         if (dsi->vdds_dsi_reg != NULL) {
5344                 if (dsi->vdds_dsi_enabled) {
5345                         regulator_disable(dsi->vdds_dsi_reg);
5346                         dsi->vdds_dsi_enabled = false;
5347                 }
5348
5349                 regulator_put(dsi->vdds_dsi_reg);
5350                 dsi->vdds_dsi_reg = NULL;
5351         }
5352
5353         return 0;
5354 }
5355
5356 static int dsi_runtime_suspend(struct device *dev)
5357 {
5358         dispc_runtime_put();
5359
5360         return 0;
5361 }
5362
5363 static int dsi_runtime_resume(struct device *dev)
5364 {
5365         int r;
5366
5367         r = dispc_runtime_get();
5368         if (r)
5369                 return r;
5370
5371         return 0;
5372 }
5373
5374 static const struct dev_pm_ops dsi_pm_ops = {
5375         .runtime_suspend = dsi_runtime_suspend,
5376         .runtime_resume = dsi_runtime_resume,
5377 };
5378
5379 static struct platform_driver omap_dsihw_driver = {
5380         .remove         = __exit_p(omap_dsihw_remove),
5381         .driver         = {
5382                 .name   = "omapdss_dsi",
5383                 .owner  = THIS_MODULE,
5384                 .pm     = &dsi_pm_ops,
5385         },
5386 };
5387
5388 int __init dsi_init_platform_driver(void)
5389 {
5390         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
5391 }
5392
5393 void __exit dsi_uninit_platform_driver(void)
5394 {
5395         platform_driver_unregister(&omap_dsihw_driver);
5396 }