drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47
  48 /*#define VERBOSE_IRQ*/
  49 #define DSI_CATCH_MISSING_TE
  50
  51 struct dsi_reg { u16 idx; };
  52
  53 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  54
  55 #define DSI_SZ_REGS             SZ_1K
  56 /* DSI Protocol Engine */
  57
  58 #define DSI_REVISION                    DSI_REG(0x0000)
  59 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  60 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  61 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  62 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  63 #define DSI_CTRL                        DSI_REG(0x0040)
  64 #define DSI_GNQ                         DSI_REG(0x0044)
  65 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  66 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  67 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  68 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  69 #define DSI_TIMING1                     DSI_REG(0x0058)
  70 #define DSI_TIMING2                     DSI_REG(0x005C)
  71 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  72 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  73 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  74 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  75 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  76 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  77 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  78 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  79 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  80 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  81 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  82 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  83 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  84 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  85 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  86 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  87 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  89 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  90 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  91 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  92
  93 /* DSIPHY_SCP */
  94
  95 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  96 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  97 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  98 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
  99 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 100
 101 /* DSI_PLL_CTRL_SCP */
 102
 103 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 104 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 105 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 106 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 107 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 108
 109 #define REG_GET(dsidev, idx, start, end) \
 110         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 111
 112 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 113         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 114
 115 /* Global interrupts */
 116 #define DSI_IRQ_VC0             (1 << 0)
 117 #define DSI_IRQ_VC1             (1 << 1)
 118 #define DSI_IRQ_VC2             (1 << 2)
 119 #define DSI_IRQ_VC3             (1 << 3)
 120 #define DSI_IRQ_WAKEUP          (1 << 4)
 121 #define DSI_IRQ_RESYNC          (1 << 5)
 122 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 123 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 124 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 125 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 126 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 127 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 128 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 129 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 130 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 131 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 132 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 133 #define DSI_IRQ_ERROR_MASK \
 134         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 135         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 136 #define DSI_IRQ_CHANNEL_MASK    0xf
 137
 138 /* Virtual channel interrupts */
 139 #define DSI_VC_IRQ_CS           (1 << 0)
 140 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 141 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 142 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 143 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 144 #define DSI_VC_IRQ_BTA          (1 << 5)
 145 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 146 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 147 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 148 #define DSI_VC_IRQ_ERROR_MASK \
 149         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 150         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 151         DSI_VC_IRQ_FIFO_TX_UDF)
 152
 153 /* ComplexIO interrupts */
 154 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 155 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 156 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 157 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 158 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 159 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 160 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 161 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 162 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 163 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 164 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 165 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 166 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 167 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 168 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 169 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 170 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 171 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 172 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 173 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 174 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 186 #define DSI_CIO_IRQ_ERROR_MASK \
 187         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 188          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 189          DSI_CIO_IRQ_ERRSYNCESC5 | \
 190          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 191          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 192          DSI_CIO_IRQ_ERRESC5 | \
 193          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 194          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 195          DSI_CIO_IRQ_ERRCONTROL5 | \
 196          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 201
 202 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 203
 204 #define DSI_MAX_NR_ISRS                2
 205 #define DSI_MAX_NR_LANES        5
 206
 207 enum dsi_lane_function {
 208         DSI_LANE_UNUSED = 0,
 209         DSI_LANE_CLK,
 210         DSI_LANE_DATA1,
 211         DSI_LANE_DATA2,
 212         DSI_LANE_DATA3,
 213         DSI_LANE_DATA4,
 214 };
 215
 216 struct dsi_lane_config {
 217         enum dsi_lane_function function;
 218         u8 polarity;
 219 };
 220
 221 struct dsi_isr_data {
 222         omap_dsi_isr_t  isr;
 223         void            *arg;
 224         u32             mask;
 225 };
 226
 227 enum fifo_size {
 228         DSI_FIFO_SIZE_0         = 0,
 229         DSI_FIFO_SIZE_32        = 1,
 230         DSI_FIFO_SIZE_64        = 2,
 231         DSI_FIFO_SIZE_96        = 3,
 232         DSI_FIFO_SIZE_128       = 4,
 233 };
 234
 235 enum dsi_vc_source {
 236         DSI_VC_SOURCE_L4 = 0,
 237         DSI_VC_SOURCE_VP,
 238 };
 239
 240 struct dsi_irq_stats {
 241         unsigned long last_reset;
 242         unsigned irq_count;
 243         unsigned dsi_irqs[32];
 244         unsigned vc_irqs[4][32];
 245         unsigned cio_irqs[32];
 246 };
 247
 248 struct dsi_isr_tables {
 249         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 250         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 252 };
 253
 254 struct dsi_data {
 255         struct platform_device *pdev;
 256         void __iomem    *base;
 257
 258         int module_id;
 259
 260         int irq;
 261
 262         struct clk *dss_clk;
 263         struct clk *sys_clk;
 264
 265         struct dsi_clock_info current_cinfo;
 266
 267         bool vdds_dsi_enabled;
 268         struct regulator *vdds_dsi_reg;
 269
 270         struct {
 271                 enum dsi_vc_source source;
 272                 struct omap_dss_device *dssdev;
 273                 enum fifo_size fifo_size;
 274                 int vc_id;
 275         } vc[4];
 276
 277         struct mutex lock;
 278         struct semaphore bus_lock;
 279
 280         unsigned pll_locked;
 281
 282         spinlock_t irq_lock;
 283         struct dsi_isr_tables isr_tables;
 284         /* space for a copy used by the interrupt handler */
 285         struct dsi_isr_tables isr_tables_copy;
 286
 287         int update_channel;
 288 #ifdef DEBUG
 289         unsigned update_bytes;
 290 #endif
 291
 292         bool te_enabled;
 293         bool ulps_enabled;
 294
 295         void (*framedone_callback)(int, void *);
 296         void *framedone_data;
 297
 298         struct delayed_work framedone_timeout_work;
 299
 300 #ifdef DSI_CATCH_MISSING_TE
 301         struct timer_list te_timer;
 302 #endif
 303
 304         unsigned long cache_req_pck;
 305         unsigned long cache_clk_freq;
 306         struct dsi_clock_info cache_cinfo;
 307
 308         u32             errors;
 309         spinlock_t      errors_lock;
 310 #ifdef DEBUG
 311         ktime_t perf_setup_time;
 312         ktime_t perf_start_time;
 313 #endif
 314         int debug_read;
 315         int debug_write;
 316
 317 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 318         spinlock_t irq_stats_lock;
 319         struct dsi_irq_stats irq_stats;
 320 #endif
 321         /* DSI PLL Parameter Ranges */
 322         unsigned long regm_max, regn_max;
 323         unsigned long  regm_dispc_max, regm_dsi_max;
 324         unsigned long  fint_min, fint_max;
 325         unsigned long lpdiv_max;
 326
 327         unsigned num_lanes_supported;
 328
 329         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 330         unsigned num_lanes_used;
 331
 332         unsigned scp_clk_refcount;
 333
 334         struct dss_lcd_mgr_config mgr_config;
 335         struct omap_video_timings timings;
 336         enum omap_dss_dsi_pixel_format pix_fmt;
 337         enum omap_dss_dsi_mode mode;
 338         struct omap_dss_dsi_videomode_timings vm_timings;
 339
 340         struct omap_dss_output output;
 341 };
 342
 343 struct dsi_packet_sent_handler_data {
 344         struct platform_device *dsidev;
 345         struct completion *completion;
 346 };
 347
 348 #ifdef DEBUG
 349 static bool dsi_perf;
 350 module_param(dsi_perf, bool, 0644);
 351 #endif
 352
 353 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 354 {
 355         return dev_get_drvdata(&dsidev->dev);
 356 }
 357
 358 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 359 {
 360         return dssdev->output->pdev;
 361 }
 362
 363 struct platform_device *dsi_get_dsidev_from_id(int module)
 364 {
 365         struct omap_dss_output *out;
 366         enum omap_dss_output_id id;
 367
 368         id = module == 0 ? OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
 369
 370         out = omap_dss_get_output(id);
 371
 372         return out->pdev;
 373 }
 374
 375 static inline void dsi_write_reg(struct platform_device *dsidev,
 376                 const struct dsi_reg idx, u32 val)
 377 {
 378         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 379
 380         __raw_writel(val, dsi->base + idx.idx);
 381 }
 382
 383 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 384                 const struct dsi_reg idx)
 385 {
 386         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 387
 388         return __raw_readl(dsi->base + idx.idx);
 389 }
 390
 391 void dsi_bus_lock(struct omap_dss_device *dssdev)
 392 {
 393         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 394         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 395
 396         down(&dsi->bus_lock);
 397 }
 398 EXPORT_SYMBOL(dsi_bus_lock);
 399
 400 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 401 {
 402         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 403         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 404
 405         up(&dsi->bus_lock);
 406 }
 407 EXPORT_SYMBOL(dsi_bus_unlock);
 408
 409 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 410 {
 411         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 412
 413         return dsi->bus_lock.count == 0;
 414 }
 415
 416 static void dsi_completion_handler(void *data, u32 mask)
 417 {
 418         complete((struct completion *)data);
 419 }
 420
 421 static inline int wait_for_bit_change(struct platform_device *dsidev,
 422                 const struct dsi_reg idx, int bitnum, int value)
 423 {
 424         unsigned long timeout;
 425         ktime_t wait;
 426         int t;
 427
 428         /* first busyloop to see if the bit changes right away */
 429         t = 100;
 430         while (t-- > 0) {
 431                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 432                         return value;
 433         }
 434
 435         /* then loop for 500ms, sleeping for 1ms in between */
 436         timeout = jiffies + msecs_to_jiffies(500);
 437         while (time_before(jiffies, timeout)) {
 438                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 439                         return value;
 440
 441                 wait = ns_to_ktime(1000 * 1000);
 442                 set_current_state(TASK_UNINTERRUPTIBLE);
 443                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 444         }
 445
 446         return !value;
 447 }
 448
 449 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 450 {
 451         switch (fmt) {
 452         case OMAP_DSS_DSI_FMT_RGB888:
 453         case OMAP_DSS_DSI_FMT_RGB666:
 454                 return 24;
 455         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 456                 return 18;
 457         case OMAP_DSS_DSI_FMT_RGB565:
 458                 return 16;
 459         default:
 460                 BUG();
 461                 return 0;
 462         }
 463 }
 464
 465 #ifdef DEBUG
 466 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 467 {
 468         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 469         dsi->perf_setup_time = ktime_get();
 470 }
 471
 472 static void dsi_perf_mark_start(struct platform_device *dsidev)
 473 {
 474         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 475         dsi->perf_start_time = ktime_get();
 476 }
 477
 478 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 479 {
 480         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 481         ktime_t t, setup_time, trans_time;
 482         u32 total_bytes;
 483         u32 setup_us, trans_us, total_us;
 484
 485         if (!dsi_perf)
 486                 return;
 487
 488         t = ktime_get();
 489
 490         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 491         setup_us = (u32)ktime_to_us(setup_time);
 492         if (setup_us == 0)
 493                 setup_us = 1;
 494
 495         trans_time = ktime_sub(t, dsi->perf_start_time);
 496         trans_us = (u32)ktime_to_us(trans_time);
 497         if (trans_us == 0)
 498                 trans_us = 1;
 499
 500         total_us = setup_us + trans_us;
 501
 502         total_bytes = dsi->update_bytes;
 503
 504         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 505                         "%u bytes, %u kbytes/sec\n",
 506                         name,
 507                         setup_us,
 508                         trans_us,
 509                         total_us,
 510                         1000*1000 / total_us,
 511                         total_bytes,
 512                         total_bytes * 1000 / total_us);
 513 }
 514 #else
 515 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 516 {
 517 }
 518
 519 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 520 {
 521 }
 522
 523 static inline void dsi_perf_show(struct platform_device *dsidev,
 524                 const char *name)
 525 {
 526 }
 527 #endif
 528
 529 static void print_irq_status(u32 status)
 530 {
 531         if (status == 0)
 532                 return;
 533
 534 #ifndef VERBOSE_IRQ
 535         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 536                 return;
 537 #endif
 538         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 539
 540 #define PIS(x) \
 541         if (status & DSI_IRQ_##x) \
 542                 printk(#x " ");
 543 #ifdef VERBOSE_IRQ
 544         PIS(VC0);
 545         PIS(VC1);
 546         PIS(VC2);
 547         PIS(VC3);
 548 #endif
 549         PIS(WAKEUP);
 550         PIS(RESYNC);
 551         PIS(PLL_LOCK);
 552         PIS(PLL_UNLOCK);
 553         PIS(PLL_RECALL);
 554         PIS(COMPLEXIO_ERR);
 555         PIS(HS_TX_TIMEOUT);
 556         PIS(LP_RX_TIMEOUT);
 557         PIS(TE_TRIGGER);
 558         PIS(ACK_TRIGGER);
 559         PIS(SYNC_LOST);
 560         PIS(LDO_POWER_GOOD);
 561         PIS(TA_TIMEOUT);
 562 #undef PIS
 563
 564         printk("\n");
 565 }
 566
 567 static void print_irq_status_vc(int channel, u32 status)
 568 {
 569         if (status == 0)
 570                 return;
 571
 572 #ifndef VERBOSE_IRQ
 573         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 574                 return;
 575 #endif
 576         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 577
 578 #define PIS(x) \
 579         if (status & DSI_VC_IRQ_##x) \
 580                 printk(#x " ");
 581         PIS(CS);
 582         PIS(ECC_CORR);
 583 #ifdef VERBOSE_IRQ
 584         PIS(PACKET_SENT);
 585 #endif
 586         PIS(FIFO_TX_OVF);
 587         PIS(FIFO_RX_OVF);
 588         PIS(BTA);
 589         PIS(ECC_NO_CORR);
 590         PIS(FIFO_TX_UDF);
 591         PIS(PP_BUSY_CHANGE);
 592 #undef PIS
 593         printk("\n");
 594 }
 595
 596 static void print_irq_status_cio(u32 status)
 597 {
 598         if (status == 0)
 599                 return;
 600
 601         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 602
 603 #define PIS(x) \
 604         if (status & DSI_CIO_IRQ_##x) \
 605                 printk(#x " ");
 606         PIS(ERRSYNCESC1);
 607         PIS(ERRSYNCESC2);
 608         PIS(ERRSYNCESC3);
 609         PIS(ERRESC1);
 610         PIS(ERRESC2);
 611         PIS(ERRESC3);
 612         PIS(ERRCONTROL1);
 613         PIS(ERRCONTROL2);
 614         PIS(ERRCONTROL3);
 615         PIS(STATEULPS1);
 616         PIS(STATEULPS2);
 617         PIS(STATEULPS3);
 618         PIS(ERRCONTENTIONLP0_1);
 619         PIS(ERRCONTENTIONLP1_1);
 620         PIS(ERRCONTENTIONLP0_2);
 621         PIS(ERRCONTENTIONLP1_2);
 622         PIS(ERRCONTENTIONLP0_3);
 623         PIS(ERRCONTENTIONLP1_3);
 624         PIS(ULPSACTIVENOT_ALL0);
 625         PIS(ULPSACTIVENOT_ALL1);
 626 #undef PIS
 627
 628         printk("\n");
 629 }
 630
 631 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 632 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 633                 u32 *vcstatus, u32 ciostatus)
 634 {
 635         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 636         int i;
 637
 638         spin_lock(&dsi->irq_stats_lock);
 639
 640         dsi->irq_stats.irq_count++;
 641         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 642
 643         for (i = 0; i < 4; ++i)
 644                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 645
 646         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 647
 648         spin_unlock(&dsi->irq_stats_lock);
 649 }
 650 #else
 651 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 652 #endif
 653
 654 static int debug_irq;
 655
 656 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 657                 u32 *vcstatus, u32 ciostatus)
 658 {
 659         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 660         int i;
 661
 662         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 663                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 664                 print_irq_status(irqstatus);
 665                 spin_lock(&dsi->errors_lock);
 666                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 667                 spin_unlock(&dsi->errors_lock);
 668         } else if (debug_irq) {
 669                 print_irq_status(irqstatus);
 670         }
 671
 672         for (i = 0; i < 4; ++i) {
 673                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 674                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 675                                        i, vcstatus[i]);
 676                         print_irq_status_vc(i, vcstatus[i]);
 677                 } else if (debug_irq) {
 678                         print_irq_status_vc(i, vcstatus[i]);
 679                 }
 680         }
 681
 682         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 683                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 684                 print_irq_status_cio(ciostatus);
 685         } else if (debug_irq) {
 686                 print_irq_status_cio(ciostatus);
 687         }
 688 }
 689
 690 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 691                 unsigned isr_array_size, u32 irqstatus)
 692 {
 693         struct dsi_isr_data *isr_data;
 694         int i;
 695
 696         for (i = 0; i < isr_array_size; i++) {
 697                 isr_data = &isr_array[i];
 698                 if (isr_data->isr && isr_data->mask & irqstatus)
 699                         isr_data->isr(isr_data->arg, irqstatus);
 700         }
 701 }
 702
 703 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 704                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 705 {
 706         int i;
 707
 708         dsi_call_isrs(isr_tables->isr_table,
 709                         ARRAY_SIZE(isr_tables->isr_table),
 710                         irqstatus);
 711
 712         for (i = 0; i < 4; ++i) {
 713                 if (vcstatus[i] == 0)
 714                         continue;
 715                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 716                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 717                                 vcstatus[i]);
 718         }
 719
 720         if (ciostatus != 0)
 721                 dsi_call_isrs(isr_tables->isr_table_cio,
 722                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 723                                 ciostatus);
 724 }
 725
 726 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 727 {
 728         struct platform_device *dsidev;
 729         struct dsi_data *dsi;
 730         u32 irqstatus, vcstatus[4], ciostatus;
 731         int i;
 732
 733         dsidev = (struct platform_device *) arg;
 734         dsi = dsi_get_dsidrv_data(dsidev);
 735
 736         spin_lock(&dsi->irq_lock);
 737
 738         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 739
 740         /* IRQ is not for us */
 741         if (!irqstatus) {
 742                 spin_unlock(&dsi->irq_lock);
 743                 return IRQ_NONE;
 744         }
 745
 746         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 747         /* flush posted write */
 748         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 749
 750         for (i = 0; i < 4; ++i) {
 751                 if ((irqstatus & (1 << i)) == 0) {
 752                         vcstatus[i] = 0;
 753                         continue;
 754                 }
 755
 756                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 757
 758                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 759                 /* flush posted write */
 760                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 761         }
 762
 763         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 764                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 765
 766                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 767                 /* flush posted write */
 768                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 769         } else {
 770                 ciostatus = 0;
 771         }
 772
 773 #ifdef DSI_CATCH_MISSING_TE
 774         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 775                 del_timer(&dsi->te_timer);
 776 #endif
 777
 778         /* make a copy and unlock, so that isrs can unregister
 779          * themselves */
 780         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 781                 sizeof(dsi->isr_tables));
 782
 783         spin_unlock(&dsi->irq_lock);
 784
 785         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 786
 787         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 788
 789         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 790
 791         return IRQ_HANDLED;
 792 }
 793
 794 /* dsi->irq_lock has to be locked by the caller */
 795 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 796                 struct dsi_isr_data *isr_array,
 797                 unsigned isr_array_size, u32 default_mask,
 798                 const struct dsi_reg enable_reg,
 799                 const struct dsi_reg status_reg)
 800 {
 801         struct dsi_isr_data *isr_data;
 802         u32 mask;
 803         u32 old_mask;
 804         int i;
 805
 806         mask = default_mask;
 807
 808         for (i = 0; i < isr_array_size; i++) {
 809                 isr_data = &isr_array[i];
 810
 811                 if (isr_data->isr == NULL)
 812                         continue;
 813
 814                 mask |= isr_data->mask;
 815         }
 816
 817         old_mask = dsi_read_reg(dsidev, enable_reg);
 818         /* clear the irqstatus for newly enabled irqs */
 819         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 820         dsi_write_reg(dsidev, enable_reg, mask);
 821
 822         /* flush posted writes */
 823         dsi_read_reg(dsidev, enable_reg);
 824         dsi_read_reg(dsidev, status_reg);
 825 }
 826
 827 /* dsi->irq_lock has to be locked by the caller */
 828 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 829 {
 830         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 831         u32 mask = DSI_IRQ_ERROR_MASK;
 832 #ifdef DSI_CATCH_MISSING_TE
 833         mask |= DSI_IRQ_TE_TRIGGER;
 834 #endif
 835         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 836                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 837                         DSI_IRQENABLE, DSI_IRQSTATUS);
 838 }
 839
 840 /* dsi->irq_lock has to be locked by the caller */
 841 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 842 {
 843         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 844
 845         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 846                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 847                         DSI_VC_IRQ_ERROR_MASK,
 848                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 849 }
 850
 851 /* dsi->irq_lock has to be locked by the caller */
 852 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 853 {
 854         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 855
 856         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 857                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 858                         DSI_CIO_IRQ_ERROR_MASK,
 859                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 860 }
 861
 862 static void _dsi_initialize_irq(struct platform_device *dsidev)
 863 {
 864         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 865         unsigned long flags;
 866         int vc;
 867
 868         spin_lock_irqsave(&dsi->irq_lock, flags);
 869
 870         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 871
 872         _omap_dsi_set_irqs(dsidev);
 873         for (vc = 0; vc < 4; ++vc)
 874                 _omap_dsi_set_irqs_vc(dsidev, vc);
 875         _omap_dsi_set_irqs_cio(dsidev);
 876
 877         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 878 }
 879
 880 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 881                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 882 {
 883         struct dsi_isr_data *isr_data;
 884         int free_idx;
 885         int i;
 886
 887         BUG_ON(isr == NULL);
 888
 889         /* check for duplicate entry and find a free slot */
 890         free_idx = -1;
 891         for (i = 0; i < isr_array_size; i++) {
 892                 isr_data = &isr_array[i];
 893
 894                 if (isr_data->isr == isr && isr_data->arg == arg &&
 895                                 isr_data->mask == mask) {
 896                         return -EINVAL;
 897                 }
 898
 899                 if (isr_data->isr == NULL && free_idx == -1)
 900                         free_idx = i;
 901         }
 902
 903         if (free_idx == -1)
 904                 return -EBUSY;
 905
 906         isr_data = &isr_array[free_idx];
 907         isr_data->isr = isr;
 908         isr_data->arg = arg;
 909         isr_data->mask = mask;
 910
 911         return 0;
 912 }
 913
 914 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 915                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 916 {
 917         struct dsi_isr_data *isr_data;
 918         int i;
 919
 920         for (i = 0; i < isr_array_size; i++) {
 921                 isr_data = &isr_array[i];
 922                 if (isr_data->isr != isr || isr_data->arg != arg ||
 923                                 isr_data->mask != mask)
 924                         continue;
 925
 926                 isr_data->isr = NULL;
 927                 isr_data->arg = NULL;
 928                 isr_data->mask = 0;
 929
 930                 return 0;
 931         }
 932
 933         return -EINVAL;
 934 }
 935
 936 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 937                 void *arg, u32 mask)
 938 {
 939         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 940         unsigned long flags;
 941         int r;
 942
 943         spin_lock_irqsave(&dsi->irq_lock, flags);
 944
 945         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 946                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 947
 948         if (r == 0)
 949                 _omap_dsi_set_irqs(dsidev);
 950
 951         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 952
 953         return r;
 954 }
 955
 956 static int dsi_unregister_isr(struct platform_device *dsidev,
 957                 omap_dsi_isr_t isr, void *arg, u32 mask)
 958 {
 959         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 960         unsigned long flags;
 961         int r;
 962
 963         spin_lock_irqsave(&dsi->irq_lock, flags);
 964
 965         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 966                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 967
 968         if (r == 0)
 969                 _omap_dsi_set_irqs(dsidev);
 970
 971         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 972
 973         return r;
 974 }
 975
 976 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 977                 omap_dsi_isr_t isr, void *arg, u32 mask)
 978 {
 979         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 980         unsigned long flags;
 981         int r;
 982
 983         spin_lock_irqsave(&dsi->irq_lock, flags);
 984
 985         r = _dsi_register_isr(isr, arg, mask,
 986                         dsi->isr_tables.isr_table_vc[channel],
 987                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 988
 989         if (r == 0)
 990                 _omap_dsi_set_irqs_vc(dsidev, channel);
 991
 992         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 993
 994         return r;
 995 }
 996
 997 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 998                 omap_dsi_isr_t isr, void *arg, u32 mask)
 999 {
1000         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1001         unsigned long flags;
1002         int r;
1003
1004         spin_lock_irqsave(&dsi->irq_lock, flags);
1005
1006         r = _dsi_unregister_isr(isr, arg, mask,
1007                         dsi->isr_tables.isr_table_vc[channel],
1008                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1009
1010         if (r == 0)
1011                 _omap_dsi_set_irqs_vc(dsidev, channel);
1012
1013         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1014
1015         return r;
1016 }
1017
1018 static int dsi_register_isr_cio(struct platform_device *dsidev,
1019                 omap_dsi_isr_t isr, void *arg, u32 mask)
1020 {
1021         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022         unsigned long flags;
1023         int r;
1024
1025         spin_lock_irqsave(&dsi->irq_lock, flags);
1026
1027         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1028                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1029
1030         if (r == 0)
1031                 _omap_dsi_set_irqs_cio(dsidev);
1032
1033         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1034
1035         return r;
1036 }
1037
1038 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1039                 omap_dsi_isr_t isr, void *arg, u32 mask)
1040 {
1041         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042         unsigned long flags;
1043         int r;
1044
1045         spin_lock_irqsave(&dsi->irq_lock, flags);
1046
1047         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1048                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1049
1050         if (r == 0)
1051                 _omap_dsi_set_irqs_cio(dsidev);
1052
1053         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1054
1055         return r;
1056 }
1057
1058 static u32 dsi_get_errors(struct platform_device *dsidev)
1059 {
1060         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1061         unsigned long flags;
1062         u32 e;
1063         spin_lock_irqsave(&dsi->errors_lock, flags);
1064         e = dsi->errors;
1065         dsi->errors = 0;
1066         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1067         return e;
1068 }
1069
1070 int dsi_runtime_get(struct platform_device *dsidev)
1071 {
1072         int r;
1073         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1074
1075         DSSDBG("dsi_runtime_get\n");
1076
1077         r = pm_runtime_get_sync(&dsi->pdev->dev);
1078         WARN_ON(r < 0);
1079         return r < 0 ? r : 0;
1080 }
1081
1082 void dsi_runtime_put(struct platform_device *dsidev)
1083 {
1084         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1085         int r;
1086
1087         DSSDBG("dsi_runtime_put\n");
1088
1089         r = pm_runtime_put_sync(&dsi->pdev->dev);
1090         WARN_ON(r < 0 && r != -ENOSYS);
1091 }
1092
1093 /* source clock for DSI PLL. this could also be PCLKFREE */
1094 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1095                 bool enable)
1096 {
1097         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1098
1099         if (enable)
1100                 clk_prepare_enable(dsi->sys_clk);
1101         else
1102                 clk_disable_unprepare(dsi->sys_clk);
1103
1104         if (enable && dsi->pll_locked) {
1105                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1106                         DSSERR("cannot lock PLL when enabling clocks\n");
1107         }
1108 }
1109
1110 #ifdef DEBUG
1111 static void _dsi_print_reset_status(struct platform_device *dsidev)
1112 {
1113         u32 l;
1114         int b0, b1, b2;
1115
1116         if (!dss_debug)
1117                 return;
1118
1119         /* A dummy read using the SCP interface to any DSIPHY register is
1120          * required after DSIPHY reset to complete the reset of the DSI complex
1121          * I/O. */
1122         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1123
1124         printk(KERN_DEBUG "DSI resets: ");
1125
1126         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1127         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1128
1129         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1130         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1131
1132         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1133                 b0 = 28;
1134                 b1 = 27;
1135                 b2 = 26;
1136         } else {
1137                 b0 = 24;
1138                 b1 = 25;
1139                 b2 = 26;
1140         }
1141
1142         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1143         printk("PHY (%x%x%x, %d, %d, %d)\n",
1144                         FLD_GET(l, b0, b0),
1145                         FLD_GET(l, b1, b1),
1146                         FLD_GET(l, b2, b2),
1147                         FLD_GET(l, 29, 29),
1148                         FLD_GET(l, 30, 30),
1149                         FLD_GET(l, 31, 31));
1150 }
1151 #else
1152 #define _dsi_print_reset_status(x)
1153 #endif
1154
1155 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1156 {
1157         DSSDBG("dsi_if_enable(%d)\n", enable);
1158
1159         enable = enable ? 1 : 0;
1160         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1161
1162         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1163                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1164                         return -EIO;
1165         }
1166
1167         return 0;
1168 }
1169
1170 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1171 {
1172         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1173
1174         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1175 }
1176
1177 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1178 {
1179         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1182 }
1183
1184 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1185 {
1186         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1187
1188         return dsi->current_cinfo.clkin4ddr / 16;
1189 }
1190
1191 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1192 {
1193         unsigned long r;
1194         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1195
1196         if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1197                 /* DSI FCLK source is DSS_CLK_FCK */
1198                 r = clk_get_rate(dsi->dss_clk);
1199         } else {
1200                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1201                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1202         }
1203
1204         return r;
1205 }
1206
1207 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1208 {
1209         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1210         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1211         unsigned long dsi_fclk;
1212         unsigned lp_clk_div;
1213         unsigned long lp_clk;
1214
1215         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1216
1217         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1218                 return -EINVAL;
1219
1220         dsi_fclk = dsi_fclk_rate(dsidev);
1221
1222         lp_clk = dsi_fclk / 2 / lp_clk_div;
1223
1224         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1225         dsi->current_cinfo.lp_clk = lp_clk;
1226         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1227
1228         /* LP_CLK_DIVISOR */
1229         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1230
1231         /* LP_RX_SYNCHRO_ENABLE */
1232         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1233
1234         return 0;
1235 }
1236
1237 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1238 {
1239         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1240
1241         if (dsi->scp_clk_refcount++ == 0)
1242                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1243 }
1244
1245 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1246 {
1247         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1248
1249         WARN_ON(dsi->scp_clk_refcount == 0);
1250         if (--dsi->scp_clk_refcount == 0)
1251                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1252 }
1253
1254 enum dsi_pll_power_state {
1255         DSI_PLL_POWER_OFF       = 0x0,
1256         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1257         DSI_PLL_POWER_ON_ALL    = 0x2,
1258         DSI_PLL_POWER_ON_DIV    = 0x3,
1259 };
1260
1261 static int dsi_pll_power(struct platform_device *dsidev,
1262                 enum dsi_pll_power_state state)
1263 {
1264         int t = 0;
1265
1266         /* DSI-PLL power command 0x3 is not working */
1267         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1268                         state == DSI_PLL_POWER_ON_DIV)
1269                 state = DSI_PLL_POWER_ON_ALL;
1270
1271         /* PLL_PWR_CMD */
1272         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1273
1274         /* PLL_PWR_STATUS */
1275         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1276                 if (++t > 1000) {
1277                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1278                                         state);
1279                         return -ENODEV;
1280                 }
1281                 udelay(1);
1282         }
1283
1284         return 0;
1285 }
1286
1287 /* calculate clock rates using dividers in cinfo */
1288 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1289                 struct dsi_clock_info *cinfo)
1290 {
1291         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1292
1293         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1294                 return -EINVAL;
1295
1296         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1297                 return -EINVAL;
1298
1299         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1300                 return -EINVAL;
1301
1302         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1303                 return -EINVAL;
1304
1305         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1306         cinfo->fint = cinfo->clkin / cinfo->regn;
1307
1308         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1309                 return -EINVAL;
1310
1311         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1312
1313         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1314                 return -EINVAL;
1315
1316         if (cinfo->regm_dispc > 0)
1317                 cinfo->dsi_pll_hsdiv_dispc_clk =
1318                         cinfo->clkin4ddr / cinfo->regm_dispc;
1319         else
1320                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1321
1322         if (cinfo->regm_dsi > 0)
1323                 cinfo->dsi_pll_hsdiv_dsi_clk =
1324                         cinfo->clkin4ddr / cinfo->regm_dsi;
1325         else
1326                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1327
1328         return 0;
1329 }
1330
1331 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1332                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1333                 struct dispc_clock_info *dispc_cinfo)
1334 {
1335         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1336         struct dsi_clock_info cur, best;
1337         struct dispc_clock_info best_dispc;
1338         int min_fck_per_pck;
1339         int match = 0;
1340         unsigned long dss_sys_clk, max_dss_fck;
1341
1342         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1343
1344         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1345
1346         if (req_pck == dsi->cache_req_pck &&
1347                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1348                 DSSDBG("DSI clock info found from cache\n");
1349                 *dsi_cinfo = dsi->cache_cinfo;
1350                 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1351                         dispc_cinfo);
1352                 return 0;
1353         }
1354
1355         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1356
1357         if (min_fck_per_pck &&
1358                 req_pck * min_fck_per_pck > max_dss_fck) {
1359                 DSSERR("Requested pixel clock not possible with the current "
1360                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1361                                 "the constraint off.\n");
1362                 min_fck_per_pck = 0;
1363         }
1364
1365         DSSDBG("dsi_pll_calc\n");
1366
1367 retry:
1368         memset(&best, 0, sizeof(best));
1369         memset(&best_dispc, 0, sizeof(best_dispc));
1370
1371         memset(&cur, 0, sizeof(cur));
1372         cur.clkin = dss_sys_clk;
1373
1374         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1375         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1376         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1377                 cur.fint = cur.clkin / cur.regn;
1378
1379                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1380                         continue;
1381
1382                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1383                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1384                         unsigned long a, b;
1385
1386                         a = 2 * cur.regm * (cur.clkin/1000);
1387                         b = cur.regn;
1388                         cur.clkin4ddr = a / b * 1000;
1389
1390                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1391                                 break;
1392
1393                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1394                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1395                         for (cur.regm_dispc = 1; cur.regm_dispc <
1396                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1397                                 struct dispc_clock_info cur_dispc;
1398                                 cur.dsi_pll_hsdiv_dispc_clk =
1399                                         cur.clkin4ddr / cur.regm_dispc;
1400
1401                                 /* this will narrow down the search a bit,
1402                                  * but still give pixclocks below what was
1403                                  * requested */
1404                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1405                                         break;
1406
1407                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1408                                         continue;
1409
1410                                 if (min_fck_per_pck &&
1411                                         cur.dsi_pll_hsdiv_dispc_clk <
1412                                                 req_pck * min_fck_per_pck)
1413                                         continue;
1414
1415                                 match = 1;
1416
1417                                 dispc_find_clk_divs(req_pck,
1418                                                 cur.dsi_pll_hsdiv_dispc_clk,
1419                                                 &cur_dispc);
1420
1421                                 if (abs(cur_dispc.pck - req_pck) <
1422                                                 abs(best_dispc.pck - req_pck)) {
1423                                         best = cur;
1424                                         best_dispc = cur_dispc;
1425
1426                                         if (cur_dispc.pck == req_pck)
1427                                                 goto found;
1428                                 }
1429                         }
1430                 }
1431         }
1432 found:
1433         if (!match) {
1434                 if (min_fck_per_pck) {
1435                         DSSERR("Could not find suitable clock settings.\n"
1436                                         "Turning FCK/PCK constraint off and"
1437                                         "trying again.\n");
1438                         min_fck_per_pck = 0;
1439                         goto retry;
1440                 }
1441
1442                 DSSERR("Could not find suitable clock settings.\n");
1443
1444                 return -EINVAL;
1445         }
1446
1447         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1448         best.regm_dsi = 0;
1449         best.dsi_pll_hsdiv_dsi_clk = 0;
1450
1451         if (dsi_cinfo)
1452                 *dsi_cinfo = best;
1453         if (dispc_cinfo)
1454                 *dispc_cinfo = best_dispc;
1455
1456         dsi->cache_req_pck = req_pck;
1457         dsi->cache_clk_freq = 0;
1458         dsi->cache_cinfo = best;
1459
1460         return 0;
1461 }
1462
1463 static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
1464                 unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
1465 {
1466         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1467         struct dsi_clock_info cur, best;
1468
1469         DSSDBG("dsi_pll_calc_ddrfreq\n");
1470
1471         memset(&best, 0, sizeof(best));
1472         memset(&cur, 0, sizeof(cur));
1473
1474         cur.clkin = clk_get_rate(dsi->sys_clk);
1475
1476         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1477                 cur.fint = cur.clkin / cur.regn;
1478
1479                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1480                         continue;
1481
1482                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1483                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1484                         unsigned long a, b;
1485
1486                         a = 2 * cur.regm * (cur.clkin/1000);
1487                         b = cur.regn;
1488                         cur.clkin4ddr = a / b * 1000;
1489
1490                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1491                                 break;
1492
1493                         if (abs(cur.clkin4ddr - req_clkin4ddr) <
1494                                         abs(best.clkin4ddr - req_clkin4ddr)) {
1495                                 best = cur;
1496                                 DSSDBG("best %ld\n", best.clkin4ddr);
1497                         }
1498
1499                         if (cur.clkin4ddr == req_clkin4ddr)
1500                                 goto found;
1501                 }
1502         }
1503 found:
1504         if (cinfo)
1505                 *cinfo = best;
1506
1507         return 0;
1508 }
1509
1510 static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
1511                 struct dsi_clock_info *cinfo)
1512 {
1513         unsigned long max_dsi_fck;
1514
1515         max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1516
1517         cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1518         cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1519 }
1520
1521 static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
1522                 unsigned long req_pck, struct dsi_clock_info *cinfo,
1523                 struct dispc_clock_info *dispc_cinfo)
1524 {
1525         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1526         unsigned regm_dispc, best_regm_dispc;
1527         unsigned long dispc_clk, best_dispc_clk;
1528         int min_fck_per_pck;
1529         unsigned long max_dss_fck;
1530         struct dispc_clock_info best_dispc;
1531         bool match;
1532
1533         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1534
1535         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1536
1537         if (min_fck_per_pck &&
1538                         req_pck * min_fck_per_pck > max_dss_fck) {
1539                 DSSERR("Requested pixel clock not possible with the current "
1540                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1541                                 "the constraint off.\n");
1542                 min_fck_per_pck = 0;
1543         }
1544
1545 retry:
1546         best_regm_dispc = 0;
1547         best_dispc_clk = 0;
1548         memset(&best_dispc, 0, sizeof(best_dispc));
1549         match = false;
1550
1551         for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
1552                 struct dispc_clock_info cur_dispc;
1553
1554                 dispc_clk = cinfo->clkin4ddr / regm_dispc;
1555
1556                 /* this will narrow down the search a bit,
1557                  * but still give pixclocks below what was
1558                  * requested */
1559                 if (dispc_clk  < req_pck)
1560                         break;
1561
1562                 if (dispc_clk > max_dss_fck)
1563                         continue;
1564
1565                 if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
1566                         continue;
1567
1568                 match = true;
1569
1570                 dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
1571
1572                 if (abs(cur_dispc.pck - req_pck) <
1573                                 abs(best_dispc.pck - req_pck)) {
1574                         best_regm_dispc = regm_dispc;
1575                         best_dispc_clk = dispc_clk;
1576                         best_dispc = cur_dispc;
1577
1578                         if (cur_dispc.pck == req_pck)
1579                                 goto found;
1580                 }
1581         }
1582
1583         if (!match) {
1584                 if (min_fck_per_pck) {
1585                         DSSERR("Could not find suitable clock settings.\n"
1586                                         "Turning FCK/PCK constraint off and"
1587                                         "trying again.\n");
1588                         min_fck_per_pck = 0;
1589                         goto retry;
1590                 }
1591
1592                 DSSERR("Could not find suitable clock settings.\n");
1593
1594                 return -EINVAL;
1595         }
1596 found:
1597         cinfo->regm_dispc = best_regm_dispc;
1598         cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
1599
1600         *dispc_cinfo = best_dispc;
1601
1602         return 0;
1603 }
1604
1605 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1606                 struct dsi_clock_info *cinfo)
1607 {
1608         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1609         int r = 0;
1610         u32 l;
1611         int f = 0;
1612         u8 regn_start, regn_end, regm_start, regm_end;
1613         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1614
1615         DSSDBGF();
1616
1617         dsi->current_cinfo.clkin = cinfo->clkin;
1618         dsi->current_cinfo.fint = cinfo->fint;
1619         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1620         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1621                         cinfo->dsi_pll_hsdiv_dispc_clk;
1622         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1623                         cinfo->dsi_pll_hsdiv_dsi_clk;
1624
1625         dsi->current_cinfo.regn = cinfo->regn;
1626         dsi->current_cinfo.regm = cinfo->regm;
1627         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1628         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1629
1630         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1631
1632         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1633
1634         /* DSIPHY == CLKIN4DDR */
1635         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1636                         cinfo->regm,
1637                         cinfo->regn,
1638                         cinfo->clkin,
1639                         cinfo->clkin4ddr);
1640
1641         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1642                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1643
1644         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1645
1646         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1647                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1648                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1649                 cinfo->dsi_pll_hsdiv_dispc_clk);
1650         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1651                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1652                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1653                 cinfo->dsi_pll_hsdiv_dsi_clk);
1654
1655         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1656         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1657         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1658                         &regm_dispc_end);
1659         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1660                         &regm_dsi_end);
1661
1662         /* DSI_PLL_AUTOMODE = manual */
1663         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1664
1665         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1666         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1667         /* DSI_PLL_REGN */
1668         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1669         /* DSI_PLL_REGM */
1670         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1671         /* DSI_CLOCK_DIV */
1672         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1673                         regm_dispc_start, regm_dispc_end);
1674         /* DSIPROTO_CLOCK_DIV */
1675         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1676                         regm_dsi_start, regm_dsi_end);
1677         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1678
1679         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1680
1681         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1682
1683         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1684                 f = cinfo->fint < 1000000 ? 0x3 :
1685                         cinfo->fint < 1250000 ? 0x4 :
1686                         cinfo->fint < 1500000 ? 0x5 :
1687                         cinfo->fint < 1750000 ? 0x6 :
1688                         0x7;
1689
1690                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1691         } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1692                 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1693
1694                 l = FLD_MOD(l, f, 4, 1);        /* PLL_SELFREQDCO */
1695         }
1696
1697         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1698         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1699         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1700         if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1701                 l = FLD_MOD(l, 3, 22, 21);      /* REF_SYSCLK = sysclk */
1702         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1703
1704         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1705
1706         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1707                 DSSERR("dsi pll go bit not going down.\n");
1708                 r = -EIO;
1709                 goto err;
1710         }
1711
1712         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1713                 DSSERR("cannot lock PLL\n");
1714                 r = -EIO;
1715                 goto err;
1716         }
1717
1718         dsi->pll_locked = 1;
1719
1720         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1721         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1722         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1723         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1724         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1725         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1726         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1727         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1728         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1729         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1730         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1731         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1732         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1733         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1734         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1735         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1736
1737         DSSDBG("PLL config done\n");
1738 err:
1739         return r;
1740 }
1741
1742 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1743                 bool enable_hsdiv)
1744 {
1745         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1746         int r = 0;
1747         enum dsi_pll_power_state pwstate;
1748
1749         DSSDBG("PLL init\n");
1750
1751         if (dsi->vdds_dsi_reg == NULL) {
1752                 struct regulator *vdds_dsi;
1753
1754                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1755
1756                 if (IS_ERR(vdds_dsi)) {
1757                         DSSERR("can't get VDDS_DSI regulator\n");
1758                         return PTR_ERR(vdds_dsi);
1759                 }
1760
1761                 dsi->vdds_dsi_reg = vdds_dsi;
1762         }
1763
1764         dsi_enable_pll_clock(dsidev, 1);
1765         /*
1766          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1767          */
1768         dsi_enable_scp_clk(dsidev);
1769
1770         if (!dsi->vdds_dsi_enabled) {
1771                 r = regulator_enable(dsi->vdds_dsi_reg);
1772                 if (r)
1773                         goto err0;
1774                 dsi->vdds_dsi_enabled = true;
1775         }
1776
1777         /* XXX PLL does not come out of reset without this... */
1778         dispc_pck_free_enable(1);
1779
1780         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1781                 DSSERR("PLL not coming out of reset.\n");
1782                 r = -ENODEV;
1783                 dispc_pck_free_enable(0);
1784                 goto err1;
1785         }
1786
1787         /* XXX ... but if left on, we get problems when planes do not
1788          * fill the whole display. No idea about this */
1789         dispc_pck_free_enable(0);
1790
1791         if (enable_hsclk && enable_hsdiv)
1792                 pwstate = DSI_PLL_POWER_ON_ALL;
1793         else if (enable_hsclk)
1794                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1795         else if (enable_hsdiv)
1796                 pwstate = DSI_PLL_POWER_ON_DIV;
1797         else
1798                 pwstate = DSI_PLL_POWER_OFF;
1799
1800         r = dsi_pll_power(dsidev, pwstate);
1801
1802         if (r)
1803                 goto err1;
1804
1805         DSSDBG("PLL init done\n");
1806
1807         return 0;
1808 err1:
1809         if (dsi->vdds_dsi_enabled) {
1810                 regulator_disable(dsi->vdds_dsi_reg);
1811                 dsi->vdds_dsi_enabled = false;
1812         }
1813 err0:
1814         dsi_disable_scp_clk(dsidev);
1815         dsi_enable_pll_clock(dsidev, 0);
1816         return r;
1817 }
1818
1819 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1820 {
1821         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1822
1823         dsi->pll_locked = 0;
1824         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1825         if (disconnect_lanes) {
1826                 WARN_ON(!dsi->vdds_dsi_enabled);
1827                 regulator_disable(dsi->vdds_dsi_reg);
1828                 dsi->vdds_dsi_enabled = false;
1829         }
1830
1831         dsi_disable_scp_clk(dsidev);
1832         dsi_enable_pll_clock(dsidev, 0);
1833
1834         DSSDBG("PLL uninit done\n");
1835 }
1836
1837 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1838                 struct seq_file *s)
1839 {
1840         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1841         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1842         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1843         int dsi_module = dsi->module_id;
1844
1845         dispc_clk_src = dss_get_dispc_clk_source();
1846         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1847
1848         if (dsi_runtime_get(dsidev))
1849                 return;
1850
1851         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1852
1853         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1854
1855         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1856
1857         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1858                         cinfo->clkin4ddr, cinfo->regm);
1859
1860         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1861                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1862                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1863                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1864                         cinfo->dsi_pll_hsdiv_dispc_clk,
1865                         cinfo->regm_dispc,
1866                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1867                         "off" : "on");
1868
1869         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1870                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1871                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1872                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1873                         cinfo->dsi_pll_hsdiv_dsi_clk,
1874                         cinfo->regm_dsi,
1875                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1876                         "off" : "on");
1877
1878         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1879
1880         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1881                         dss_get_generic_clk_source_name(dsi_clk_src),
1882                         dss_feat_get_clk_source_name(dsi_clk_src));
1883
1884         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1885
1886         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1887                         cinfo->clkin4ddr / 4);
1888
1889         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1890
1891         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1892
1893         dsi_runtime_put(dsidev);
1894 }
1895
1896 void dsi_dump_clocks(struct seq_file *s)
1897 {
1898         struct platform_device *dsidev;
1899         int i;
1900
1901         for  (i = 0; i < MAX_NUM_DSI; i++) {
1902                 dsidev = dsi_get_dsidev_from_id(i);
1903                 if (dsidev)
1904                         dsi_dump_dsidev_clocks(dsidev, s);
1905         }
1906 }
1907
1908 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1909 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1910                 struct seq_file *s)
1911 {
1912         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1913         unsigned long flags;
1914         struct dsi_irq_stats stats;
1915
1916         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1917
1918         stats = dsi->irq_stats;
1919         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1920         dsi->irq_stats.last_reset = jiffies;
1921
1922         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1923
1924         seq_printf(s, "period %u ms\n",
1925                         jiffies_to_msecs(jiffies - stats.last_reset));
1926
1927         seq_printf(s, "irqs %d\n", stats.irq_count);
1928 #define PIS(x) \
1929         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1930
1931         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1932         PIS(VC0);
1933         PIS(VC1);
1934         PIS(VC2);
1935         PIS(VC3);
1936         PIS(WAKEUP);
1937         PIS(RESYNC);
1938         PIS(PLL_LOCK);
1939         PIS(PLL_UNLOCK);
1940         PIS(PLL_RECALL);
1941         PIS(COMPLEXIO_ERR);
1942         PIS(HS_TX_TIMEOUT);
1943         PIS(LP_RX_TIMEOUT);
1944         PIS(TE_TRIGGER);
1945         PIS(ACK_TRIGGER);
1946         PIS(SYNC_LOST);
1947         PIS(LDO_POWER_GOOD);
1948         PIS(TA_TIMEOUT);
1949 #undef PIS
1950
1951 #define PIS(x) \
1952         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1953                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1954                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1955                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1956                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1957
1958         seq_printf(s, "-- VC interrupts --\n");
1959         PIS(CS);
1960         PIS(ECC_CORR);
1961         PIS(PACKET_SENT);
1962         PIS(FIFO_TX_OVF);
1963         PIS(FIFO_RX_OVF);
1964         PIS(BTA);
1965         PIS(ECC_NO_CORR);
1966         PIS(FIFO_TX_UDF);
1967         PIS(PP_BUSY_CHANGE);
1968 #undef PIS
1969
1970 #define PIS(x) \
1971         seq_printf(s, "%-20s %10d\n", #x, \
1972                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1973
1974         seq_printf(s, "-- CIO interrupts --\n");
1975         PIS(ERRSYNCESC1);
1976         PIS(ERRSYNCESC2);
1977         PIS(ERRSYNCESC3);
1978         PIS(ERRESC1);
1979         PIS(ERRESC2);
1980         PIS(ERRESC3);
1981         PIS(ERRCONTROL1);
1982         PIS(ERRCONTROL2);
1983         PIS(ERRCONTROL3);
1984         PIS(STATEULPS1);
1985         PIS(STATEULPS2);
1986         PIS(STATEULPS3);
1987         PIS(ERRCONTENTIONLP0_1);
1988         PIS(ERRCONTENTIONLP1_1);
1989         PIS(ERRCONTENTIONLP0_2);
1990         PIS(ERRCONTENTIONLP1_2);
1991         PIS(ERRCONTENTIONLP0_3);
1992         PIS(ERRCONTENTIONLP1_3);
1993         PIS(ULPSACTIVENOT_ALL0);
1994         PIS(ULPSACTIVENOT_ALL1);
1995 #undef PIS
1996 }
1997
1998 static void dsi1_dump_irqs(struct seq_file *s)
1999 {
2000         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2001
2002         dsi_dump_dsidev_irqs(dsidev, s);
2003 }
2004
2005 static void dsi2_dump_irqs(struct seq_file *s)
2006 {
2007         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2008
2009         dsi_dump_dsidev_irqs(dsidev, s);
2010 }
2011 #endif
2012
2013 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
2014                 struct seq_file *s)
2015 {
2016 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
2017
2018         if (dsi_runtime_get(dsidev))
2019                 return;
2020         dsi_enable_scp_clk(dsidev);
2021
2022         DUMPREG(DSI_REVISION);
2023         DUMPREG(DSI_SYSCONFIG);
2024         DUMPREG(DSI_SYSSTATUS);
2025         DUMPREG(DSI_IRQSTATUS);
2026         DUMPREG(DSI_IRQENABLE);
2027         DUMPREG(DSI_CTRL);
2028         DUMPREG(DSI_COMPLEXIO_CFG1);
2029         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
2030         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
2031         DUMPREG(DSI_CLK_CTRL);
2032         DUMPREG(DSI_TIMING1);
2033         DUMPREG(DSI_TIMING2);
2034         DUMPREG(DSI_VM_TIMING1);
2035         DUMPREG(DSI_VM_TIMING2);
2036         DUMPREG(DSI_VM_TIMING3);
2037         DUMPREG(DSI_CLK_TIMING);
2038         DUMPREG(DSI_TX_FIFO_VC_SIZE);
2039         DUMPREG(DSI_RX_FIFO_VC_SIZE);
2040         DUMPREG(DSI_COMPLEXIO_CFG2);
2041         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
2042         DUMPREG(DSI_VM_TIMING4);
2043         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
2044         DUMPREG(DSI_VM_TIMING5);
2045         DUMPREG(DSI_VM_TIMING6);
2046         DUMPREG(DSI_VM_TIMING7);
2047         DUMPREG(DSI_STOPCLK_TIMING);
2048
2049         DUMPREG(DSI_VC_CTRL(0));
2050         DUMPREG(DSI_VC_TE(0));
2051         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
2052         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
2053         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
2054         DUMPREG(DSI_VC_IRQSTATUS(0));
2055         DUMPREG(DSI_VC_IRQENABLE(0));
2056
2057         DUMPREG(DSI_VC_CTRL(1));
2058         DUMPREG(DSI_VC_TE(1));
2059         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
2060         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
2061         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
2062         DUMPREG(DSI_VC_IRQSTATUS(1));
2063         DUMPREG(DSI_VC_IRQENABLE(1));
2064
2065         DUMPREG(DSI_VC_CTRL(2));
2066         DUMPREG(DSI_VC_TE(2));
2067         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
2068         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
2069         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
2070         DUMPREG(DSI_VC_IRQSTATUS(2));
2071         DUMPREG(DSI_VC_IRQENABLE(2));
2072
2073         DUMPREG(DSI_VC_CTRL(3));
2074         DUMPREG(DSI_VC_TE(3));
2075         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
2076         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
2077         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
2078         DUMPREG(DSI_VC_IRQSTATUS(3));
2079         DUMPREG(DSI_VC_IRQENABLE(3));
2080
2081         DUMPREG(DSI_DSIPHY_CFG0);
2082         DUMPREG(DSI_DSIPHY_CFG1);
2083         DUMPREG(DSI_DSIPHY_CFG2);
2084         DUMPREG(DSI_DSIPHY_CFG5);
2085
2086         DUMPREG(DSI_PLL_CONTROL);
2087         DUMPREG(DSI_PLL_STATUS);
2088         DUMPREG(DSI_PLL_GO);
2089         DUMPREG(DSI_PLL_CONFIGURATION1);
2090         DUMPREG(DSI_PLL_CONFIGURATION2);
2091
2092         dsi_disable_scp_clk(dsidev);
2093         dsi_runtime_put(dsidev);
2094 #undef DUMPREG
2095 }
2096
2097 static void dsi1_dump_regs(struct seq_file *s)
2098 {
2099         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2100
2101         dsi_dump_dsidev_regs(dsidev, s);
2102 }
2103
2104 static void dsi2_dump_regs(struct seq_file *s)
2105 {
2106         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2107
2108         dsi_dump_dsidev_regs(dsidev, s);
2109 }
2110
2111 enum dsi_cio_power_state {
2112         DSI_COMPLEXIO_POWER_OFF         = 0x0,
2113         DSI_COMPLEXIO_POWER_ON          = 0x1,
2114         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
2115 };
2116
2117 static int dsi_cio_power(struct platform_device *dsidev,
2118                 enum dsi_cio_power_state state)
2119 {
2120         int t = 0;
2121
2122         /* PWR_CMD */
2123         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2124
2125         /* PWR_STATUS */
2126         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2127                         26, 25) != state) {
2128                 if (++t > 1000) {
2129                         DSSERR("failed to set complexio power state to "
2130                                         "%d\n", state);
2131                         return -ENODEV;
2132                 }
2133                 udelay(1);
2134         }
2135
2136         return 0;
2137 }
2138
2139 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2140 {
2141         int val;
2142
2143         /* line buffer on OMAP3 is 1024 x 24bits */
2144         /* XXX: for some reason using full buffer size causes
2145          * considerable TX slowdown with update sizes that fill the
2146          * whole buffer */
2147         if (!dss_has_feature(FEAT_DSI_GNQ))
2148                 return 1023 * 3;
2149
2150         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2151
2152         switch (val) {
2153         case 1:
2154                 return 512 * 3;         /* 512x24 bits */
2155         case 2:
2156                 return 682 * 3;         /* 682x24 bits */
2157         case 3:
2158                 return 853 * 3;         /* 853x24 bits */
2159         case 4:
2160                 return 1024 * 3;        /* 1024x24 bits */
2161         case 5:
2162                 return 1194 * 3;        /* 1194x24 bits */
2163         case 6:
2164                 return 1365 * 3;        /* 1365x24 bits */
2165         case 7:
2166                 return 1920 * 3;        /* 1920x24 bits */
2167         default:
2168                 BUG();
2169                 return 0;
2170         }
2171 }
2172
2173 static int dsi_set_lane_config(struct platform_device *dsidev)
2174 {
2175         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2176         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2177         static const enum dsi_lane_function functions[] = {
2178                 DSI_LANE_CLK,
2179                 DSI_LANE_DATA1,
2180                 DSI_LANE_DATA2,
2181                 DSI_LANE_DATA3,
2182                 DSI_LANE_DATA4,
2183         };
2184         u32 r;
2185         int i;
2186
2187         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2188
2189         for (i = 0; i < dsi->num_lanes_used; ++i) {
2190                 unsigned offset = offsets[i];
2191                 unsigned polarity, lane_number;
2192                 unsigned t;
2193
2194                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2195                         if (dsi->lanes[t].function == functions[i])
2196                                 break;
2197
2198                 if (t == dsi->num_lanes_supported)
2199                         return -EINVAL;
2200
2201                 lane_number = t;
2202                 polarity = dsi->lanes[t].polarity;
2203
2204                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2205                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2206         }
2207
2208         /* clear the unused lanes */
2209         for (; i < dsi->num_lanes_supported; ++i) {
2210                 unsigned offset = offsets[i];
2211
2212                 r = FLD_MOD(r, 0, offset + 2, offset);
2213                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2214         }
2215
2216         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2217
2218         return 0;
2219 }
2220
2221 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2222 {
2223         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2224
2225         /* convert time in ns to ddr ticks, rounding up */
2226         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2227         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2228 }
2229
2230 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2231 {
2232         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2233
2234         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2235         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2236 }
2237
2238 static void dsi_cio_timings(struct platform_device *dsidev)
2239 {
2240         u32 r;
2241         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2242         u32 tlpx_half, tclk_trail, tclk_zero;
2243         u32 tclk_prepare;
2244
2245         /* calculate timings */
2246
2247         /* 1 * DDR_CLK = 2 * UI */
2248
2249         /* min 40ns + 4*UI      max 85ns + 6*UI */
2250         ths_prepare = ns2ddr(dsidev, 70) + 2;
2251
2252         /* min 145ns + 10*UI */
2253         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2254
2255         /* min max(8*UI, 60ns+4*UI) */
2256         ths_trail = ns2ddr(dsidev, 60) + 5;
2257
2258         /* min 100ns */
2259         ths_exit = ns2ddr(dsidev, 145);
2260
2261         /* tlpx min 50n */
2262         tlpx_half = ns2ddr(dsidev, 25);
2263
2264         /* min 60ns */
2265         tclk_trail = ns2ddr(dsidev, 60) + 2;
2266
2267         /* min 38ns, max 95ns */
2268         tclk_prepare = ns2ddr(dsidev, 65);
2269
2270         /* min tclk-prepare + tclk-zero = 300ns */
2271         tclk_zero = ns2ddr(dsidev, 260);
2272
2273         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2274                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2275                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2276         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2277                         ths_trail, ddr2ns(dsidev, ths_trail),
2278                         ths_exit, ddr2ns(dsidev, ths_exit));
2279
2280         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2281                         "tclk_zero %u (%uns)\n",
2282                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2283                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2284                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2285         DSSDBG("tclk_prepare %u (%uns)\n",
2286                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2287
2288         /* program timings */
2289
2290         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2291         r = FLD_MOD(r, ths_prepare, 31, 24);
2292         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2293         r = FLD_MOD(r, ths_trail, 15, 8);
2294         r = FLD_MOD(r, ths_exit, 7, 0);
2295         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2296
2297         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2298         r = FLD_MOD(r, tlpx_half, 20, 16);
2299         r = FLD_MOD(r, tclk_trail, 15, 8);
2300         r = FLD_MOD(r, tclk_zero, 7, 0);
2301
2302         if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2303                 r = FLD_MOD(r, 0, 21, 21);      /* DCCEN = disable */
2304                 r = FLD_MOD(r, 1, 22, 22);      /* CLKINP_DIVBY2EN = enable */
2305                 r = FLD_MOD(r, 1, 23, 23);      /* CLKINP_SEL = enable */
2306         }
2307
2308         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2309
2310         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2311         r = FLD_MOD(r, tclk_prepare, 7, 0);
2312         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2313 }
2314
2315 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2316 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2317                 unsigned mask_p, unsigned mask_n)
2318 {
2319         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2320         int i;
2321         u32 l;
2322         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2323
2324         l = 0;
2325
2326         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2327                 unsigned p = dsi->lanes[i].polarity;
2328
2329                 if (mask_p & (1 << i))
2330                         l |= 1 << (i * 2 + (p ? 0 : 1));
2331
2332                 if (mask_n & (1 << i))
2333                         l |= 1 << (i * 2 + (p ? 1 : 0));
2334         }
2335
2336         /*
2337          * Bits in REGLPTXSCPDAT4TO0DXDY:
2338          * 17: DY0 18: DX0
2339          * 19: DY1 20: DX1
2340          * 21: DY2 22: DX2
2341          * 23: DY3 24: DX3
2342          * 25: DY4 26: DX4
2343          */
2344
2345         /* Set the lane override configuration */
2346
2347         /* REGLPTXSCPDAT4TO0DXDY */
2348         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2349
2350         /* Enable lane override */
2351
2352         /* ENLPTXSCPDAT */
2353         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2354 }
2355
2356 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2357 {
2358         /* Disable lane override */
2359         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2360         /* Reset the lane override configuration */
2361         /* REGLPTXSCPDAT4TO0DXDY */
2362         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2363 }
2364
2365 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2366 {
2367         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2368         int t, i;
2369         bool in_use[DSI_MAX_NR_LANES];
2370         static const u8 offsets_old[] = { 28, 27, 26 };
2371         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2372         const u8 *offsets;
2373
2374         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2375                 offsets = offsets_old;
2376         else
2377                 offsets = offsets_new;
2378
2379         for (i = 0; i < dsi->num_lanes_supported; ++i)
2380                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2381
2382         t = 100000;
2383         while (true) {
2384                 u32 l;
2385                 int ok;
2386
2387                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2388
2389                 ok = 0;
2390                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2391                         if (!in_use[i] || (l & (1 << offsets[i])))
2392                                 ok++;
2393                 }
2394
2395                 if (ok == dsi->num_lanes_supported)
2396                         break;
2397
2398                 if (--t == 0) {
2399                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2400                                 if (!in_use[i] || (l & (1 << offsets[i])))
2401                                         continue;
2402
2403                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2404                                                 "out of reset\n", i);
2405                         }
2406                         return -EIO;
2407                 }
2408         }
2409
2410         return 0;
2411 }
2412
2413 /* return bitmask of enabled lanes, lane0 being the lsb */
2414 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2415 {
2416         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2417         unsigned mask = 0;
2418         int i;
2419
2420         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2421                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2422                         mask |= 1 << i;
2423         }
2424
2425         return mask;
2426 }
2427
2428 static int dsi_cio_init(struct platform_device *dsidev)
2429 {
2430         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2431         int r;
2432         u32 l;
2433
2434         DSSDBGF();
2435
2436         r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2437         if (r)
2438                 return r;
2439
2440         dsi_enable_scp_clk(dsidev);
2441
2442         /* A dummy read using the SCP interface to any DSIPHY register is
2443          * required after DSIPHY reset to complete the reset of the DSI complex
2444          * I/O. */
2445         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2446
2447         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2448                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2449                 r = -EIO;
2450                 goto err_scp_clk_dom;
2451         }
2452
2453         r = dsi_set_lane_config(dsidev);
2454         if (r)
2455                 goto err_scp_clk_dom;
2456
2457         /* set TX STOP MODE timer to maximum for this operation */
2458         l = dsi_read_reg(dsidev, DSI_TIMING1);
2459         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2460         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2461         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2462         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2463         dsi_write_reg(dsidev, DSI_TIMING1, l);
2464
2465         if (dsi->ulps_enabled) {
2466                 unsigned mask_p;
2467                 int i;
2468
2469                 DSSDBG("manual ulps exit\n");
2470
2471                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2472                  * stop state. DSS HW cannot do this via the normal
2473                  * ULPS exit sequence, as after reset the DSS HW thinks
2474                  * that we are not in ULPS mode, and refuses to send the
2475                  * sequence. So we need to send the ULPS exit sequence
2476                  * manually by setting positive lines high and negative lines
2477                  * low for 1ms.
2478                  */
2479
2480                 mask_p = 0;
2481
2482                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2483                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2484                                 continue;
2485                         mask_p |= 1 << i;
2486                 }
2487
2488                 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2489         }
2490
2491         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2492         if (r)
2493                 goto err_cio_pwr;
2494
2495         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2496                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2497                 r = -ENODEV;
2498                 goto err_cio_pwr_dom;
2499         }
2500
2501         dsi_if_enable(dsidev, true);
2502         dsi_if_enable(dsidev, false);
2503         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2504
2505         r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2506         if (r)
2507                 goto err_tx_clk_esc_rst;
2508
2509         if (dsi->ulps_enabled) {
2510                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2511                 ktime_t wait = ns_to_ktime(1000 * 1000);
2512                 set_current_state(TASK_UNINTERRUPTIBLE);
2513                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2514
2515                 /* Disable the override. The lanes should be set to Mark-11
2516                  * state by the HW */
2517                 dsi_cio_disable_lane_override(dsidev);
2518         }
2519
2520         /* FORCE_TX_STOP_MODE_IO */
2521         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2522
2523         dsi_cio_timings(dsidev);
2524
2525         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2526                 /* DDR_CLK_ALWAYS_ON */
2527                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2528                         dsi->vm_timings.ddr_clk_always_on, 13, 13);
2529         }
2530
2531         dsi->ulps_enabled = false;
2532
2533         DSSDBG("CIO init done\n");
2534
2535         return 0;
2536
2537 err_tx_clk_esc_rst:
2538         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2539 err_cio_pwr_dom:
2540         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2541 err_cio_pwr:
2542         if (dsi->ulps_enabled)
2543                 dsi_cio_disable_lane_override(dsidev);
2544 err_scp_clk_dom:
2545         dsi_disable_scp_clk(dsidev);
2546         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2547         return r;
2548 }
2549
2550 static void dsi_cio_uninit(struct platform_device *dsidev)
2551 {
2552         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2553
2554         /* DDR_CLK_ALWAYS_ON */
2555         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2556
2557         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2558         dsi_disable_scp_clk(dsidev);
2559         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2560 }
2561
2562 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2563                 enum fifo_size size1, enum fifo_size size2,
2564                 enum fifo_size size3, enum fifo_size size4)
2565 {
2566         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2567         u32 r = 0;
2568         int add = 0;
2569         int i;
2570
2571         dsi->vc[0].fifo_size = size1;
2572         dsi->vc[1].fifo_size = size2;
2573         dsi->vc[2].fifo_size = size3;
2574         dsi->vc[3].fifo_size = size4;
2575
2576         for (i = 0; i < 4; i++) {
2577                 u8 v;
2578                 int size = dsi->vc[i].fifo_size;
2579
2580                 if (add + size > 4) {
2581                         DSSERR("Illegal FIFO configuration\n");
2582                         BUG();
2583                         return;
2584                 }
2585
2586                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2587                 r |= v << (8 * i);
2588                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2589                 add += size;
2590         }
2591
2592         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2593 }
2594
2595 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2596                 enum fifo_size size1, enum fifo_size size2,
2597                 enum fifo_size size3, enum fifo_size size4)
2598 {
2599         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2600         u32 r = 0;
2601         int add = 0;
2602         int i;
2603
2604         dsi->vc[0].fifo_size = size1;
2605         dsi->vc[1].fifo_size = size2;
2606         dsi->vc[2].fifo_size = size3;
2607         dsi->vc[3].fifo_size = size4;
2608
2609         for (i = 0; i < 4; i++) {
2610                 u8 v;
2611                 int size = dsi->vc[i].fifo_size;
2612
2613                 if (add + size > 4) {
2614                         DSSERR("Illegal FIFO configuration\n");
2615                         BUG();
2616                         return;
2617                 }
2618
2619                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2620                 r |= v << (8 * i);
2621                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2622                 add += size;
2623         }
2624
2625         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2626 }
2627
2628 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2629 {
2630         u32 r;
2631
2632         r = dsi_read_reg(dsidev, DSI_TIMING1);
2633         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2634         dsi_write_reg(dsidev, DSI_TIMING1, r);
2635
2636         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2637                 DSSERR("TX_STOP bit not going down\n");
2638                 return -EIO;
2639         }
2640
2641         return 0;
2642 }
2643
2644 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2645 {
2646         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2647 }
2648
2649 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2650 {
2651         struct dsi_packet_sent_handler_data *vp_data =
2652                 (struct dsi_packet_sent_handler_data *) data;
2653         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2654         const int channel = dsi->update_channel;
2655         u8 bit = dsi->te_enabled ? 30 : 31;
2656
2657         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2658                 complete(vp_data->completion);
2659 }
2660
2661 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2662 {
2663         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2664         DECLARE_COMPLETION_ONSTACK(completion);
2665         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2666         int r = 0;
2667         u8 bit;
2668
2669         bit = dsi->te_enabled ? 30 : 31;
2670
2671         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2672                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2673         if (r)
2674                 goto err0;
2675
2676         /* Wait for completion only if TE_EN/TE_START is still set */
2677         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2678                 if (wait_for_completion_timeout(&completion,
2679                                 msecs_to_jiffies(10)) == 0) {
2680                         DSSERR("Failed to complete previous frame transfer\n");
2681                         r = -EIO;
2682                         goto err1;
2683                 }
2684         }
2685
2686         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2687                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2688
2689         return 0;
2690 err1:
2691         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2692                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2693 err0:
2694         return r;
2695 }
2696
2697 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2698 {
2699         struct dsi_packet_sent_handler_data *l4_data =
2700                 (struct dsi_packet_sent_handler_data *) data;
2701         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2702         const int channel = dsi->update_channel;
2703
2704         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2705                 complete(l4_data->completion);
2706 }
2707
2708 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2709 {
2710         DECLARE_COMPLETION_ONSTACK(completion);
2711         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2712         int r = 0;
2713
2714         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2715                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2716         if (r)
2717                 goto err0;
2718
2719         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2720         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2721                 if (wait_for_completion_timeout(&completion,
2722                                 msecs_to_jiffies(10)) == 0) {
2723                         DSSERR("Failed to complete previous l4 transfer\n");
2724                         r = -EIO;
2725                         goto err1;
2726                 }
2727         }
2728
2729         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2730                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2731
2732         return 0;
2733 err1:
2734         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2735                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2736 err0:
2737         return r;
2738 }
2739
2740 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2741 {
2742         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2743
2744         WARN_ON(!dsi_bus_is_locked(dsidev));
2745
2746         WARN_ON(in_interrupt());
2747
2748         if (!dsi_vc_is_enabled(dsidev, channel))
2749                 return 0;
2750
2751         switch (dsi->vc[channel].source) {
2752         case DSI_VC_SOURCE_VP:
2753                 return dsi_sync_vc_vp(dsidev, channel);
2754         case DSI_VC_SOURCE_L4:
2755                 return dsi_sync_vc_l4(dsidev, channel);
2756         default:
2757                 BUG();
2758                 return -EINVAL;
2759         }
2760 }
2761
2762 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2763                 bool enable)
2764 {
2765         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2766                         channel, enable);
2767
2768         enable = enable ? 1 : 0;
2769
2770         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2771
2772         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2773                 0, enable) != enable) {
2774                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2775                         return -EIO;
2776         }
2777
2778         return 0;
2779 }
2780
2781 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2782 {
2783         u32 r;
2784
2785         DSSDBGF("%d", channel);
2786
2787         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2788
2789         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2790                 DSSERR("VC(%d) busy when trying to configure it!\n",
2791                                 channel);
2792
2793         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2794         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2795         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2796         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2797         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2798         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2799         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2800         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2801                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2802
2803         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2804         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2805
2806         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2807 }
2808
2809 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2810                 enum dsi_vc_source source)
2811 {
2812         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2813
2814         if (dsi->vc[channel].source == source)
2815                 return 0;
2816
2817         DSSDBGF("%d", channel);
2818
2819         dsi_sync_vc(dsidev, channel);
2820
2821         dsi_vc_enable(dsidev, channel, 0);
2822
2823         /* VC_BUSY */
2824         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2825                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2826                 return -EIO;
2827         }
2828
2829         /* SOURCE, 0 = L4, 1 = video port */
2830         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2831
2832         /* DCS_CMD_ENABLE */
2833         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2834                 bool enable = source == DSI_VC_SOURCE_VP;
2835                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2836         }
2837
2838         dsi_vc_enable(dsidev, channel, 1);
2839
2840         dsi->vc[channel].source = source;
2841
2842         return 0;
2843 }
2844
2845 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2846                 bool enable)
2847 {
2848         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2849         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2850
2851         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2852
2853         WARN_ON(!dsi_bus_is_locked(dsidev));
2854
2855         dsi_vc_enable(dsidev, channel, 0);
2856         dsi_if_enable(dsidev, 0);
2857
2858         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2859
2860         dsi_vc_enable(dsidev, channel, 1);
2861         dsi_if_enable(dsidev, 1);
2862
2863         dsi_force_tx_stop_mode_io(dsidev);
2864
2865         /* start the DDR clock by sending a NULL packet */
2866         if (dsi->vm_timings.ddr_clk_always_on && enable)
2867                 dsi_vc_send_null(dssdev, channel);
2868 }
2869 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2870
2871 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2872 {
2873         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2874                 u32 val;
2875                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2876                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2877                                 (val >> 0) & 0xff,
2878                                 (val >> 8) & 0xff,
2879                                 (val >> 16) & 0xff,
2880                                 (val >> 24) & 0xff);
2881         }
2882 }
2883
2884 static void dsi_show_rx_ack_with_err(u16 err)
2885 {
2886         DSSERR("\tACK with ERROR (%#x):\n", err);
2887         if (err & (1 << 0))
2888                 DSSERR("\t\tSoT Error\n");
2889         if (err & (1 << 1))
2890                 DSSERR("\t\tSoT Sync Error\n");
2891         if (err & (1 << 2))
2892                 DSSERR("\t\tEoT Sync Error\n");
2893         if (err & (1 << 3))
2894                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2895         if (err & (1 << 4))
2896                 DSSERR("\t\tLP Transmit Sync Error\n");
2897         if (err & (1 << 5))
2898                 DSSERR("\t\tHS Receive Timeout Error\n");
2899         if (err & (1 << 6))
2900                 DSSERR("\t\tFalse Control Error\n");
2901         if (err & (1 << 7))
2902                 DSSERR("\t\t(reserved7)\n");
2903         if (err & (1 << 8))
2904                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2905         if (err & (1 << 9))
2906                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2907         if (err & (1 << 10))
2908                 DSSERR("\t\tChecksum Error\n");
2909         if (err & (1 << 11))
2910                 DSSERR("\t\tData type not recognized\n");
2911         if (err & (1 << 12))
2912                 DSSERR("\t\tInvalid VC ID\n");
2913         if (err & (1 << 13))
2914                 DSSERR("\t\tInvalid Transmission Length\n");
2915         if (err & (1 << 14))
2916                 DSSERR("\t\t(reserved14)\n");
2917         if (err & (1 << 15))
2918                 DSSERR("\t\tDSI Protocol Violation\n");
2919 }
2920
2921 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2922                 int channel)
2923 {
2924         /* RX_FIFO_NOT_EMPTY */
2925         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2926                 u32 val;
2927                 u8 dt;
2928                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2929                 DSSERR("\trawval %#08x\n", val);
2930                 dt = FLD_GET(val, 5, 0);
2931                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2932                         u16 err = FLD_GET(val, 23, 8);
2933                         dsi_show_rx_ack_with_err(err);
2934                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2935                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2936                                         FLD_GET(val, 23, 8));
2937                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2938                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2939                                         FLD_GET(val, 23, 8));
2940                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2941                         DSSERR("\tDCS long response, len %d\n",
2942                                         FLD_GET(val, 23, 8));
2943                         dsi_vc_flush_long_data(dsidev, channel);
2944                 } else {
2945                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2946                 }
2947         }
2948         return 0;
2949 }
2950
2951 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2952 {
2953         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2954
2955         if (dsi->debug_write || dsi->debug_read)
2956                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2957
2958         WARN_ON(!dsi_bus_is_locked(dsidev));
2959
2960         /* RX_FIFO_NOT_EMPTY */
2961         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2962                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2963                 dsi_vc_flush_receive_data(dsidev, channel);
2964         }
2965
2966         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2967
2968         /* flush posted write */
2969         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2970
2971         return 0;
2972 }
2973
2974 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2975 {
2976         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2977         DECLARE_COMPLETION_ONSTACK(completion);
2978         int r = 0;
2979         u32 err;
2980
2981         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2982                         &completion, DSI_VC_IRQ_BTA);
2983         if (r)
2984                 goto err0;
2985
2986         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2987                         DSI_IRQ_ERROR_MASK);
2988         if (r)
2989                 goto err1;
2990
2991         r = dsi_vc_send_bta(dsidev, channel);
2992         if (r)
2993                 goto err2;
2994
2995         if (wait_for_completion_timeout(&completion,
2996                                 msecs_to_jiffies(500)) == 0) {
2997                 DSSERR("Failed to receive BTA\n");
2998                 r = -EIO;
2999                 goto err2;
3000         }
3001
3002         err = dsi_get_errors(dsidev);
3003         if (err) {
3004                 DSSERR("Error while sending BTA: %x\n", err);
3005                 r = -EIO;
3006                 goto err2;
3007         }
3008 err2:
3009         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
3010                         DSI_IRQ_ERROR_MASK);
3011 err1:
3012         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
3013                         &completion, DSI_VC_IRQ_BTA);
3014 err0:
3015         return r;
3016 }
3017 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
3018
3019 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
3020                 int channel, u8 data_type, u16 len, u8 ecc)
3021 {
3022         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3023         u32 val;
3024         u8 data_id;
3025
3026         WARN_ON(!dsi_bus_is_locked(dsidev));
3027
3028         data_id = data_type | dsi->vc[channel].vc_id << 6;
3029
3030         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
3031                 FLD_VAL(ecc, 31, 24);
3032
3033         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
3034 }
3035
3036 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
3037                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
3038 {
3039         u32 val;
3040
3041         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
3042
3043 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3044                         b1, b2, b3, b4, val); */
3045
3046         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3047 }
3048
3049 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3050                 u8 data_type, u8 *data, u16 len, u8 ecc)
3051 {
3052         /*u32 val; */
3053         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3054         int i;
3055         u8 *p;
3056         int r = 0;
3057         u8 b1, b2, b3, b4;
3058
3059         if (dsi->debug_write)
3060                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3061
3062         /* len + header */
3063         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3064                 DSSERR("unable to send long packet: packet too long.\n");
3065                 return -EINVAL;
3066         }
3067
3068         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3069
3070         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3071
3072         p = data;
3073         for (i = 0; i < len >> 2; i++) {
3074                 if (dsi->debug_write)
3075                         DSSDBG("\tsending full packet %d\n", i);
3076
3077                 b1 = *p++;
3078                 b2 = *p++;
3079                 b3 = *p++;
3080                 b4 = *p++;
3081
3082                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3083         }
3084
3085         i = len % 4;
3086         if (i) {
3087                 b1 = 0; b2 = 0; b3 = 0;
3088
3089                 if (dsi->debug_write)
3090                         DSSDBG("\tsending remainder bytes %d\n", i);
3091
3092                 switch (i) {
3093                 case 3:
3094                         b1 = *p++;
3095                         b2 = *p++;
3096                         b3 = *p++;
3097                         break;
3098                 case 2:
3099                         b1 = *p++;
3100                         b2 = *p++;
3101                         break;
3102                 case 1:
3103                         b1 = *p++;
3104                         break;
3105                 }
3106
3107                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3108         }
3109
3110         return r;
3111 }
3112
3113 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3114                 u8 data_type, u16 data, u8 ecc)
3115 {
3116         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3117         u32 r;
3118         u8 data_id;
3119
3120         WARN_ON(!dsi_bus_is_locked(dsidev));
3121
3122         if (dsi->debug_write)
3123                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3124                                 channel,
3125                                 data_type, data & 0xff, (data >> 8) & 0xff);
3126
3127         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3128
3129         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3130                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3131                 return -EINVAL;
3132         }
3133
3134         data_id = data_type | dsi->vc[channel].vc_id << 6;
3135
3136         r = (data_id << 0) | (data << 8) | (ecc << 24);
3137
3138         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3139
3140         return 0;
3141 }
3142
3143 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3144 {
3145         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3146
3147         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3148                 0, 0);
3149 }
3150 EXPORT_SYMBOL(dsi_vc_send_null);
3151
3152 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3153                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3154 {
3155         int r;
3156
3157         if (len == 0) {
3158                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3159                 r = dsi_vc_send_short(dsidev, channel,
3160                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3161         } else if (len == 1) {
3162                 r = dsi_vc_send_short(dsidev, channel,
3163                                 type == DSS_DSI_CONTENT_GENERIC ?
3164                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3165                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3166         } else if (len == 2) {
3167                 r = dsi_vc_send_short(dsidev, channel,
3168                                 type == DSS_DSI_CONTENT_GENERIC ?
3169                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3170                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3171                                 data[0] | (data[1] << 8), 0);
3172         } else {
3173                 r = dsi_vc_send_long(dsidev, channel,
3174                                 type == DSS_DSI_CONTENT_GENERIC ?
3175                                 MIPI_DSI_GENERIC_LONG_WRITE :
3176                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3177         }
3178
3179         return r;
3180 }
3181
3182 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3183                 u8 *data, int len)
3184 {
3185         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3186
3187         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3188                         DSS_DSI_CONTENT_DCS);
3189 }
3190 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3191
3192 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3193                 u8 *data, int len)
3194 {
3195         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3196
3197         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3198                         DSS_DSI_CONTENT_GENERIC);
3199 }
3200 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3201
3202 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3203                 u8 *data, int len, enum dss_dsi_content_type type)
3204 {
3205         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3206         int r;
3207
3208         r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3209         if (r)
3210                 goto err;
3211
3212         r = dsi_vc_send_bta_sync(dssdev, channel);
3213         if (r)
3214                 goto err;
3215
3216         /* RX_FIFO_NOT_EMPTY */
3217         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3218                 DSSERR("rx fifo not empty after write, dumping data:\n");
3219                 dsi_vc_flush_receive_data(dsidev, channel);
3220                 r = -EIO;
3221                 goto err;
3222         }
3223
3224         return 0;
3225 err:
3226         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3227                         channel, data[0], len);
3228         return r;
3229 }
3230
3231 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3232                 int len)
3233 {
3234         return dsi_vc_write_common(dssdev, channel, data, len,
3235                         DSS_DSI_CONTENT_DCS);
3236 }
3237 EXPORT_SYMBOL(dsi_vc_dcs_write);
3238
3239 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3240                 int len)
3241 {
3242         return dsi_vc_write_common(dssdev, channel, data, len,
3243                         DSS_DSI_CONTENT_GENERIC);
3244 }
3245 EXPORT_SYMBOL(dsi_vc_generic_write);
3246
3247 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3248 {
3249         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3250 }
3251 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3252
3253 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3254 {
3255         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3256 }
3257 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3258
3259 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3260                 u8 param)
3261 {
3262         u8 buf[2];
3263         buf[0] = dcs_cmd;
3264         buf[1] = param;
3265         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3266 }
3267 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3268
3269 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3270                 u8 param)
3271 {
3272         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3273 }
3274 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3275
3276 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3277                 u8 param1, u8 param2)
3278 {
3279         u8 buf[2];
3280         buf[0] = param1;
3281         buf[1] = param2;
3282         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3283 }
3284 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3285
3286 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3287                 int channel, u8 dcs_cmd)
3288 {
3289         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3290         int r;
3291
3292         if (dsi->debug_read)
3293                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3294                         channel, dcs_cmd);
3295
3296         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3297         if (r) {
3298                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3299                         " failed\n", channel, dcs_cmd);
3300                 return r;
3301         }
3302
3303         return 0;
3304 }
3305
3306 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3307                 int channel, u8 *reqdata, int reqlen)
3308 {
3309         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3310         u16 data;
3311         u8 data_type;
3312         int r;
3313
3314         if (dsi->debug_read)
3315                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3316                         channel, reqlen);
3317
3318         if (reqlen == 0) {
3319                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3320                 data = 0;
3321         } else if (reqlen == 1) {
3322                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3323                 data = reqdata[0];
3324         } else if (reqlen == 2) {
3325                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3326                 data = reqdata[0] | (reqdata[1] << 8);
3327         } else {
3328                 BUG();
3329                 return -EINVAL;
3330         }
3331
3332         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3333         if (r) {
3334                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3335                         " failed\n", channel, reqlen);
3336                 return r;
3337         }
3338
3339         return 0;
3340 }
3341
3342 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3343                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3344 {
3345         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3346         u32 val;
3347         u8 dt;
3348         int r;
3349
3350         /* RX_FIFO_NOT_EMPTY */
3351         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3352                 DSSERR("RX fifo empty when trying to read.\n");
3353                 r = -EIO;
3354                 goto err;
3355         }
3356
3357         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3358         if (dsi->debug_read)
3359                 DSSDBG("\theader: %08x\n", val);
3360         dt = FLD_GET(val, 5, 0);
3361         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3362                 u16 err = FLD_GET(val, 23, 8);
3363                 dsi_show_rx_ack_with_err(err);
3364                 r = -EIO;
3365                 goto err;
3366
3367         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3368                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3369                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3370                 u8 data = FLD_GET(val, 15, 8);
3371                 if (dsi->debug_read)
3372                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3373                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3374                                 "DCS", data);
3375
3376                 if (buflen < 1) {
3377                         r = -EIO;
3378                         goto err;
3379                 }
3380
3381                 buf[0] = data;
3382
3383                 return 1;
3384         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3385                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3386                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3387                 u16 data = FLD_GET(val, 23, 8);
3388                 if (dsi->debug_read)
3389                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3390                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3391                                 "DCS", data);
3392
3393                 if (buflen < 2) {
3394                         r = -EIO;
3395                         goto err;
3396                 }
3397
3398                 buf[0] = data & 0xff;
3399                 buf[1] = (data >> 8) & 0xff;
3400
3401                 return 2;
3402         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3403                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3404                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3405                 int w;
3406                 int len = FLD_GET(val, 23, 8);
3407                 if (dsi->debug_read)
3408                         DSSDBG("\t%s long response, len %d\n",
3409                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3410                                 "DCS", len);
3411
3412                 if (len > buflen) {
3413                         r = -EIO;
3414                         goto err;
3415                 }
3416
3417                 /* two byte checksum ends the packet, not included in len */
3418                 for (w = 0; w < len + 2;) {
3419                         int b;
3420                         val = dsi_read_reg(dsidev,
3421                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3422                         if (dsi->debug_read)
3423                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3424                                                 (val >> 0) & 0xff,
3425                                                 (val >> 8) & 0xff,
3426                                                 (val >> 16) & 0xff,
3427                                                 (val >> 24) & 0xff);
3428
3429                         for (b = 0; b < 4; ++b) {
3430                                 if (w < len)
3431                                         buf[w] = (val >> (b * 8)) & 0xff;
3432                                 /* we discard the 2 byte checksum */
3433                                 ++w;
3434                         }
3435                 }
3436
3437                 return len;
3438         } else {
3439                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3440                 r = -EIO;
3441                 goto err;
3442         }
3443
3444 err:
3445         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3446                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3447
3448         return r;
3449 }
3450
3451 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3452                 u8 *buf, int buflen)
3453 {
3454         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3455         int r;
3456
3457         r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3458         if (r)
3459                 goto err;
3460
3461         r = dsi_vc_send_bta_sync(dssdev, channel);
3462         if (r)
3463                 goto err;
3464
3465         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3466                 DSS_DSI_CONTENT_DCS);
3467         if (r < 0)
3468                 goto err;
3469
3470         if (r != buflen) {
3471                 r = -EIO;
3472                 goto err;
3473         }
3474
3475         return 0;
3476 err:
3477         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3478         return r;
3479 }
3480 EXPORT_SYMBOL(dsi_vc_dcs_read);
3481
3482 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3483                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3484 {
3485         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3486         int r;
3487
3488         r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3489         if (r)
3490                 return r;
3491
3492         r = dsi_vc_send_bta_sync(dssdev, channel);
3493         if (r)
3494                 return r;
3495
3496         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3497                 DSS_DSI_CONTENT_GENERIC);
3498         if (r < 0)
3499                 return r;
3500
3501         if (r != buflen) {
3502                 r = -EIO;
3503                 return r;
3504         }
3505
3506         return 0;
3507 }
3508
3509 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3510                 int buflen)
3511 {
3512         int r;
3513
3514         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3515         if (r) {
3516                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3517                 return r;
3518         }
3519
3520         return 0;
3521 }
3522 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3523
3524 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3525                 u8 *buf, int buflen)
3526 {
3527         int r;
3528
3529         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3530         if (r) {
3531                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3532                 return r;
3533         }
3534
3535         return 0;
3536 }
3537 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3538
3539 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3540                 u8 param1, u8 param2, u8 *buf, int buflen)
3541 {
3542         int r;
3543         u8 reqdata[2];
3544
3545         reqdata[0] = param1;
3546         reqdata[1] = param2;
3547
3548         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3549         if (r) {
3550                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3551                 return r;
3552         }
3553
3554         return 0;
3555 }
3556 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3557
3558 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3559                 u16 len)
3560 {
3561         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3562
3563         return dsi_vc_send_short(dsidev, channel,
3564                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3565 }
3566 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3567
3568 static int dsi_enter_ulps(struct platform_device *dsidev)
3569 {
3570         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3571         DECLARE_COMPLETION_ONSTACK(completion);
3572         int r, i;
3573         unsigned mask;
3574
3575         DSSDBGF();
3576
3577         WARN_ON(!dsi_bus_is_locked(dsidev));
3578
3579         WARN_ON(dsi->ulps_enabled);
3580
3581         if (dsi->ulps_enabled)
3582                 return 0;
3583
3584         /* DDR_CLK_ALWAYS_ON */
3585         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3586                 dsi_if_enable(dsidev, 0);
3587                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3588                 dsi_if_enable(dsidev, 1);
3589         }
3590
3591         dsi_sync_vc(dsidev, 0);
3592         dsi_sync_vc(dsidev, 1);
3593         dsi_sync_vc(dsidev, 2);
3594         dsi_sync_vc(dsidev, 3);
3595
3596         dsi_force_tx_stop_mode_io(dsidev);
3597
3598         dsi_vc_enable(dsidev, 0, false);
3599         dsi_vc_enable(dsidev, 1, false);
3600         dsi_vc_enable(dsidev, 2, false);
3601         dsi_vc_enable(dsidev, 3, false);
3602
3603         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3604                 DSSERR("HS busy when enabling ULPS\n");
3605                 return -EIO;
3606         }
3607
3608         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3609                 DSSERR("LP busy when enabling ULPS\n");
3610                 return -EIO;
3611         }
3612
3613         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3614                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3615         if (r)
3616                 return r;
3617
3618         mask = 0;
3619
3620         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3621                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3622                         continue;
3623                 mask |= 1 << i;
3624         }
3625         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3626         /* LANEx_ULPS_SIG2 */
3627         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3628
3629         /* flush posted write and wait for SCP interface to finish the write */
3630         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3631
3632         if (wait_for_completion_timeout(&completion,
3633                                 msecs_to_jiffies(1000)) == 0) {
3634                 DSSERR("ULPS enable timeout\n");
3635                 r = -EIO;
3636                 goto err;
3637         }
3638
3639         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3640                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3641
3642         /* Reset LANEx_ULPS_SIG2 */
3643         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3644
3645         /* flush posted write and wait for SCP interface to finish the write */
3646         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3647
3648         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3649
3650         dsi_if_enable(dsidev, false);
3651
3652         dsi->ulps_enabled = true;
3653
3654         return 0;
3655
3656 err:
3657         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3658                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3659         return r;
3660 }
3661
3662 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3663                 unsigned ticks, bool x4, bool x16)
3664 {
3665         unsigned long fck;
3666         unsigned long total_ticks;
3667         u32 r;
3668
3669         BUG_ON(ticks > 0x1fff);
3670
3671         /* ticks in DSI_FCK */
3672         fck = dsi_fclk_rate(dsidev);
3673
3674         r = dsi_read_reg(dsidev, DSI_TIMING2);
3675         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3676         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3677         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3678         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3679         dsi_write_reg(dsidev, DSI_TIMING2, r);
3680
3681         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3682
3683         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3684                         total_ticks,
3685                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3686                         (total_ticks * 1000) / (fck / 1000 / 1000));
3687 }
3688
3689 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3690                 bool x8, bool x16)
3691 {
3692         unsigned long fck;
3693         unsigned long total_ticks;
3694         u32 r;
3695
3696         BUG_ON(ticks > 0x1fff);
3697
3698         /* ticks in DSI_FCK */
3699         fck = dsi_fclk_rate(dsidev);
3700
3701         r = dsi_read_reg(dsidev, DSI_TIMING1);
3702         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3703         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3704         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3705         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3706         dsi_write_reg(dsidev, DSI_TIMING1, r);
3707
3708         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3709
3710         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3711                         total_ticks,
3712                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3713                         (total_ticks * 1000) / (fck / 1000 / 1000));
3714 }
3715
3716 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3717                 unsigned ticks, bool x4, bool x16)
3718 {
3719         unsigned long fck;
3720         unsigned long total_ticks;
3721         u32 r;
3722
3723         BUG_ON(ticks > 0x1fff);
3724
3725         /* ticks in DSI_FCK */
3726         fck = dsi_fclk_rate(dsidev);
3727
3728         r = dsi_read_reg(dsidev, DSI_TIMING1);
3729         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3730         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3731         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3732         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3733         dsi_write_reg(dsidev, DSI_TIMING1, r);
3734
3735         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3736
3737         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3738                         total_ticks,
3739                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3740                         (total_ticks * 1000) / (fck / 1000 / 1000));
3741 }
3742
3743 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3744                 unsigned ticks, bool x4, bool x16)
3745 {
3746         unsigned long fck;
3747         unsigned long total_ticks;
3748         u32 r;
3749
3750         BUG_ON(ticks > 0x1fff);
3751
3752         /* ticks in TxByteClkHS */
3753         fck = dsi_get_txbyteclkhs(dsidev);
3754
3755         r = dsi_read_reg(dsidev, DSI_TIMING2);
3756         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3757         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3758         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3759         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3760         dsi_write_reg(dsidev, DSI_TIMING2, r);
3761
3762         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3763
3764         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3765                         total_ticks,
3766                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3767                         (total_ticks * 1000) / (fck / 1000 / 1000));
3768 }
3769
3770 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3771 {
3772         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3773         int num_line_buffers;
3774
3775         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3776                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3777                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3778                 struct omap_video_timings *timings = &dsi->timings;
3779                 /*
3780                  * Don't use line buffers if width is greater than the video
3781                  * port's line buffer size
3782                  */
3783                 if (line_buf_size <= timings->x_res * bpp / 8)
3784                         num_line_buffers = 0;
3785                 else
3786                         num_line_buffers = 2;
3787         } else {
3788                 /* Use maximum number of line buffers in command mode */
3789                 num_line_buffers = 2;
3790         }
3791
3792         /* LINE_BUFFER */
3793         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3794 }
3795
3796 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3797 {
3798         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3799         bool vsync_end = dsi->vm_timings.vp_vsync_end;
3800         bool hsync_end = dsi->vm_timings.vp_hsync_end;
3801         u32 r;
3802
3803         r = dsi_read_reg(dsidev, DSI_CTRL);
3804         r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
3805         r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
3806         r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
3807         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3808         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3809         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3810         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3811         dsi_write_reg(dsidev, DSI_CTRL, r);
3812 }
3813
3814 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3815 {
3816         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3817         int blanking_mode = dsi->vm_timings.blanking_mode;
3818         int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3819         int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3820         int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3821         u32 r;
3822
3823         /*
3824          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3825          * 1 = Long blanking packets are sent in corresponding blanking periods
3826          */
3827         r = dsi_read_reg(dsidev, DSI_CTRL);
3828         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3829         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3830         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3831         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3832         dsi_write_reg(dsidev, DSI_CTRL, r);
3833 }
3834
3835 /*
3836  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3837  * results in maximum transition time for data and clock lanes to enter and
3838  * exit HS mode. Hence, this is the scenario where the least amount of command
3839  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3840  * clock cycles that can be used to interleave command mode data in HS so that
3841  * all scenarios are satisfied.
3842  */
3843 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3844                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3845 {
3846         int transition;
3847
3848         /*
3849          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3850          * time of data lanes only, if it isn't set, we need to consider HS
3851          * transition time of both data and clock lanes. HS transition time
3852          * of Scenario 3 is considered.
3853          */
3854         if (ddr_alwon) {
3855                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3856         } else {
3857                 int trans1, trans2;
3858                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3859                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3860                                 enter_hs + 1;
3861                 transition = max(trans1, trans2);
3862         }
3863
3864         return blank > transition ? blank - transition : 0;
3865 }
3866
3867 /*
3868  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3869  * results in maximum transition time for data lanes to enter and exit LP mode.
3870  * Hence, this is the scenario where the least amount of command mode data can
3871  * be interleaved. We program the minimum amount of bytes that can be
3872  * interleaved in LP so that all scenarios are satisfied.
3873  */
3874 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3875                 int lp_clk_div, int tdsi_fclk)
3876 {
3877         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3878         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3879         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3880         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3881         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3882
3883         /* maximum LP transition time according to Scenario 1 */
3884         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3885
3886         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3887         tlp_avail = thsbyte_clk * (blank - trans_lp);
3888
3889         ttxclkesc = tdsi_fclk * lp_clk_div;
3890
3891         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3892                         26) / 16;
3893
3894         return max(lp_inter, 0);
3895 }
3896
3897 static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
3898 {
3899         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3900         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3901         int blanking_mode;
3902         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3903         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3904         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3905         int tclk_trail, ths_exit, exiths_clk;
3906         bool ddr_alwon;
3907         struct omap_video_timings *timings = &dsi->timings;
3908         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3909         int ndl = dsi->num_lanes_used - 1;
3910         int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
3911         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3912         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3913         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3914         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3915         u32 r;
3916
3917         r = dsi_read_reg(dsidev, DSI_CTRL);
3918         blanking_mode = FLD_GET(r, 20, 20);
3919         hfp_blanking_mode = FLD_GET(r, 21, 21);
3920         hbp_blanking_mode = FLD_GET(r, 22, 22);
3921         hsa_blanking_mode = FLD_GET(r, 23, 23);
3922
3923         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3924         hbp = FLD_GET(r, 11, 0);
3925         hfp = FLD_GET(r, 23, 12);
3926         hsa = FLD_GET(r, 31, 24);
3927
3928         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3929         ddr_clk_post = FLD_GET(r, 7, 0);
3930         ddr_clk_pre = FLD_GET(r, 15, 8);
3931
3932         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3933         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3934         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3935
3936         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3937         lp_clk_div = FLD_GET(r, 12, 0);
3938         ddr_alwon = FLD_GET(r, 13, 13);
3939
3940         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3941         ths_exit = FLD_GET(r, 7, 0);
3942
3943         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3944         tclk_trail = FLD_GET(r, 15, 8);
3945
3946         exiths_clk = ths_exit + tclk_trail;
3947
3948         width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3949         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3950
3951         if (!hsa_blanking_mode) {
3952                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3953                                         enter_hs_mode_lat, exit_hs_mode_lat,
3954                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3955                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3956                                         enter_hs_mode_lat, exit_hs_mode_lat,
3957                                         lp_clk_div, dsi_fclk_hsdiv);
3958         }
3959
3960         if (!hfp_blanking_mode) {
3961                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3962                                         enter_hs_mode_lat, exit_hs_mode_lat,
3963                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3964                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3965                                         enter_hs_mode_lat, exit_hs_mode_lat,
3966                                         lp_clk_div, dsi_fclk_hsdiv);
3967         }
3968
3969         if (!hbp_blanking_mode) {
3970                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3971                                         enter_hs_mode_lat, exit_hs_mode_lat,
3972                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3973
3974                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3975                                         enter_hs_mode_lat, exit_hs_mode_lat,
3976                                         lp_clk_div, dsi_fclk_hsdiv);
3977         }
3978
3979         if (!blanking_mode) {
3980                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3981                                         enter_hs_mode_lat, exit_hs_mode_lat,
3982                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3983
3984                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3985                                         enter_hs_mode_lat, exit_hs_mode_lat,
3986                                         lp_clk_div, dsi_fclk_hsdiv);
3987         }
3988
3989         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3990                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3991                 bl_interleave_hs);
3992
3993         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3994                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3995                 bl_interleave_lp);
3996
3997         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3998         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3999         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
4000         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
4001         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
4002
4003         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
4004         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
4005         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
4006         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
4007         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
4008
4009         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
4010         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
4011         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
4012         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
4013 }
4014
4015 static int dsi_proto_config(struct omap_dss_device *dssdev)
4016 {
4017         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4018         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4019         u32 r;
4020         int buswidth = 0;
4021
4022         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
4023                         DSI_FIFO_SIZE_32,
4024                         DSI_FIFO_SIZE_32,
4025                         DSI_FIFO_SIZE_32);
4026
4027         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
4028                         DSI_FIFO_SIZE_32,
4029                         DSI_FIFO_SIZE_32,
4030                         DSI_FIFO_SIZE_32);
4031
4032         /* XXX what values for the timeouts? */
4033         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
4034         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
4035         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
4036         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
4037
4038         switch (dsi_get_pixel_size(dsi->pix_fmt)) {
4039         case 16:
4040                 buswidth = 0;
4041                 break;
4042         case 18:
4043                 buswidth = 1;
4044                 break;
4045         case 24:
4046                 buswidth = 2;
4047                 break;
4048         default:
4049                 BUG();
4050                 return -EINVAL;
4051         }
4052
4053         r = dsi_read_reg(dsidev, DSI_CTRL);
4054         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
4055         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
4056         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
4057         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
4058         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
4059         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
4060         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
4061         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
4062         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
4063                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
4064                 /* DCS_CMD_CODE, 1=start, 0=continue */
4065                 r = FLD_MOD(r, 0, 25, 25);
4066         }
4067
4068         dsi_write_reg(dsidev, DSI_CTRL, r);
4069
4070         dsi_config_vp_num_line_buffers(dsidev);
4071
4072         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4073                 dsi_config_vp_sync_events(dsidev);
4074                 dsi_config_blanking_modes(dsidev);
4075                 dsi_config_cmd_mode_interleaving(dssdev);
4076         }
4077
4078         dsi_vc_initial_config(dsidev, 0);
4079         dsi_vc_initial_config(dsidev, 1);
4080         dsi_vc_initial_config(dsidev, 2);
4081         dsi_vc_initial_config(dsidev, 3);
4082
4083         return 0;
4084 }
4085
4086 static void dsi_proto_timings(struct platform_device *dsidev)
4087 {
4088         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4089         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
4090         unsigned tclk_pre, tclk_post;
4091         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
4092         unsigned ths_trail, ths_exit;
4093         unsigned ddr_clk_pre, ddr_clk_post;
4094         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
4095         unsigned ths_eot;
4096         int ndl = dsi->num_lanes_used - 1;
4097         u32 r;
4098
4099         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
4100         ths_prepare = FLD_GET(r, 31, 24);
4101         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
4102         ths_zero = ths_prepare_ths_zero - ths_prepare;
4103         ths_trail = FLD_GET(r, 15, 8);
4104         ths_exit = FLD_GET(r, 7, 0);
4105
4106         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
4107         tlpx = FLD_GET(r, 20, 16) * 2;
4108         tclk_trail = FLD_GET(r, 15, 8);
4109         tclk_zero = FLD_GET(r, 7, 0);
4110
4111         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
4112         tclk_prepare = FLD_GET(r, 7, 0);
4113
4114         /* min 8*UI */
4115         tclk_pre = 20;
4116         /* min 60ns + 52*UI */
4117         tclk_post = ns2ddr(dsidev, 60) + 26;
4118
4119         ths_eot = DIV_ROUND_UP(4, ndl);
4120
4121         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4122                         4);
4123         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
4124
4125         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
4126         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
4127
4128         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
4129         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
4130         r = FLD_MOD(r, ddr_clk_post, 7, 0);
4131         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
4132
4133         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
4134                         ddr_clk_pre,
4135                         ddr_clk_post);
4136
4137         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
4138                 DIV_ROUND_UP(ths_prepare, 4) +
4139                 DIV_ROUND_UP(ths_zero + 3, 4);
4140
4141         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
4142
4143         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
4144                 FLD_VAL(exit_hs_mode_lat, 15, 0);
4145         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
4146
4147         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4148                         enter_hs_mode_lat, exit_hs_mode_lat);
4149
4150          if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4151                 /* TODO: Implement a video mode check_timings function */
4152                 int hsa = dsi->vm_timings.hsa;
4153                 int hfp = dsi->vm_timings.hfp;
4154                 int hbp = dsi->vm_timings.hbp;
4155                 int vsa = dsi->vm_timings.vsa;
4156                 int vfp = dsi->vm_timings.vfp;
4157                 int vbp = dsi->vm_timings.vbp;
4158                 int window_sync = dsi->vm_timings.window_sync;
4159                 bool hsync_end = dsi->vm_timings.vp_hsync_end;
4160                 struct omap_video_timings *timings = &dsi->timings;
4161                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4162                 int tl, t_he, width_bytes;
4163
4164                 t_he = hsync_end ?
4165                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4166
4167                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4168
4169                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4170                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4171                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4172
4173                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4174                         hfp, hsync_end ? hsa : 0, tl);
4175                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4176                         vsa, timings->y_res);
4177
4178                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4179                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
4180                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
4181                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
4182                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4183
4184                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4185                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
4186                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
4187                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
4188                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
4189                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4190
4191                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4192                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
4193                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
4194                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4195         }
4196 }
4197
4198 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4199                 const struct omap_dsi_pin_config *pin_cfg)
4200 {
4201         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4202         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4203         int num_pins;
4204         const int *pins;
4205         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4206         int num_lanes;
4207         int i;
4208
4209         static const enum dsi_lane_function functions[] = {
4210                 DSI_LANE_CLK,
4211                 DSI_LANE_DATA1,
4212                 DSI_LANE_DATA2,
4213                 DSI_LANE_DATA3,
4214                 DSI_LANE_DATA4,
4215         };
4216
4217         num_pins = pin_cfg->num_pins;
4218         pins = pin_cfg->pins;
4219
4220         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4221                         || num_pins % 2 != 0)
4222                 return -EINVAL;
4223
4224         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4225                 lanes[i].function = DSI_LANE_UNUSED;
4226
4227         num_lanes = 0;
4228
4229         for (i = 0; i < num_pins; i += 2) {
4230                 u8 lane, pol;
4231                 int dx, dy;
4232
4233                 dx = pins[i];
4234                 dy = pins[i + 1];
4235
4236                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4237                         return -EINVAL;
4238
4239                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4240                         return -EINVAL;
4241
4242                 if (dx & 1) {
4243                         if (dy != dx - 1)
4244                                 return -EINVAL;
4245                         pol = 1;
4246                 } else {
4247                         if (dy != dx + 1)
4248                                 return -EINVAL;
4249                         pol = 0;
4250                 }
4251
4252                 lane = dx / 2;
4253
4254                 lanes[lane].function = functions[i / 2];
4255                 lanes[lane].polarity = pol;
4256                 num_lanes++;
4257         }
4258
4259         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4260         dsi->num_lanes_used = num_lanes;
4261
4262         return 0;
4263 }
4264 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4265
4266 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
4267                 unsigned long ddr_clk, unsigned long lp_clk)
4268 {
4269         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4270         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4271         struct dsi_clock_info cinfo;
4272         struct dispc_clock_info dispc_cinfo;
4273         unsigned lp_clk_div;
4274         unsigned long dsi_fclk;
4275         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4276         unsigned long pck;
4277         int r;
4278
4279         DSSDBGF("ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
4280
4281         mutex_lock(&dsi->lock);
4282
4283         /* Calculate PLL output clock */
4284         r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
4285         if (r)
4286                 goto err;
4287
4288         /* Calculate PLL's DSI clock */
4289         dsi_pll_calc_dsi_fck(dsidev, &cinfo);
4290
4291         /* Calculate PLL's DISPC clock and pck & lck divs */
4292         pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
4293         DSSDBG("finding dispc dividers for pck %lu\n", pck);
4294         r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
4295         if (r)
4296                 goto err;
4297
4298         /* Calculate LP clock */
4299         dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
4300         lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
4301
4302         dssdev->clocks.dsi.regn = cinfo.regn;
4303         dssdev->clocks.dsi.regm = cinfo.regm;
4304         dssdev->clocks.dsi.regm_dispc = cinfo.regm_dispc;
4305         dssdev->clocks.dsi.regm_dsi = cinfo.regm_dsi;
4306
4307         dssdev->clocks.dsi.lp_clk_div = lp_clk_div;
4308
4309         dssdev->clocks.dispc.channel.lck_div = dispc_cinfo.lck_div;
4310         dssdev->clocks.dispc.channel.pck_div = dispc_cinfo.pck_div;
4311
4312         dssdev->clocks.dispc.dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
4313
4314         dssdev->clocks.dispc.channel.lcd_clk_src =
4315                 dsi->module_id == 0 ?
4316                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4317                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
4318
4319         dssdev->clocks.dsi.dsi_fclk_src =
4320                 dsi->module_id == 0 ?
4321                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4322                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI;
4323
4324         mutex_unlock(&dsi->lock);
4325         return 0;
4326 err:
4327         mutex_unlock(&dsi->lock);
4328         return r;
4329 }
4330 EXPORT_SYMBOL(omapdss_dsi_set_clocks);
4331
4332 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4333 {
4334         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4335         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4336         struct omap_overlay_manager *mgr = dssdev->output->manager;
4337         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4338         u8 data_type;
4339         u16 word_count;
4340         int r;
4341
4342         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4343                 switch (dsi->pix_fmt) {
4344                 case OMAP_DSS_DSI_FMT_RGB888:
4345                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4346                         break;
4347                 case OMAP_DSS_DSI_FMT_RGB666:
4348                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4349                         break;
4350                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4351                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4352                         break;
4353                 case OMAP_DSS_DSI_FMT_RGB565:
4354                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4355                         break;
4356                 default:
4357                         BUG();
4358                         return -EINVAL;
4359                 };
4360
4361                 dsi_if_enable(dsidev, false);
4362                 dsi_vc_enable(dsidev, channel, false);
4363
4364                 /* MODE, 1 = video mode */
4365                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4366
4367                 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4368
4369                 dsi_vc_write_long_header(dsidev, channel, data_type,
4370                                 word_count, 0);
4371
4372                 dsi_vc_enable(dsidev, channel, true);
4373                 dsi_if_enable(dsidev, true);
4374         }
4375
4376         r = dss_mgr_enable(mgr);
4377         if (r) {
4378                 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4379                         dsi_if_enable(dsidev, false);
4380                         dsi_vc_enable(dsidev, channel, false);
4381                 }
4382
4383                 return r;
4384         }
4385
4386         return 0;
4387 }
4388 EXPORT_SYMBOL(dsi_enable_video_output);
4389
4390 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4391 {
4392         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4393         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4394         struct omap_overlay_manager *mgr = dssdev->output->manager;
4395
4396         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4397                 dsi_if_enable(dsidev, false);
4398                 dsi_vc_enable(dsidev, channel, false);
4399
4400                 /* MODE, 0 = command mode */
4401                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4402
4403                 dsi_vc_enable(dsidev, channel, true);
4404                 dsi_if_enable(dsidev, true);
4405         }
4406
4407         dss_mgr_disable(mgr);
4408 }
4409 EXPORT_SYMBOL(dsi_disable_video_output);
4410
4411 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev)
4412 {
4413         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4414         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4415         struct omap_overlay_manager *mgr = dssdev->output->manager;
4416         unsigned bytespp;
4417         unsigned bytespl;
4418         unsigned bytespf;
4419         unsigned total_len;
4420         unsigned packet_payload;
4421         unsigned packet_len;
4422         u32 l;
4423         int r;
4424         const unsigned channel = dsi->update_channel;
4425         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4426         u16 w = dsi->timings.x_res;
4427         u16 h = dsi->timings.y_res;
4428
4429         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4430
4431         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4432
4433         bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4434         bytespl = w * bytespp;
4435         bytespf = bytespl * h;
4436
4437         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4438          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4439
4440         if (bytespf < line_buf_size)
4441                 packet_payload = bytespf;
4442         else
4443                 packet_payload = (line_buf_size) / bytespl * bytespl;
4444
4445         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4446         total_len = (bytespf / packet_payload) * packet_len;
4447
4448         if (bytespf % packet_payload)
4449                 total_len += (bytespf % packet_payload) + 1;
4450
4451         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4452         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4453
4454         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4455                 packet_len, 0);
4456
4457         if (dsi->te_enabled)
4458                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4459         else
4460                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4461         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4462
4463         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4464          * because DSS interrupts are not capable of waking up the CPU and the
4465          * framedone interrupt could be delayed for quite a long time. I think
4466          * the same goes for any DSS interrupts, but for some reason I have not
4467          * seen the problem anywhere else than here.
4468          */
4469         dispc_disable_sidle();
4470
4471         dsi_perf_mark_start(dsidev);
4472
4473         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4474                 msecs_to_jiffies(250));
4475         BUG_ON(r == 0);
4476
4477         dss_mgr_set_timings(mgr, &dsi->timings);
4478
4479         dss_mgr_start_update(mgr);
4480
4481         if (dsi->te_enabled) {
4482                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4483                  * for TE is longer than the timer allows */
4484                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4485
4486                 dsi_vc_send_bta(dsidev, channel);
4487
4488 #ifdef DSI_CATCH_MISSING_TE
4489                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4490 #endif
4491         }
4492 }
4493
4494 #ifdef DSI_CATCH_MISSING_TE
4495 static void dsi_te_timeout(unsigned long arg)
4496 {
4497         DSSERR("TE not received for 250ms!\n");
4498 }
4499 #endif
4500
4501 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4502 {
4503         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4504
4505         /* SIDLEMODE back to smart-idle */
4506         dispc_enable_sidle();
4507
4508         if (dsi->te_enabled) {
4509                 /* enable LP_RX_TO again after the TE */
4510                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4511         }
4512
4513         dsi->framedone_callback(error, dsi->framedone_data);
4514
4515         if (!error)
4516                 dsi_perf_show(dsidev, "DISPC");
4517 }
4518
4519 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4520 {
4521         struct dsi_data *dsi = container_of(work, struct dsi_data,
4522                         framedone_timeout_work.work);
4523         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4524          * 250ms which would conflict with this timeout work. What should be
4525          * done is first cancel the transfer on the HW, and then cancel the
4526          * possibly scheduled framedone work. However, cancelling the transfer
4527          * on the HW is buggy, and would probably require resetting the whole
4528          * DSI */
4529
4530         DSSERR("Framedone not received for 250ms!\n");
4531
4532         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4533 }
4534
4535 static void dsi_framedone_irq_callback(void *data, u32 mask)
4536 {
4537         struct platform_device *dsidev = (struct platform_device *) data;
4538         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4539
4540         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4541          * turns itself off. However, DSI still has the pixels in its buffers,
4542          * and is sending the data.
4543          */
4544
4545         cancel_delayed_work(&dsi->framedone_timeout_work);
4546
4547         dsi_handle_framedone(dsidev, 0);
4548 }
4549
4550 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4551                 void (*callback)(int, void *), void *data)
4552 {
4553         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4554         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4555         u16 dw, dh;
4556
4557         dsi_perf_mark_setup(dsidev);
4558
4559         dsi->update_channel = channel;
4560
4561         dsi->framedone_callback = callback;
4562         dsi->framedone_data = data;
4563
4564         dw = dsi->timings.x_res;
4565         dh = dsi->timings.y_res;
4566
4567 #ifdef DEBUG
4568         dsi->update_bytes = dw * dh *
4569                 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4570 #endif
4571         dsi_update_screen_dispc(dssdev);
4572
4573         return 0;
4574 }
4575 EXPORT_SYMBOL(omap_dsi_update);
4576
4577 /* Display funcs */
4578
4579 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4580 {
4581         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4582         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4583         struct dispc_clock_info dispc_cinfo;
4584         int r;
4585         unsigned long long fck;
4586
4587         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4588
4589         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4590         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4591
4592         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4593         if (r) {
4594                 DSSERR("Failed to calc dispc clocks\n");
4595                 return r;
4596         }
4597
4598         dsi->mgr_config.clock_info = dispc_cinfo;
4599
4600         return 0;
4601 }
4602
4603 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4604 {
4605         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4606         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4607         struct omap_overlay_manager *mgr = dssdev->output->manager;
4608         int r;
4609         u32 irq = 0;
4610
4611         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4612                 dsi->timings.hsw = 1;
4613                 dsi->timings.hfp = 1;
4614                 dsi->timings.hbp = 1;
4615                 dsi->timings.vsw = 1;
4616                 dsi->timings.vfp = 0;
4617                 dsi->timings.vbp = 0;
4618
4619                 irq = dispc_mgr_get_framedone_irq(mgr->id);
4620
4621                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4622                         (void *) dsidev, irq);
4623                 if (r) {
4624                         DSSERR("can't get FRAMEDONE irq\n");
4625                         goto err;
4626                 }
4627
4628                 dsi->mgr_config.stallmode = true;
4629                 dsi->mgr_config.fifohandcheck = true;
4630         } else {
4631                 dsi->mgr_config.stallmode = false;
4632                 dsi->mgr_config.fifohandcheck = false;
4633         }
4634
4635         /*
4636          * override interlace, logic level and edge related parameters in
4637          * omap_video_timings with default values
4638          */
4639         dsi->timings.interlace = false;
4640         dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4641         dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4642         dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4643         dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4644         dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4645
4646         dss_mgr_set_timings(mgr, &dsi->timings);
4647
4648         r = dsi_configure_dispc_clocks(dssdev);
4649         if (r)
4650                 goto err1;
4651
4652         dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4653         dsi->mgr_config.video_port_width =
4654                         dsi_get_pixel_size(dsi->pix_fmt);
4655         dsi->mgr_config.lcden_sig_polarity = 0;
4656
4657         dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4658
4659         return 0;
4660 err1:
4661         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4662                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4663                         (void *) dsidev, irq);
4664 err:
4665         return r;
4666 }
4667
4668 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4669 {
4670         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4671         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4672         struct omap_overlay_manager *mgr = dssdev->output->manager;
4673
4674         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4675                 u32 irq;
4676
4677                 irq = dispc_mgr_get_framedone_irq(mgr->id);
4678
4679                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4680                         (void *) dsidev, irq);
4681         }
4682 }
4683
4684 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4685 {
4686         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4687         struct dsi_clock_info cinfo;
4688         int r;
4689
4690         cinfo.regn  = dssdev->clocks.dsi.regn;
4691         cinfo.regm  = dssdev->clocks.dsi.regm;
4692         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4693         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4694         r = dsi_calc_clock_rates(dsidev, &cinfo);
4695         if (r) {
4696                 DSSERR("Failed to calc dsi clocks\n");
4697                 return r;
4698         }
4699
4700         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4701         if (r) {
4702                 DSSERR("Failed to set dsi clocks\n");
4703                 return r;
4704         }
4705
4706         return 0;
4707 }
4708
4709 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4710 {
4711         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4712         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4713         struct omap_overlay_manager *mgr = dssdev->output->manager;
4714         int r;
4715
4716         r = dsi_pll_init(dsidev, true, true);
4717         if (r)
4718                 goto err0;
4719
4720         r = dsi_configure_dsi_clocks(dssdev);
4721         if (r)
4722                 goto err1;
4723
4724         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4725         dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
4726         dss_select_lcd_clk_source(mgr->id,
4727                         dssdev->clocks.dispc.channel.lcd_clk_src);
4728
4729         DSSDBG("PLL OK\n");
4730
4731         r = dsi_cio_init(dsidev);
4732         if (r)
4733                 goto err2;
4734
4735         _dsi_print_reset_status(dsidev);
4736
4737         dsi_proto_timings(dsidev);
4738         dsi_set_lp_clk_divisor(dssdev);
4739
4740         if (1)
4741                 _dsi_print_reset_status(dsidev);
4742
4743         r = dsi_proto_config(dssdev);
4744         if (r)
4745                 goto err3;
4746
4747         /* enable interface */
4748         dsi_vc_enable(dsidev, 0, 1);
4749         dsi_vc_enable(dsidev, 1, 1);
4750         dsi_vc_enable(dsidev, 2, 1);
4751         dsi_vc_enable(dsidev, 3, 1);
4752         dsi_if_enable(dsidev, 1);
4753         dsi_force_tx_stop_mode_io(dsidev);
4754
4755         return 0;
4756 err3:
4757         dsi_cio_uninit(dsidev);
4758 err2:
4759         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4760         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4761         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4762
4763 err1:
4764         dsi_pll_uninit(dsidev, true);
4765 err0:
4766         return r;
4767 }
4768
4769 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4770                 bool disconnect_lanes, bool enter_ulps)
4771 {
4772         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4773         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4774         struct omap_overlay_manager *mgr = dssdev->output->manager;
4775
4776         if (enter_ulps && !dsi->ulps_enabled)
4777                 dsi_enter_ulps(dsidev);
4778
4779         /* disable interface */
4780         dsi_if_enable(dsidev, 0);
4781         dsi_vc_enable(dsidev, 0, 0);
4782         dsi_vc_enable(dsidev, 1, 0);
4783         dsi_vc_enable(dsidev, 2, 0);
4784         dsi_vc_enable(dsidev, 3, 0);
4785
4786         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4787         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4788         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4789         dsi_cio_uninit(dsidev);
4790         dsi_pll_uninit(dsidev, disconnect_lanes);
4791 }
4792
4793 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4794 {
4795         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4796         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4797         struct omap_dss_output *out = dssdev->output;
4798         int r = 0;
4799
4800         DSSDBG("dsi_display_enable\n");
4801
4802         WARN_ON(!dsi_bus_is_locked(dsidev));
4803
4804         mutex_lock(&dsi->lock);
4805
4806         if (out == NULL || out->manager == NULL) {
4807                 DSSERR("failed to enable display: no output/manager\n");
4808                 r = -ENODEV;
4809                 goto err_start_dev;
4810         }
4811
4812         r = omap_dss_start_device(dssdev);
4813         if (r) {
4814                 DSSERR("failed to start device\n");
4815                 goto err_start_dev;
4816         }
4817
4818         r = dsi_runtime_get(dsidev);
4819         if (r)
4820                 goto err_get_dsi;
4821
4822         dsi_enable_pll_clock(dsidev, 1);
4823
4824         _dsi_initialize_irq(dsidev);
4825
4826         r = dsi_display_init_dispc(dssdev);
4827         if (r)
4828                 goto err_init_dispc;
4829
4830         r = dsi_display_init_dsi(dssdev);
4831         if (r)
4832                 goto err_init_dsi;
4833
4834         mutex_unlock(&dsi->lock);
4835
4836         return 0;
4837
4838 err_init_dsi:
4839         dsi_display_uninit_dispc(dssdev);
4840 err_init_dispc:
4841         dsi_enable_pll_clock(dsidev, 0);
4842         dsi_runtime_put(dsidev);
4843 err_get_dsi:
4844         omap_dss_stop_device(dssdev);
4845 err_start_dev:
4846         mutex_unlock(&dsi->lock);
4847         DSSDBG("dsi_display_enable FAILED\n");
4848         return r;
4849 }
4850 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4851
4852 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4853                 bool disconnect_lanes, bool enter_ulps)
4854 {
4855         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4856         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4857
4858         DSSDBG("dsi_display_disable\n");
4859
4860         WARN_ON(!dsi_bus_is_locked(dsidev));
4861
4862         mutex_lock(&dsi->lock);
4863
4864         dsi_sync_vc(dsidev, 0);
4865         dsi_sync_vc(dsidev, 1);
4866         dsi_sync_vc(dsidev, 2);
4867         dsi_sync_vc(dsidev, 3);
4868
4869         dsi_display_uninit_dispc(dssdev);
4870
4871         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4872
4873         dsi_runtime_put(dsidev);
4874         dsi_enable_pll_clock(dsidev, 0);
4875
4876         omap_dss_stop_device(dssdev);
4877
4878         mutex_unlock(&dsi->lock);
4879 }
4880 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4881
4882 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4883 {
4884         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4885         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4886
4887         dsi->te_enabled = enable;
4888         return 0;
4889 }
4890 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4891
4892 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
4893                 struct omap_video_timings *timings)
4894 {
4895         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4896         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4897
4898         mutex_lock(&dsi->lock);
4899
4900         dsi->timings = *timings;
4901
4902         mutex_unlock(&dsi->lock);
4903 }
4904 EXPORT_SYMBOL(omapdss_dsi_set_timings);
4905
4906 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
4907 {
4908         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4909         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4910
4911         mutex_lock(&dsi->lock);
4912
4913         dsi->timings.x_res = w;
4914         dsi->timings.y_res = h;
4915
4916         mutex_unlock(&dsi->lock);
4917 }
4918 EXPORT_SYMBOL(omapdss_dsi_set_size);
4919
4920 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
4921                 enum omap_dss_dsi_pixel_format fmt)
4922 {
4923         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4924         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4925
4926         mutex_lock(&dsi->lock);
4927
4928         dsi->pix_fmt = fmt;
4929
4930         mutex_unlock(&dsi->lock);
4931 }
4932 EXPORT_SYMBOL(omapdss_dsi_set_pixel_format);
4933
4934 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
4935                 enum omap_dss_dsi_mode mode)
4936 {
4937         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4938         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4939
4940         mutex_lock(&dsi->lock);
4941
4942         dsi->mode = mode;
4943
4944         mutex_unlock(&dsi->lock);
4945 }
4946 EXPORT_SYMBOL(omapdss_dsi_set_operation_mode);
4947
4948 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
4949                 struct omap_dss_dsi_videomode_timings *timings)
4950 {
4951         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4952         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4953
4954         mutex_lock(&dsi->lock);
4955
4956         dsi->vm_timings = *timings;
4957
4958         mutex_unlock(&dsi->lock);
4959 }
4960 EXPORT_SYMBOL(omapdss_dsi_set_videomode_timings);
4961
4962 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4963 {
4964         struct platform_device *dsidev =
4965                         dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
4966         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4967
4968         DSSDBG("DSI init\n");
4969
4970         if (dsi->vdds_dsi_reg == NULL) {
4971                 struct regulator *vdds_dsi;
4972
4973                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4974
4975                 if (IS_ERR(vdds_dsi)) {
4976                         DSSERR("can't get VDDS_DSI regulator\n");
4977                         return PTR_ERR(vdds_dsi);
4978                 }
4979
4980                 dsi->vdds_dsi_reg = vdds_dsi;
4981         }
4982
4983         return 0;
4984 }
4985
4986 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4987 {
4988         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4989         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4990         int i;
4991
4992         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4993                 if (!dsi->vc[i].dssdev) {
4994                         dsi->vc[i].dssdev = dssdev;
4995                         *channel = i;
4996                         return 0;
4997                 }
4998         }
4999
5000         DSSERR("cannot get VC for display %s", dssdev->name);
5001         return -ENOSPC;
5002 }
5003 EXPORT_SYMBOL(omap_dsi_request_vc);
5004
5005 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5006 {
5007         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5008         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5009
5010         if (vc_id < 0 || vc_id > 3) {
5011                 DSSERR("VC ID out of range\n");
5012                 return -EINVAL;
5013         }
5014
5015         if (channel < 0 || channel > 3) {
5016                 DSSERR("Virtual Channel out of range\n");
5017                 return -EINVAL;
5018         }
5019
5020         if (dsi->vc[channel].dssdev != dssdev) {
5021                 DSSERR("Virtual Channel not allocated to display %s\n",
5022                         dssdev->name);
5023                 return -EINVAL;
5024         }
5025
5026         dsi->vc[channel].vc_id = vc_id;
5027
5028         return 0;
5029 }
5030 EXPORT_SYMBOL(omap_dsi_set_vc_id);
5031
5032 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5033 {
5034         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5035         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5036
5037         if ((channel >= 0 && channel <= 3) &&
5038                 dsi->vc[channel].dssdev == dssdev) {
5039                 dsi->vc[channel].dssdev = NULL;
5040                 dsi->vc[channel].vc_id = 0;
5041         }
5042 }
5043 EXPORT_SYMBOL(omap_dsi_release_vc);
5044
5045 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5046 {
5047         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5048                 DSSERR("%s (%s) not active\n",
5049                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5050                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5051 }
5052
5053 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5054 {
5055         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5056                 DSSERR("%s (%s) not active\n",
5057                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5058                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5059 }
5060
5061 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5062 {
5063         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5064
5065         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5066         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5067         dsi->regm_dispc_max =
5068                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5069         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5070         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5071         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5072         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5073 }
5074
5075 static int dsi_get_clocks(struct platform_device *dsidev)
5076 {
5077         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5078         struct clk *clk;
5079
5080         clk = clk_get(&dsidev->dev, "fck");
5081         if (IS_ERR(clk)) {
5082                 DSSERR("can't get fck\n");
5083                 return PTR_ERR(clk);
5084         }
5085
5086         dsi->dss_clk = clk;
5087
5088         clk = clk_get(&dsidev->dev, "sys_clk");
5089         if (IS_ERR(clk)) {
5090                 DSSERR("can't get sys_clk\n");
5091                 clk_put(dsi->dss_clk);
5092                 dsi->dss_clk = NULL;
5093                 return PTR_ERR(clk);
5094         }
5095
5096         dsi->sys_clk = clk;
5097
5098         return 0;
5099 }
5100
5101 static void dsi_put_clocks(struct platform_device *dsidev)
5102 {
5103         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5104
5105         if (dsi->dss_clk)
5106                 clk_put(dsi->dss_clk);
5107         if (dsi->sys_clk)
5108                 clk_put(dsi->sys_clk);
5109 }
5110
5111 static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev)
5112 {
5113         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5114         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5115         const char *def_disp_name = dss_get_default_display_name();
5116         struct omap_dss_device *def_dssdev;
5117         int i;
5118
5119         def_dssdev = NULL;
5120
5121         for (i = 0; i < pdata->num_devices; ++i) {
5122                 struct omap_dss_device *dssdev = pdata->devices[i];
5123
5124                 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5125                         continue;
5126
5127                 if (dssdev->phy.dsi.module != dsi->module_id)
5128                         continue;
5129
5130                 if (def_dssdev == NULL)
5131                         def_dssdev = dssdev;
5132
5133                 if (def_disp_name != NULL &&
5134                                 strcmp(dssdev->name, def_disp_name) == 0) {
5135                         def_dssdev = dssdev;
5136                         break;
5137                 }
5138         }
5139
5140         return def_dssdev;
5141 }
5142
5143 static void __init dsi_probe_pdata(struct platform_device *dsidev)
5144 {
5145         struct omap_dss_device *plat_dssdev;
5146         struct omap_dss_device *dssdev;
5147         int r;
5148
5149         plat_dssdev = dsi_find_dssdev(dsidev);
5150
5151         if (!plat_dssdev)
5152                 return;
5153
5154         dssdev = dss_alloc_and_init_device(&dsidev->dev);
5155         if (!dssdev)
5156                 return;
5157
5158         dss_copy_device_pdata(dssdev, plat_dssdev);
5159
5160         r = dsi_init_display(dssdev);
5161         if (r) {
5162                 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5163                 dss_put_device(dssdev);
5164                 return;
5165         }
5166
5167         r = dss_add_device(dssdev);
5168         if (r) {
5169                 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5170                 dss_put_device(dssdev);
5171                 return;
5172         }
5173 }
5174
5175 static void __init dsi_init_output(struct platform_device *dsidev)
5176 {
5177         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5178         struct omap_dss_output *out = &dsi->output;
5179
5180         out->pdev = dsidev;
5181         out->id = dsi->module_id == 0 ?
5182                         OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5183
5184         out->type = OMAP_DISPLAY_TYPE_DSI;
5185
5186         dss_register_output(out);
5187 }
5188
5189 static void __exit dsi_uninit_output(struct platform_device *dsidev)
5190 {
5191         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5192         struct omap_dss_output *out = &dsi->output;
5193
5194         dss_unregister_output(out);
5195 }
5196
5197 /* DSI1 HW IP initialisation */
5198 static int __init omap_dsihw_probe(struct platform_device *dsidev)
5199 {
5200         u32 rev;
5201         int r, i;
5202         struct resource *dsi_mem;
5203         struct dsi_data *dsi;
5204
5205         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5206         if (!dsi)
5207                 return -ENOMEM;
5208
5209         dsi->module_id = dsidev->id;
5210         dsi->pdev = dsidev;
5211         dev_set_drvdata(&dsidev->dev, dsi);
5212
5213         spin_lock_init(&dsi->irq_lock);
5214         spin_lock_init(&dsi->errors_lock);
5215         dsi->errors = 0;
5216
5217 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5218         spin_lock_init(&dsi->irq_stats_lock);
5219         dsi->irq_stats.last_reset = jiffies;
5220 #endif
5221
5222         mutex_init(&dsi->lock);
5223         sema_init(&dsi->bus_lock, 1);
5224
5225         INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5226                              dsi_framedone_timeout_work_callback);
5227
5228 #ifdef DSI_CATCH_MISSING_TE
5229         init_timer(&dsi->te_timer);
5230         dsi->te_timer.function = dsi_te_timeout;
5231         dsi->te_timer.data = 0;
5232 #endif
5233         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5234         if (!dsi_mem) {
5235                 DSSERR("can't get IORESOURCE_MEM DSI\n");
5236                 return -EINVAL;
5237         }
5238
5239         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5240                                  resource_size(dsi_mem));
5241         if (!dsi->base) {
5242                 DSSERR("can't ioremap DSI\n");
5243                 return -ENOMEM;
5244         }
5245
5246         dsi->irq = platform_get_irq(dsi->pdev, 0);
5247         if (dsi->irq < 0) {
5248                 DSSERR("platform_get_irq failed\n");
5249                 return -ENODEV;
5250         }
5251
5252         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5253                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5254         if (r < 0) {
5255                 DSSERR("request_irq failed\n");
5256                 return r;
5257         }
5258
5259         /* DSI VCs initialization */
5260         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5261                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5262                 dsi->vc[i].dssdev = NULL;
5263                 dsi->vc[i].vc_id = 0;
5264         }
5265
5266         dsi_calc_clock_param_ranges(dsidev);
5267
5268         r = dsi_get_clocks(dsidev);
5269         if (r)
5270                 return r;
5271
5272         pm_runtime_enable(&dsidev->dev);
5273
5274         r = dsi_runtime_get(dsidev);
5275         if (r)
5276                 goto err_runtime_get;
5277
5278         rev = dsi_read_reg(dsidev, DSI_REVISION);
5279         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5280                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5281
5282         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5283          * of data to 3 by default */
5284         if (dss_has_feature(FEAT_DSI_GNQ))
5285                 /* NB_DATA_LANES */
5286                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5287         else
5288                 dsi->num_lanes_supported = 3;
5289
5290         dsi_init_output(dsidev);
5291
5292         dsi_probe_pdata(dsidev);
5293
5294         dsi_runtime_put(dsidev);
5295
5296         if (dsi->module_id == 0)
5297                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5298         else if (dsi->module_id == 1)
5299                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5300
5301 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5302         if (dsi->module_id == 0)
5303                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5304         else if (dsi->module_id == 1)
5305                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5306 #endif
5307         return 0;
5308
5309 err_runtime_get:
5310         pm_runtime_disable(&dsidev->dev);
5311         dsi_put_clocks(dsidev);
5312         return r;
5313 }
5314
5315 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5316 {
5317         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5318
5319         WARN_ON(dsi->scp_clk_refcount > 0);
5320
5321         dss_unregister_child_devices(&dsidev->dev);
5322
5323         dsi_uninit_output(dsidev);
5324
5325         pm_runtime_disable(&dsidev->dev);
5326
5327         dsi_put_clocks(dsidev);
5328
5329         if (dsi->vdds_dsi_reg != NULL) {
5330                 if (dsi->vdds_dsi_enabled) {
5331                         regulator_disable(dsi->vdds_dsi_reg);
5332                         dsi->vdds_dsi_enabled = false;
5333                 }
5334
5335                 regulator_put(dsi->vdds_dsi_reg);
5336                 dsi->vdds_dsi_reg = NULL;
5337         }
5338
5339         return 0;
5340 }
5341
5342 static int dsi_runtime_suspend(struct device *dev)
5343 {
5344         dispc_runtime_put();
5345
5346         return 0;
5347 }
5348
5349 static int dsi_runtime_resume(struct device *dev)
5350 {
5351         int r;
5352
5353         r = dispc_runtime_get();
5354         if (r)
5355                 return r;
5356
5357         return 0;
5358 }
5359
5360 static const struct dev_pm_ops dsi_pm_ops = {
5361         .runtime_suspend = dsi_runtime_suspend,
5362         .runtime_resume = dsi_runtime_resume,
5363 };
5364
5365 static struct platform_driver omap_dsihw_driver = {
5366         .remove         = __exit_p(omap_dsihw_remove),
5367         .driver         = {
5368                 .name   = "omapdss_dsi",
5369                 .owner  = THIS_MODULE,
5370                 .pm     = &dsi_pm_ops,
5371         },
5372 };
5373
5374 int __init dsi_init_platform_driver(void)
5375 {
5376         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
5377 }
5378
5379 void __exit dsi_uninit_platform_driver(void)
5380 {
5381         platform_driver_unregister(&omap_dsihw_driver);
5382 }