drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44
  45 #include "dss.h"
  46 #include "dss_features.h"
  47
  48 #define DSI_CATCH_MISSING_TE
  49
  50 struct dsi_reg { u16 idx; };
  51
  52 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  53
  54 #define DSI_SZ_REGS             SZ_1K
  55 /* DSI Protocol Engine */
  56
  57 #define DSI_REVISION                    DSI_REG(0x0000)
  58 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  59 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  60 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  61 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  62 #define DSI_CTRL                        DSI_REG(0x0040)
  63 #define DSI_GNQ                         DSI_REG(0x0044)
  64 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  65 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  66 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  67 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  68 #define DSI_TIMING1                     DSI_REG(0x0058)
  69 #define DSI_TIMING2                     DSI_REG(0x005C)
  70 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  71 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  72 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  73 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  74 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  75 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  76 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  77 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  78 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  79 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  80 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  81 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  82 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  83 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  84 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  85 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  86 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  87 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  88 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  89 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  90 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  91
  92 /* DSIPHY_SCP */
  93
  94 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  95 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  96 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  97 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
  98 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
  99
 100 /* DSI_PLL_CTRL_SCP */
 101
 102 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 103 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 104 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 105 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 106 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 107
 108 #define REG_GET(dsidev, idx, start, end) \
 109         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 110
 111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 112         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 113
 114 /* Global interrupts */
 115 #define DSI_IRQ_VC0             (1 << 0)
 116 #define DSI_IRQ_VC1             (1 << 1)
 117 #define DSI_IRQ_VC2             (1 << 2)
 118 #define DSI_IRQ_VC3             (1 << 3)
 119 #define DSI_IRQ_WAKEUP          (1 << 4)
 120 #define DSI_IRQ_RESYNC          (1 << 5)
 121 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 122 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 123 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 124 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 125 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 126 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 127 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 128 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 129 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 130 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 131 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 132 #define DSI_IRQ_ERROR_MASK \
 133         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 134         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 135 #define DSI_IRQ_CHANNEL_MASK    0xf
 136
 137 /* Virtual channel interrupts */
 138 #define DSI_VC_IRQ_CS           (1 << 0)
 139 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 140 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 141 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 142 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 143 #define DSI_VC_IRQ_BTA          (1 << 5)
 144 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 145 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 147 #define DSI_VC_IRQ_ERROR_MASK \
 148         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 149         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 150         DSI_VC_IRQ_FIFO_TX_UDF)
 151
 152 /* ComplexIO interrupts */
 153 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 154 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 155 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 156 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 157 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 158 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 159 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 160 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 161 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 162 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 163 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 164 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 165 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 166 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 167 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 168 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 169 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 170 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 171 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 172 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 185 #define DSI_CIO_IRQ_ERROR_MASK \
 186         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 187          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 188          DSI_CIO_IRQ_ERRSYNCESC5 | \
 189          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 190          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 191          DSI_CIO_IRQ_ERRESC5 | \
 192          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 193          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 194          DSI_CIO_IRQ_ERRCONTROL5 | \
 195          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 196          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 200
 201 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 202
 203 static int dsi_display_init_dispc(struct platform_device *dsidev,
 204         struct omap_overlay_manager *mgr);
 205 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
 206         struct omap_overlay_manager *mgr);
 207
 208 #define DSI_MAX_NR_ISRS                2
 209 #define DSI_MAX_NR_LANES        5
 210
 211 enum dsi_lane_function {
 212         DSI_LANE_UNUSED = 0,
 213         DSI_LANE_CLK,
 214         DSI_LANE_DATA1,
 215         DSI_LANE_DATA2,
 216         DSI_LANE_DATA3,
 217         DSI_LANE_DATA4,
 218 };
 219
 220 struct dsi_lane_config {
 221         enum dsi_lane_function function;
 222         u8 polarity;
 223 };
 224
 225 struct dsi_isr_data {
 226         omap_dsi_isr_t  isr;
 227         void            *arg;
 228         u32             mask;
 229 };
 230
 231 enum fifo_size {
 232         DSI_FIFO_SIZE_0         = 0,
 233         DSI_FIFO_SIZE_32        = 1,
 234         DSI_FIFO_SIZE_64        = 2,
 235         DSI_FIFO_SIZE_96        = 3,
 236         DSI_FIFO_SIZE_128       = 4,
 237 };
 238
 239 enum dsi_vc_source {
 240         DSI_VC_SOURCE_L4 = 0,
 241         DSI_VC_SOURCE_VP,
 242 };
 243
 244 struct dsi_irq_stats {
 245         unsigned long last_reset;
 246         unsigned irq_count;
 247         unsigned dsi_irqs[32];
 248         unsigned vc_irqs[4][32];
 249         unsigned cio_irqs[32];
 250 };
 251
 252 struct dsi_isr_tables {
 253         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 254         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 255         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 256 };
 257
 258 struct dsi_data {
 259         struct platform_device *pdev;
 260         void __iomem    *base;
 261
 262         int module_id;
 263
 264         int irq;
 265
 266         struct clk *dss_clk;
 267         struct clk *sys_clk;
 268
 269         struct dispc_clock_info user_dispc_cinfo;
 270         struct dsi_clock_info user_dsi_cinfo;
 271
 272         enum omap_dss_clk_source user_dispc_fclk_src;
 273         enum omap_dss_clk_source user_lcd_clk_src;
 274         enum omap_dss_clk_source user_dsi_fclk_src;
 275
 276         struct dsi_clock_info current_cinfo;
 277
 278         bool vdds_dsi_enabled;
 279         struct regulator *vdds_dsi_reg;
 280
 281         struct {
 282                 enum dsi_vc_source source;
 283                 struct omap_dss_device *dssdev;
 284                 enum fifo_size fifo_size;
 285                 int vc_id;
 286         } vc[4];
 287
 288         struct mutex lock;
 289         struct semaphore bus_lock;
 290
 291         unsigned pll_locked;
 292
 293         spinlock_t irq_lock;
 294         struct dsi_isr_tables isr_tables;
 295         /* space for a copy used by the interrupt handler */
 296         struct dsi_isr_tables isr_tables_copy;
 297
 298         int update_channel;
 299 #ifdef DEBUG
 300         unsigned update_bytes;
 301 #endif
 302
 303         bool te_enabled;
 304         bool ulps_enabled;
 305
 306         void (*framedone_callback)(int, void *);
 307         void *framedone_data;
 308
 309         struct delayed_work framedone_timeout_work;
 310
 311 #ifdef DSI_CATCH_MISSING_TE
 312         struct timer_list te_timer;
 313 #endif
 314
 315         unsigned long cache_req_pck;
 316         unsigned long cache_clk_freq;
 317         struct dsi_clock_info cache_cinfo;
 318
 319         u32             errors;
 320         spinlock_t      errors_lock;
 321 #ifdef DEBUG
 322         ktime_t perf_setup_time;
 323         ktime_t perf_start_time;
 324 #endif
 325         int debug_read;
 326         int debug_write;
 327
 328 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 329         spinlock_t irq_stats_lock;
 330         struct dsi_irq_stats irq_stats;
 331 #endif
 332         /* DSI PLL Parameter Ranges */
 333         unsigned long regm_max, regn_max;
 334         unsigned long  regm_dispc_max, regm_dsi_max;
 335         unsigned long  fint_min, fint_max;
 336         unsigned long lpdiv_max;
 337
 338         unsigned num_lanes_supported;
 339
 340         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 341         unsigned num_lanes_used;
 342
 343         unsigned scp_clk_refcount;
 344
 345         struct dss_lcd_mgr_config mgr_config;
 346         struct omap_video_timings timings;
 347         enum omap_dss_dsi_pixel_format pix_fmt;
 348         enum omap_dss_dsi_mode mode;
 349         struct omap_dss_dsi_videomode_timings vm_timings;
 350
 351         struct omap_dss_output output;
 352 };
 353
 354 struct dsi_packet_sent_handler_data {
 355         struct platform_device *dsidev;
 356         struct completion *completion;
 357 };
 358
 359 #ifdef DEBUG
 360 static bool dsi_perf;
 361 module_param(dsi_perf, bool, 0644);
 362 #endif
 363
 364 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 365 {
 366         return dev_get_drvdata(&dsidev->dev);
 367 }
 368
 369 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 370 {
 371         return dssdev->output->pdev;
 372 }
 373
 374 struct platform_device *dsi_get_dsidev_from_id(int module)
 375 {
 376         struct omap_dss_output *out;
 377         enum omap_dss_output_id id;
 378
 379         switch (module) {
 380         case 0:
 381                 id = OMAP_DSS_OUTPUT_DSI1;
 382                 break;
 383         case 1:
 384                 id = OMAP_DSS_OUTPUT_DSI2;
 385                 break;
 386         default:
 387                 return NULL;
 388         }
 389
 390         out = omap_dss_get_output(id);
 391
 392         return out ? out->pdev : NULL;
 393 }
 394
 395 static inline void dsi_write_reg(struct platform_device *dsidev,
 396                 const struct dsi_reg idx, u32 val)
 397 {
 398         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 399
 400         __raw_writel(val, dsi->base + idx.idx);
 401 }
 402
 403 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 404                 const struct dsi_reg idx)
 405 {
 406         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 407
 408         return __raw_readl(dsi->base + idx.idx);
 409 }
 410
 411 void dsi_bus_lock(struct omap_dss_device *dssdev)
 412 {
 413         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 414         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 415
 416         down(&dsi->bus_lock);
 417 }
 418 EXPORT_SYMBOL(dsi_bus_lock);
 419
 420 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 421 {
 422         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 423         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 424
 425         up(&dsi->bus_lock);
 426 }
 427 EXPORT_SYMBOL(dsi_bus_unlock);
 428
 429 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 430 {
 431         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 432
 433         return dsi->bus_lock.count == 0;
 434 }
 435
 436 static void dsi_completion_handler(void *data, u32 mask)
 437 {
 438         complete((struct completion *)data);
 439 }
 440
 441 static inline int wait_for_bit_change(struct platform_device *dsidev,
 442                 const struct dsi_reg idx, int bitnum, int value)
 443 {
 444         unsigned long timeout;
 445         ktime_t wait;
 446         int t;
 447
 448         /* first busyloop to see if the bit changes right away */
 449         t = 100;
 450         while (t-- > 0) {
 451                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 452                         return value;
 453         }
 454
 455         /* then loop for 500ms, sleeping for 1ms in between */
 456         timeout = jiffies + msecs_to_jiffies(500);
 457         while (time_before(jiffies, timeout)) {
 458                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 459                         return value;
 460
 461                 wait = ns_to_ktime(1000 * 1000);
 462                 set_current_state(TASK_UNINTERRUPTIBLE);
 463                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 464         }
 465
 466         return !value;
 467 }
 468
 469 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 470 {
 471         switch (fmt) {
 472         case OMAP_DSS_DSI_FMT_RGB888:
 473         case OMAP_DSS_DSI_FMT_RGB666:
 474                 return 24;
 475         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 476                 return 18;
 477         case OMAP_DSS_DSI_FMT_RGB565:
 478                 return 16;
 479         default:
 480                 BUG();
 481                 return 0;
 482         }
 483 }
 484
 485 #ifdef DEBUG
 486 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 487 {
 488         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 489         dsi->perf_setup_time = ktime_get();
 490 }
 491
 492 static void dsi_perf_mark_start(struct platform_device *dsidev)
 493 {
 494         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 495         dsi->perf_start_time = ktime_get();
 496 }
 497
 498 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 499 {
 500         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 501         ktime_t t, setup_time, trans_time;
 502         u32 total_bytes;
 503         u32 setup_us, trans_us, total_us;
 504
 505         if (!dsi_perf)
 506                 return;
 507
 508         t = ktime_get();
 509
 510         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 511         setup_us = (u32)ktime_to_us(setup_time);
 512         if (setup_us == 0)
 513                 setup_us = 1;
 514
 515         trans_time = ktime_sub(t, dsi->perf_start_time);
 516         trans_us = (u32)ktime_to_us(trans_time);
 517         if (trans_us == 0)
 518                 trans_us = 1;
 519
 520         total_us = setup_us + trans_us;
 521
 522         total_bytes = dsi->update_bytes;
 523
 524         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 525                         "%u bytes, %u kbytes/sec\n",
 526                         name,
 527                         setup_us,
 528                         trans_us,
 529                         total_us,
 530                         1000*1000 / total_us,
 531                         total_bytes,
 532                         total_bytes * 1000 / total_us);
 533 }
 534 #else
 535 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 536 {
 537 }
 538
 539 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 540 {
 541 }
 542
 543 static inline void dsi_perf_show(struct platform_device *dsidev,
 544                 const char *name)
 545 {
 546 }
 547 #endif
 548
 549 static int verbose_irq;
 550
 551 static void print_irq_status(u32 status)
 552 {
 553         if (status == 0)
 554                 return;
 555
 556         if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 557                 return;
 558
 559 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
 560
 561         pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 562                 status,
 563                 verbose_irq ? PIS(VC0) : "",
 564                 verbose_irq ? PIS(VC1) : "",
 565                 verbose_irq ? PIS(VC2) : "",
 566                 verbose_irq ? PIS(VC3) : "",
 567                 PIS(WAKEUP),
 568                 PIS(RESYNC),
 569                 PIS(PLL_LOCK),
 570                 PIS(PLL_UNLOCK),
 571                 PIS(PLL_RECALL),
 572                 PIS(COMPLEXIO_ERR),
 573                 PIS(HS_TX_TIMEOUT),
 574                 PIS(LP_RX_TIMEOUT),
 575                 PIS(TE_TRIGGER),
 576                 PIS(ACK_TRIGGER),
 577                 PIS(SYNC_LOST),
 578                 PIS(LDO_POWER_GOOD),
 579                 PIS(TA_TIMEOUT));
 580 #undef PIS
 581 }
 582
 583 static void print_irq_status_vc(int channel, u32 status)
 584 {
 585         if (status == 0)
 586                 return;
 587
 588         if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 589                 return;
 590
 591 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
 592
 593         pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
 594                 channel,
 595                 status,
 596                 PIS(CS),
 597                 PIS(ECC_CORR),
 598                 PIS(ECC_NO_CORR),
 599                 verbose_irq ? PIS(PACKET_SENT) : "",
 600                 PIS(BTA),
 601                 PIS(FIFO_TX_OVF),
 602                 PIS(FIFO_RX_OVF),
 603                 PIS(FIFO_TX_UDF),
 604                 PIS(PP_BUSY_CHANGE));
 605 #undef PIS
 606 }
 607
 608 static void print_irq_status_cio(u32 status)
 609 {
 610         if (status == 0)
 611                 return;
 612
 613 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
 614
 615         pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
 616                 status,
 617                 PIS(ERRSYNCESC1),
 618                 PIS(ERRSYNCESC2),
 619                 PIS(ERRSYNCESC3),
 620                 PIS(ERRESC1),
 621                 PIS(ERRESC2),
 622                 PIS(ERRESC3),
 623                 PIS(ERRCONTROL1),
 624                 PIS(ERRCONTROL2),
 625                 PIS(ERRCONTROL3),
 626                 PIS(STATEULPS1),
 627                 PIS(STATEULPS2),
 628                 PIS(STATEULPS3),
 629                 PIS(ERRCONTENTIONLP0_1),
 630                 PIS(ERRCONTENTIONLP1_1),
 631                 PIS(ERRCONTENTIONLP0_2),
 632                 PIS(ERRCONTENTIONLP1_2),
 633                 PIS(ERRCONTENTIONLP0_3),
 634                 PIS(ERRCONTENTIONLP1_3),
 635                 PIS(ULPSACTIVENOT_ALL0),
 636                 PIS(ULPSACTIVENOT_ALL1));
 637 #undef PIS
 638 }
 639
 640 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 641 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 642                 u32 *vcstatus, u32 ciostatus)
 643 {
 644         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 645         int i;
 646
 647         spin_lock(&dsi->irq_stats_lock);
 648
 649         dsi->irq_stats.irq_count++;
 650         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 651
 652         for (i = 0; i < 4; ++i)
 653                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 654
 655         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 656
 657         spin_unlock(&dsi->irq_stats_lock);
 658 }
 659 #else
 660 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 661 #endif
 662
 663 static int debug_irq;
 664
 665 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 666                 u32 *vcstatus, u32 ciostatus)
 667 {
 668         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 669         int i;
 670
 671         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 672                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 673                 print_irq_status(irqstatus);
 674                 spin_lock(&dsi->errors_lock);
 675                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 676                 spin_unlock(&dsi->errors_lock);
 677         } else if (debug_irq) {
 678                 print_irq_status(irqstatus);
 679         }
 680
 681         for (i = 0; i < 4; ++i) {
 682                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 683                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 684                                        i, vcstatus[i]);
 685                         print_irq_status_vc(i, vcstatus[i]);
 686                 } else if (debug_irq) {
 687                         print_irq_status_vc(i, vcstatus[i]);
 688                 }
 689         }
 690
 691         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 692                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 693                 print_irq_status_cio(ciostatus);
 694         } else if (debug_irq) {
 695                 print_irq_status_cio(ciostatus);
 696         }
 697 }
 698
 699 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 700                 unsigned isr_array_size, u32 irqstatus)
 701 {
 702         struct dsi_isr_data *isr_data;
 703         int i;
 704
 705         for (i = 0; i < isr_array_size; i++) {
 706                 isr_data = &isr_array[i];
 707                 if (isr_data->isr && isr_data->mask & irqstatus)
 708                         isr_data->isr(isr_data->arg, irqstatus);
 709         }
 710 }
 711
 712 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 713                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 714 {
 715         int i;
 716
 717         dsi_call_isrs(isr_tables->isr_table,
 718                         ARRAY_SIZE(isr_tables->isr_table),
 719                         irqstatus);
 720
 721         for (i = 0; i < 4; ++i) {
 722                 if (vcstatus[i] == 0)
 723                         continue;
 724                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 725                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 726                                 vcstatus[i]);
 727         }
 728
 729         if (ciostatus != 0)
 730                 dsi_call_isrs(isr_tables->isr_table_cio,
 731                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 732                                 ciostatus);
 733 }
 734
 735 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 736 {
 737         struct platform_device *dsidev;
 738         struct dsi_data *dsi;
 739         u32 irqstatus, vcstatus[4], ciostatus;
 740         int i;
 741
 742         dsidev = (struct platform_device *) arg;
 743         dsi = dsi_get_dsidrv_data(dsidev);
 744
 745         spin_lock(&dsi->irq_lock);
 746
 747         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 748
 749         /* IRQ is not for us */
 750         if (!irqstatus) {
 751                 spin_unlock(&dsi->irq_lock);
 752                 return IRQ_NONE;
 753         }
 754
 755         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 756         /* flush posted write */
 757         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 758
 759         for (i = 0; i < 4; ++i) {
 760                 if ((irqstatus & (1 << i)) == 0) {
 761                         vcstatus[i] = 0;
 762                         continue;
 763                 }
 764
 765                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 766
 767                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 768                 /* flush posted write */
 769                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 770         }
 771
 772         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 773                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 774
 775                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 776                 /* flush posted write */
 777                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 778         } else {
 779                 ciostatus = 0;
 780         }
 781
 782 #ifdef DSI_CATCH_MISSING_TE
 783         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 784                 del_timer(&dsi->te_timer);
 785 #endif
 786
 787         /* make a copy and unlock, so that isrs can unregister
 788          * themselves */
 789         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 790                 sizeof(dsi->isr_tables));
 791
 792         spin_unlock(&dsi->irq_lock);
 793
 794         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 795
 796         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 797
 798         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 799
 800         return IRQ_HANDLED;
 801 }
 802
 803 /* dsi->irq_lock has to be locked by the caller */
 804 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 805                 struct dsi_isr_data *isr_array,
 806                 unsigned isr_array_size, u32 default_mask,
 807                 const struct dsi_reg enable_reg,
 808                 const struct dsi_reg status_reg)
 809 {
 810         struct dsi_isr_data *isr_data;
 811         u32 mask;
 812         u32 old_mask;
 813         int i;
 814
 815         mask = default_mask;
 816
 817         for (i = 0; i < isr_array_size; i++) {
 818                 isr_data = &isr_array[i];
 819
 820                 if (isr_data->isr == NULL)
 821                         continue;
 822
 823                 mask |= isr_data->mask;
 824         }
 825
 826         old_mask = dsi_read_reg(dsidev, enable_reg);
 827         /* clear the irqstatus for newly enabled irqs */
 828         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 829         dsi_write_reg(dsidev, enable_reg, mask);
 830
 831         /* flush posted writes */
 832         dsi_read_reg(dsidev, enable_reg);
 833         dsi_read_reg(dsidev, status_reg);
 834 }
 835
 836 /* dsi->irq_lock has to be locked by the caller */
 837 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 838 {
 839         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 840         u32 mask = DSI_IRQ_ERROR_MASK;
 841 #ifdef DSI_CATCH_MISSING_TE
 842         mask |= DSI_IRQ_TE_TRIGGER;
 843 #endif
 844         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 845                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 846                         DSI_IRQENABLE, DSI_IRQSTATUS);
 847 }
 848
 849 /* dsi->irq_lock has to be locked by the caller */
 850 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 851 {
 852         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 853
 854         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 855                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 856                         DSI_VC_IRQ_ERROR_MASK,
 857                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 858 }
 859
 860 /* dsi->irq_lock has to be locked by the caller */
 861 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 862 {
 863         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 864
 865         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 866                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 867                         DSI_CIO_IRQ_ERROR_MASK,
 868                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 869 }
 870
 871 static void _dsi_initialize_irq(struct platform_device *dsidev)
 872 {
 873         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 874         unsigned long flags;
 875         int vc;
 876
 877         spin_lock_irqsave(&dsi->irq_lock, flags);
 878
 879         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 880
 881         _omap_dsi_set_irqs(dsidev);
 882         for (vc = 0; vc < 4; ++vc)
 883                 _omap_dsi_set_irqs_vc(dsidev, vc);
 884         _omap_dsi_set_irqs_cio(dsidev);
 885
 886         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 887 }
 888
 889 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 890                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 891 {
 892         struct dsi_isr_data *isr_data;
 893         int free_idx;
 894         int i;
 895
 896         BUG_ON(isr == NULL);
 897
 898         /* check for duplicate entry and find a free slot */
 899         free_idx = -1;
 900         for (i = 0; i < isr_array_size; i++) {
 901                 isr_data = &isr_array[i];
 902
 903                 if (isr_data->isr == isr && isr_data->arg == arg &&
 904                                 isr_data->mask == mask) {
 905                         return -EINVAL;
 906                 }
 907
 908                 if (isr_data->isr == NULL && free_idx == -1)
 909                         free_idx = i;
 910         }
 911
 912         if (free_idx == -1)
 913                 return -EBUSY;
 914
 915         isr_data = &isr_array[free_idx];
 916         isr_data->isr = isr;
 917         isr_data->arg = arg;
 918         isr_data->mask = mask;
 919
 920         return 0;
 921 }
 922
 923 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 924                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 925 {
 926         struct dsi_isr_data *isr_data;
 927         int i;
 928
 929         for (i = 0; i < isr_array_size; i++) {
 930                 isr_data = &isr_array[i];
 931                 if (isr_data->isr != isr || isr_data->arg != arg ||
 932                                 isr_data->mask != mask)
 933                         continue;
 934
 935                 isr_data->isr = NULL;
 936                 isr_data->arg = NULL;
 937                 isr_data->mask = 0;
 938
 939                 return 0;
 940         }
 941
 942         return -EINVAL;
 943 }
 944
 945 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 946                 void *arg, u32 mask)
 947 {
 948         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 949         unsigned long flags;
 950         int r;
 951
 952         spin_lock_irqsave(&dsi->irq_lock, flags);
 953
 954         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 955                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 956
 957         if (r == 0)
 958                 _omap_dsi_set_irqs(dsidev);
 959
 960         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 961
 962         return r;
 963 }
 964
 965 static int dsi_unregister_isr(struct platform_device *dsidev,
 966                 omap_dsi_isr_t isr, void *arg, u32 mask)
 967 {
 968         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 969         unsigned long flags;
 970         int r;
 971
 972         spin_lock_irqsave(&dsi->irq_lock, flags);
 973
 974         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 975                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 976
 977         if (r == 0)
 978                 _omap_dsi_set_irqs(dsidev);
 979
 980         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 981
 982         return r;
 983 }
 984
 985 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 986                 omap_dsi_isr_t isr, void *arg, u32 mask)
 987 {
 988         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 989         unsigned long flags;
 990         int r;
 991
 992         spin_lock_irqsave(&dsi->irq_lock, flags);
 993
 994         r = _dsi_register_isr(isr, arg, mask,
 995                         dsi->isr_tables.isr_table_vc[channel],
 996                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 997
 998         if (r == 0)
 999                 _omap_dsi_set_irqs_vc(dsidev, channel);
1000
1001         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1002
1003         return r;
1004 }
1005
1006 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1007                 omap_dsi_isr_t isr, void *arg, u32 mask)
1008 {
1009         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1010         unsigned long flags;
1011         int r;
1012
1013         spin_lock_irqsave(&dsi->irq_lock, flags);
1014
1015         r = _dsi_unregister_isr(isr, arg, mask,
1016                         dsi->isr_tables.isr_table_vc[channel],
1017                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1018
1019         if (r == 0)
1020                 _omap_dsi_set_irqs_vc(dsidev, channel);
1021
1022         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1023
1024         return r;
1025 }
1026
1027 static int dsi_register_isr_cio(struct platform_device *dsidev,
1028                 omap_dsi_isr_t isr, void *arg, u32 mask)
1029 {
1030         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1031         unsigned long flags;
1032         int r;
1033
1034         spin_lock_irqsave(&dsi->irq_lock, flags);
1035
1036         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1037                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1038
1039         if (r == 0)
1040                 _omap_dsi_set_irqs_cio(dsidev);
1041
1042         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1043
1044         return r;
1045 }
1046
1047 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1048                 omap_dsi_isr_t isr, void *arg, u32 mask)
1049 {
1050         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1051         unsigned long flags;
1052         int r;
1053
1054         spin_lock_irqsave(&dsi->irq_lock, flags);
1055
1056         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1057                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1058
1059         if (r == 0)
1060                 _omap_dsi_set_irqs_cio(dsidev);
1061
1062         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1063
1064         return r;
1065 }
1066
1067 static u32 dsi_get_errors(struct platform_device *dsidev)
1068 {
1069         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1070         unsigned long flags;
1071         u32 e;
1072         spin_lock_irqsave(&dsi->errors_lock, flags);
1073         e = dsi->errors;
1074         dsi->errors = 0;
1075         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1076         return e;
1077 }
1078
1079 int dsi_runtime_get(struct platform_device *dsidev)
1080 {
1081         int r;
1082         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1083
1084         DSSDBG("dsi_runtime_get\n");
1085
1086         r = pm_runtime_get_sync(&dsi->pdev->dev);
1087         WARN_ON(r < 0);
1088         return r < 0 ? r : 0;
1089 }
1090
1091 void dsi_runtime_put(struct platform_device *dsidev)
1092 {
1093         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1094         int r;
1095
1096         DSSDBG("dsi_runtime_put\n");
1097
1098         r = pm_runtime_put_sync(&dsi->pdev->dev);
1099         WARN_ON(r < 0 && r != -ENOSYS);
1100 }
1101
1102 /* source clock for DSI PLL. this could also be PCLKFREE */
1103 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1104                 bool enable)
1105 {
1106         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1107
1108         if (enable)
1109                 clk_prepare_enable(dsi->sys_clk);
1110         else
1111                 clk_disable_unprepare(dsi->sys_clk);
1112
1113         if (enable && dsi->pll_locked) {
1114                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1115                         DSSERR("cannot lock PLL when enabling clocks\n");
1116         }
1117 }
1118
1119 static void _dsi_print_reset_status(struct platform_device *dsidev)
1120 {
1121         u32 l;
1122         int b0, b1, b2;
1123
1124         /* A dummy read using the SCP interface to any DSIPHY register is
1125          * required after DSIPHY reset to complete the reset of the DSI complex
1126          * I/O. */
1127         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1128
1129         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1130                 b0 = 28;
1131                 b1 = 27;
1132                 b2 = 26;
1133         } else {
1134                 b0 = 24;
1135                 b1 = 25;
1136                 b2 = 26;
1137         }
1138
1139 #define DSI_FLD_GET(fld, start, end)\
1140         FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1141
1142         pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1143                 DSI_FLD_GET(PLL_STATUS, 0, 0),
1144                 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1145                 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1146                 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1147                 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1148                 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1149                 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1150                 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1151
1152 #undef DSI_FLD_GET
1153 }
1154
1155 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1156 {
1157         DSSDBG("dsi_if_enable(%d)\n", enable);
1158
1159         enable = enable ? 1 : 0;
1160         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1161
1162         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1163                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1164                         return -EIO;
1165         }
1166
1167         return 0;
1168 }
1169
1170 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1171 {
1172         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1173
1174         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1175 }
1176
1177 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1178 {
1179         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1182 }
1183
1184 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1185 {
1186         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1187
1188         return dsi->current_cinfo.clkin4ddr / 16;
1189 }
1190
1191 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1192 {
1193         unsigned long r;
1194         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1195
1196         if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1197                 /* DSI FCLK source is DSS_CLK_FCK */
1198                 r = clk_get_rate(dsi->dss_clk);
1199         } else {
1200                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1201                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1202         }
1203
1204         return r;
1205 }
1206
1207 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1208 {
1209         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1210         unsigned long dsi_fclk;
1211         unsigned lp_clk_div;
1212         unsigned long lp_clk;
1213
1214         lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1215
1216         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1217                 return -EINVAL;
1218
1219         dsi_fclk = dsi_fclk_rate(dsidev);
1220
1221         lp_clk = dsi_fclk / 2 / lp_clk_div;
1222
1223         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1224         dsi->current_cinfo.lp_clk = lp_clk;
1225         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1226
1227         /* LP_CLK_DIVISOR */
1228         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1229
1230         /* LP_RX_SYNCHRO_ENABLE */
1231         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1232
1233         return 0;
1234 }
1235
1236 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1237 {
1238         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1239
1240         if (dsi->scp_clk_refcount++ == 0)
1241                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1242 }
1243
1244 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1245 {
1246         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1247
1248         WARN_ON(dsi->scp_clk_refcount == 0);
1249         if (--dsi->scp_clk_refcount == 0)
1250                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1251 }
1252
1253 enum dsi_pll_power_state {
1254         DSI_PLL_POWER_OFF       = 0x0,
1255         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1256         DSI_PLL_POWER_ON_ALL    = 0x2,
1257         DSI_PLL_POWER_ON_DIV    = 0x3,
1258 };
1259
1260 static int dsi_pll_power(struct platform_device *dsidev,
1261                 enum dsi_pll_power_state state)
1262 {
1263         int t = 0;
1264
1265         /* DSI-PLL power command 0x3 is not working */
1266         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1267                         state == DSI_PLL_POWER_ON_DIV)
1268                 state = DSI_PLL_POWER_ON_ALL;
1269
1270         /* PLL_PWR_CMD */
1271         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1272
1273         /* PLL_PWR_STATUS */
1274         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1275                 if (++t > 1000) {
1276                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1277                                         state);
1278                         return -ENODEV;
1279                 }
1280                 udelay(1);
1281         }
1282
1283         return 0;
1284 }
1285
1286 /* calculate clock rates using dividers in cinfo */
1287 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1288                 struct dsi_clock_info *cinfo)
1289 {
1290         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1291
1292         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1293                 return -EINVAL;
1294
1295         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1296                 return -EINVAL;
1297
1298         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1299                 return -EINVAL;
1300
1301         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1302                 return -EINVAL;
1303
1304         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1305         cinfo->fint = cinfo->clkin / cinfo->regn;
1306
1307         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1308                 return -EINVAL;
1309
1310         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1311
1312         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1313                 return -EINVAL;
1314
1315         if (cinfo->regm_dispc > 0)
1316                 cinfo->dsi_pll_hsdiv_dispc_clk =
1317                         cinfo->clkin4ddr / cinfo->regm_dispc;
1318         else
1319                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1320
1321         if (cinfo->regm_dsi > 0)
1322                 cinfo->dsi_pll_hsdiv_dsi_clk =
1323                         cinfo->clkin4ddr / cinfo->regm_dsi;
1324         else
1325                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1326
1327         return 0;
1328 }
1329
1330 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1331                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1332                 struct dispc_clock_info *dispc_cinfo)
1333 {
1334         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1335         struct dsi_clock_info cur, best;
1336         struct dispc_clock_info best_dispc;
1337         int min_fck_per_pck;
1338         int match = 0;
1339         unsigned long dss_sys_clk, max_dss_fck;
1340
1341         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1342
1343         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1344
1345         if (req_pck == dsi->cache_req_pck &&
1346                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1347                 DSSDBG("DSI clock info found from cache\n");
1348                 *dsi_cinfo = dsi->cache_cinfo;
1349                 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1350                         dispc_cinfo);
1351                 return 0;
1352         }
1353
1354         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1355
1356         if (min_fck_per_pck &&
1357                 req_pck * min_fck_per_pck > max_dss_fck) {
1358                 DSSERR("Requested pixel clock not possible with the current "
1359                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1360                                 "the constraint off.\n");
1361                 min_fck_per_pck = 0;
1362         }
1363
1364         DSSDBG("dsi_pll_calc\n");
1365
1366 retry:
1367         memset(&best, 0, sizeof(best));
1368         memset(&best_dispc, 0, sizeof(best_dispc));
1369
1370         memset(&cur, 0, sizeof(cur));
1371         cur.clkin = dss_sys_clk;
1372
1373         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1374         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1375         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1376                 cur.fint = cur.clkin / cur.regn;
1377
1378                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1379                         continue;
1380
1381                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1382                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1383                         unsigned long a, b;
1384
1385                         a = 2 * cur.regm * (cur.clkin/1000);
1386                         b = cur.regn;
1387                         cur.clkin4ddr = a / b * 1000;
1388
1389                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1390                                 break;
1391
1392                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1393                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1394                         for (cur.regm_dispc = 1; cur.regm_dispc <
1395                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1396                                 struct dispc_clock_info cur_dispc;
1397                                 cur.dsi_pll_hsdiv_dispc_clk =
1398                                         cur.clkin4ddr / cur.regm_dispc;
1399
1400                                 if (cur.regm_dispc > 1 &&
1401                                                 cur.regm_dispc % 2 != 0 &&
1402                                                 req_pck >= 1000000)
1403                                         continue;
1404
1405                                 /* this will narrow down the search a bit,
1406                                  * but still give pixclocks below what was
1407                                  * requested */
1408                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1409                                         break;
1410
1411                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1412                                         continue;
1413
1414                                 if (min_fck_per_pck &&
1415                                         cur.dsi_pll_hsdiv_dispc_clk <
1416                                                 req_pck * min_fck_per_pck)
1417                                         continue;
1418
1419                                 match = 1;
1420
1421                                 dispc_find_clk_divs(req_pck,
1422                                                 cur.dsi_pll_hsdiv_dispc_clk,
1423                                                 &cur_dispc);
1424
1425                                 if (abs(cur_dispc.pck - req_pck) <
1426                                                 abs(best_dispc.pck - req_pck)) {
1427                                         best = cur;
1428                                         best_dispc = cur_dispc;
1429
1430                                         if (cur_dispc.pck == req_pck)
1431                                                 goto found;
1432                                 }
1433                         }
1434                 }
1435         }
1436 found:
1437         if (!match) {
1438                 if (min_fck_per_pck) {
1439                         DSSERR("Could not find suitable clock settings.\n"
1440                                         "Turning FCK/PCK constraint off and"
1441                                         "trying again.\n");
1442                         min_fck_per_pck = 0;
1443                         goto retry;
1444                 }
1445
1446                 DSSERR("Could not find suitable clock settings.\n");
1447
1448                 return -EINVAL;
1449         }
1450
1451         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1452         best.regm_dsi = 0;
1453         best.dsi_pll_hsdiv_dsi_clk = 0;
1454
1455         if (dsi_cinfo)
1456                 *dsi_cinfo = best;
1457         if (dispc_cinfo)
1458                 *dispc_cinfo = best_dispc;
1459
1460         dsi->cache_req_pck = req_pck;
1461         dsi->cache_clk_freq = 0;
1462         dsi->cache_cinfo = best;
1463
1464         return 0;
1465 }
1466
1467 static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
1468                 unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
1469 {
1470         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1471         struct dsi_clock_info cur, best;
1472
1473         DSSDBG("dsi_pll_calc_ddrfreq\n");
1474
1475         memset(&best, 0, sizeof(best));
1476         memset(&cur, 0, sizeof(cur));
1477
1478         cur.clkin = clk_get_rate(dsi->sys_clk);
1479
1480         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1481                 cur.fint = cur.clkin / cur.regn;
1482
1483                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1484                         continue;
1485
1486                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1487                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1488                         unsigned long a, b;
1489
1490                         a = 2 * cur.regm * (cur.clkin/1000);
1491                         b = cur.regn;
1492                         cur.clkin4ddr = a / b * 1000;
1493
1494                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1495                                 break;
1496
1497                         if (abs(cur.clkin4ddr - req_clkin4ddr) <
1498                                         abs(best.clkin4ddr - req_clkin4ddr)) {
1499                                 best = cur;
1500                                 DSSDBG("best %ld\n", best.clkin4ddr);
1501                         }
1502
1503                         if (cur.clkin4ddr == req_clkin4ddr)
1504                                 goto found;
1505                 }
1506         }
1507 found:
1508         if (cinfo)
1509                 *cinfo = best;
1510
1511         return 0;
1512 }
1513
1514 static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
1515                 struct dsi_clock_info *cinfo)
1516 {
1517         unsigned long max_dsi_fck;
1518
1519         max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1520
1521         cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1522         cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1523 }
1524
1525 static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
1526                 unsigned long req_pck, struct dsi_clock_info *cinfo,
1527                 struct dispc_clock_info *dispc_cinfo)
1528 {
1529         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1530         unsigned regm_dispc, best_regm_dispc;
1531         unsigned long dispc_clk, best_dispc_clk;
1532         int min_fck_per_pck;
1533         unsigned long max_dss_fck;
1534         struct dispc_clock_info best_dispc;
1535         bool match;
1536
1537         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1538
1539         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1540
1541         if (min_fck_per_pck &&
1542                         req_pck * min_fck_per_pck > max_dss_fck) {
1543                 DSSERR("Requested pixel clock not possible with the current "
1544                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1545                                 "the constraint off.\n");
1546                 min_fck_per_pck = 0;
1547         }
1548
1549 retry:
1550         best_regm_dispc = 0;
1551         best_dispc_clk = 0;
1552         memset(&best_dispc, 0, sizeof(best_dispc));
1553         match = false;
1554
1555         for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
1556                 struct dispc_clock_info cur_dispc;
1557
1558                 dispc_clk = cinfo->clkin4ddr / regm_dispc;
1559
1560                 /* this will narrow down the search a bit,
1561                  * but still give pixclocks below what was
1562                  * requested */
1563                 if (dispc_clk  < req_pck)
1564                         break;
1565
1566                 if (dispc_clk > max_dss_fck)
1567                         continue;
1568
1569                 if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
1570                         continue;
1571
1572                 match = true;
1573
1574                 dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
1575
1576                 if (abs(cur_dispc.pck - req_pck) <
1577                                 abs(best_dispc.pck - req_pck)) {
1578                         best_regm_dispc = regm_dispc;
1579                         best_dispc_clk = dispc_clk;
1580                         best_dispc = cur_dispc;
1581
1582                         if (cur_dispc.pck == req_pck)
1583                                 goto found;
1584                 }
1585         }
1586
1587         if (!match) {
1588                 if (min_fck_per_pck) {
1589                         DSSERR("Could not find suitable clock settings.\n"
1590                                         "Turning FCK/PCK constraint off and"
1591                                         "trying again.\n");
1592                         min_fck_per_pck = 0;
1593                         goto retry;
1594                 }
1595
1596                 DSSERR("Could not find suitable clock settings.\n");
1597
1598                 return -EINVAL;
1599         }
1600 found:
1601         cinfo->regm_dispc = best_regm_dispc;
1602         cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
1603
1604         *dispc_cinfo = best_dispc;
1605
1606         return 0;
1607 }
1608
1609 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1610                 struct dsi_clock_info *cinfo)
1611 {
1612         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1613         int r = 0;
1614         u32 l;
1615         int f = 0;
1616         u8 regn_start, regn_end, regm_start, regm_end;
1617         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1618
1619         DSSDBG("DSI PLL clock config starts");
1620
1621         dsi->current_cinfo.clkin = cinfo->clkin;
1622         dsi->current_cinfo.fint = cinfo->fint;
1623         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1624         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1625                         cinfo->dsi_pll_hsdiv_dispc_clk;
1626         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1627                         cinfo->dsi_pll_hsdiv_dsi_clk;
1628
1629         dsi->current_cinfo.regn = cinfo->regn;
1630         dsi->current_cinfo.regm = cinfo->regm;
1631         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1632         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1633
1634         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1635
1636         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1637
1638         /* DSIPHY == CLKIN4DDR */
1639         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1640                         cinfo->regm,
1641                         cinfo->regn,
1642                         cinfo->clkin,
1643                         cinfo->clkin4ddr);
1644
1645         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1646                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1647
1648         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1649
1650         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1651                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1652                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1653                 cinfo->dsi_pll_hsdiv_dispc_clk);
1654         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1655                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1656                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1657                 cinfo->dsi_pll_hsdiv_dsi_clk);
1658
1659         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1660         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1661         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1662                         &regm_dispc_end);
1663         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1664                         &regm_dsi_end);
1665
1666         /* DSI_PLL_AUTOMODE = manual */
1667         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1668
1669         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1670         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1671         /* DSI_PLL_REGN */
1672         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1673         /* DSI_PLL_REGM */
1674         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1675         /* DSI_CLOCK_DIV */
1676         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1677                         regm_dispc_start, regm_dispc_end);
1678         /* DSIPROTO_CLOCK_DIV */
1679         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1680                         regm_dsi_start, regm_dsi_end);
1681         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1682
1683         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1684
1685         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1686
1687         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1688                 f = cinfo->fint < 1000000 ? 0x3 :
1689                         cinfo->fint < 1250000 ? 0x4 :
1690                         cinfo->fint < 1500000 ? 0x5 :
1691                         cinfo->fint < 1750000 ? 0x6 :
1692                         0x7;
1693
1694                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1695         } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1696                 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1697
1698                 l = FLD_MOD(l, f, 4, 1);        /* PLL_SELFREQDCO */
1699         }
1700
1701         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1702         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1703         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1704         if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1705                 l = FLD_MOD(l, 3, 22, 21);      /* REF_SYSCLK = sysclk */
1706         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1707
1708         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1709
1710         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1711                 DSSERR("dsi pll go bit not going down.\n");
1712                 r = -EIO;
1713                 goto err;
1714         }
1715
1716         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1717                 DSSERR("cannot lock PLL\n");
1718                 r = -EIO;
1719                 goto err;
1720         }
1721
1722         dsi->pll_locked = 1;
1723
1724         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1725         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1726         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1727         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1728         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1729         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1730         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1731         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1732         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1733         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1734         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1735         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1736         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1737         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1738         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1739         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1740
1741         DSSDBG("PLL config done\n");
1742 err:
1743         return r;
1744 }
1745
1746 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1747                 bool enable_hsdiv)
1748 {
1749         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1750         int r = 0;
1751         enum dsi_pll_power_state pwstate;
1752
1753         DSSDBG("PLL init\n");
1754
1755         /*
1756          * It seems that on many OMAPs we need to enable both to have a
1757          * functional HSDivider.
1758          */
1759         enable_hsclk = enable_hsdiv = true;
1760
1761         if (dsi->vdds_dsi_reg == NULL) {
1762                 struct regulator *vdds_dsi;
1763
1764                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1765
1766                 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1767                 if (IS_ERR(vdds_dsi))
1768                         vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
1769
1770                 if (IS_ERR(vdds_dsi)) {
1771                         DSSERR("can't get VDDS_DSI regulator\n");
1772                         return PTR_ERR(vdds_dsi);
1773                 }
1774
1775                 dsi->vdds_dsi_reg = vdds_dsi;
1776         }
1777
1778         dsi_enable_pll_clock(dsidev, 1);
1779         /*
1780          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1781          */
1782         dsi_enable_scp_clk(dsidev);
1783
1784         if (!dsi->vdds_dsi_enabled) {
1785                 r = regulator_enable(dsi->vdds_dsi_reg);
1786                 if (r)
1787                         goto err0;
1788                 dsi->vdds_dsi_enabled = true;
1789         }
1790
1791         /* XXX PLL does not come out of reset without this... */
1792         dispc_pck_free_enable(1);
1793
1794         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1795                 DSSERR("PLL not coming out of reset.\n");
1796                 r = -ENODEV;
1797                 dispc_pck_free_enable(0);
1798                 goto err1;
1799         }
1800
1801         /* XXX ... but if left on, we get problems when planes do not
1802          * fill the whole display. No idea about this */
1803         dispc_pck_free_enable(0);
1804
1805         if (enable_hsclk && enable_hsdiv)
1806                 pwstate = DSI_PLL_POWER_ON_ALL;
1807         else if (enable_hsclk)
1808                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1809         else if (enable_hsdiv)
1810                 pwstate = DSI_PLL_POWER_ON_DIV;
1811         else
1812                 pwstate = DSI_PLL_POWER_OFF;
1813
1814         r = dsi_pll_power(dsidev, pwstate);
1815
1816         if (r)
1817                 goto err1;
1818
1819         DSSDBG("PLL init done\n");
1820
1821         return 0;
1822 err1:
1823         if (dsi->vdds_dsi_enabled) {
1824                 regulator_disable(dsi->vdds_dsi_reg);
1825                 dsi->vdds_dsi_enabled = false;
1826         }
1827 err0:
1828         dsi_disable_scp_clk(dsidev);
1829         dsi_enable_pll_clock(dsidev, 0);
1830         return r;
1831 }
1832
1833 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1834 {
1835         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1836
1837         dsi->pll_locked = 0;
1838         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1839         if (disconnect_lanes) {
1840                 WARN_ON(!dsi->vdds_dsi_enabled);
1841                 regulator_disable(dsi->vdds_dsi_reg);
1842                 dsi->vdds_dsi_enabled = false;
1843         }
1844
1845         dsi_disable_scp_clk(dsidev);
1846         dsi_enable_pll_clock(dsidev, 0);
1847
1848         DSSDBG("PLL uninit done\n");
1849 }
1850
1851 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1852                 struct seq_file *s)
1853 {
1854         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1855         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1856         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1857         int dsi_module = dsi->module_id;
1858
1859         dispc_clk_src = dss_get_dispc_clk_source();
1860         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1861
1862         if (dsi_runtime_get(dsidev))
1863                 return;
1864
1865         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1866
1867         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1868
1869         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1870
1871         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1872                         cinfo->clkin4ddr, cinfo->regm);
1873
1874         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1875                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1876                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1877                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1878                         cinfo->dsi_pll_hsdiv_dispc_clk,
1879                         cinfo->regm_dispc,
1880                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1881                         "off" : "on");
1882
1883         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1884                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1885                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1886                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1887                         cinfo->dsi_pll_hsdiv_dsi_clk,
1888                         cinfo->regm_dsi,
1889                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1890                         "off" : "on");
1891
1892         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1893
1894         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1895                         dss_get_generic_clk_source_name(dsi_clk_src),
1896                         dss_feat_get_clk_source_name(dsi_clk_src));
1897
1898         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1899
1900         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1901                         cinfo->clkin4ddr / 4);
1902
1903         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1904
1905         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1906
1907         dsi_runtime_put(dsidev);
1908 }
1909
1910 void dsi_dump_clocks(struct seq_file *s)
1911 {
1912         struct platform_device *dsidev;
1913         int i;
1914
1915         for  (i = 0; i < MAX_NUM_DSI; i++) {
1916                 dsidev = dsi_get_dsidev_from_id(i);
1917                 if (dsidev)
1918                         dsi_dump_dsidev_clocks(dsidev, s);
1919         }
1920 }
1921
1922 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1923 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1924                 struct seq_file *s)
1925 {
1926         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1927         unsigned long flags;
1928         struct dsi_irq_stats stats;
1929
1930         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1931
1932         stats = dsi->irq_stats;
1933         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1934         dsi->irq_stats.last_reset = jiffies;
1935
1936         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1937
1938         seq_printf(s, "period %u ms\n",
1939                         jiffies_to_msecs(jiffies - stats.last_reset));
1940
1941         seq_printf(s, "irqs %d\n", stats.irq_count);
1942 #define PIS(x) \
1943         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1944
1945         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1946         PIS(VC0);
1947         PIS(VC1);
1948         PIS(VC2);
1949         PIS(VC3);
1950         PIS(WAKEUP);
1951         PIS(RESYNC);
1952         PIS(PLL_LOCK);
1953         PIS(PLL_UNLOCK);
1954         PIS(PLL_RECALL);
1955         PIS(COMPLEXIO_ERR);
1956         PIS(HS_TX_TIMEOUT);
1957         PIS(LP_RX_TIMEOUT);
1958         PIS(TE_TRIGGER);
1959         PIS(ACK_TRIGGER);
1960         PIS(SYNC_LOST);
1961         PIS(LDO_POWER_GOOD);
1962         PIS(TA_TIMEOUT);
1963 #undef PIS
1964
1965 #define PIS(x) \
1966         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1967                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1968                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1969                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1970                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1971
1972         seq_printf(s, "-- VC interrupts --\n");
1973         PIS(CS);
1974         PIS(ECC_CORR);
1975         PIS(PACKET_SENT);
1976         PIS(FIFO_TX_OVF);
1977         PIS(FIFO_RX_OVF);
1978         PIS(BTA);
1979         PIS(ECC_NO_CORR);
1980         PIS(FIFO_TX_UDF);
1981         PIS(PP_BUSY_CHANGE);
1982 #undef PIS
1983
1984 #define PIS(x) \
1985         seq_printf(s, "%-20s %10d\n", #x, \
1986                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1987
1988         seq_printf(s, "-- CIO interrupts --\n");
1989         PIS(ERRSYNCESC1);
1990         PIS(ERRSYNCESC2);
1991         PIS(ERRSYNCESC3);
1992         PIS(ERRESC1);
1993         PIS(ERRESC2);
1994         PIS(ERRESC3);
1995         PIS(ERRCONTROL1);
1996         PIS(ERRCONTROL2);
1997         PIS(ERRCONTROL3);
1998         PIS(STATEULPS1);
1999         PIS(STATEULPS2);
2000         PIS(STATEULPS3);
2001         PIS(ERRCONTENTIONLP0_1);
2002         PIS(ERRCONTENTIONLP1_1);
2003         PIS(ERRCONTENTIONLP0_2);
2004         PIS(ERRCONTENTIONLP1_2);
2005         PIS(ERRCONTENTIONLP0_3);
2006         PIS(ERRCONTENTIONLP1_3);
2007         PIS(ULPSACTIVENOT_ALL0);
2008         PIS(ULPSACTIVENOT_ALL1);
2009 #undef PIS
2010 }
2011
2012 static void dsi1_dump_irqs(struct seq_file *s)
2013 {
2014         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2015
2016         dsi_dump_dsidev_irqs(dsidev, s);
2017 }
2018
2019 static void dsi2_dump_irqs(struct seq_file *s)
2020 {
2021         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2022
2023         dsi_dump_dsidev_irqs(dsidev, s);
2024 }
2025 #endif
2026
2027 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
2028                 struct seq_file *s)
2029 {
2030 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
2031
2032         if (dsi_runtime_get(dsidev))
2033                 return;
2034         dsi_enable_scp_clk(dsidev);
2035
2036         DUMPREG(DSI_REVISION);
2037         DUMPREG(DSI_SYSCONFIG);
2038         DUMPREG(DSI_SYSSTATUS);
2039         DUMPREG(DSI_IRQSTATUS);
2040         DUMPREG(DSI_IRQENABLE);
2041         DUMPREG(DSI_CTRL);
2042         DUMPREG(DSI_COMPLEXIO_CFG1);
2043         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
2044         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
2045         DUMPREG(DSI_CLK_CTRL);
2046         DUMPREG(DSI_TIMING1);
2047         DUMPREG(DSI_TIMING2);
2048         DUMPREG(DSI_VM_TIMING1);
2049         DUMPREG(DSI_VM_TIMING2);
2050         DUMPREG(DSI_VM_TIMING3);
2051         DUMPREG(DSI_CLK_TIMING);
2052         DUMPREG(DSI_TX_FIFO_VC_SIZE);
2053         DUMPREG(DSI_RX_FIFO_VC_SIZE);
2054         DUMPREG(DSI_COMPLEXIO_CFG2);
2055         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
2056         DUMPREG(DSI_VM_TIMING4);
2057         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
2058         DUMPREG(DSI_VM_TIMING5);
2059         DUMPREG(DSI_VM_TIMING6);
2060         DUMPREG(DSI_VM_TIMING7);
2061         DUMPREG(DSI_STOPCLK_TIMING);
2062
2063         DUMPREG(DSI_VC_CTRL(0));
2064         DUMPREG(DSI_VC_TE(0));
2065         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
2066         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
2067         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
2068         DUMPREG(DSI_VC_IRQSTATUS(0));
2069         DUMPREG(DSI_VC_IRQENABLE(0));
2070
2071         DUMPREG(DSI_VC_CTRL(1));
2072         DUMPREG(DSI_VC_TE(1));
2073         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
2074         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
2075         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
2076         DUMPREG(DSI_VC_IRQSTATUS(1));
2077         DUMPREG(DSI_VC_IRQENABLE(1));
2078
2079         DUMPREG(DSI_VC_CTRL(2));
2080         DUMPREG(DSI_VC_TE(2));
2081         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
2082         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
2083         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
2084         DUMPREG(DSI_VC_IRQSTATUS(2));
2085         DUMPREG(DSI_VC_IRQENABLE(2));
2086
2087         DUMPREG(DSI_VC_CTRL(3));
2088         DUMPREG(DSI_VC_TE(3));
2089         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
2090         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
2091         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
2092         DUMPREG(DSI_VC_IRQSTATUS(3));
2093         DUMPREG(DSI_VC_IRQENABLE(3));
2094
2095         DUMPREG(DSI_DSIPHY_CFG0);
2096         DUMPREG(DSI_DSIPHY_CFG1);
2097         DUMPREG(DSI_DSIPHY_CFG2);
2098         DUMPREG(DSI_DSIPHY_CFG5);
2099
2100         DUMPREG(DSI_PLL_CONTROL);
2101         DUMPREG(DSI_PLL_STATUS);
2102         DUMPREG(DSI_PLL_GO);
2103         DUMPREG(DSI_PLL_CONFIGURATION1);
2104         DUMPREG(DSI_PLL_CONFIGURATION2);
2105
2106         dsi_disable_scp_clk(dsidev);
2107         dsi_runtime_put(dsidev);
2108 #undef DUMPREG
2109 }
2110
2111 static void dsi1_dump_regs(struct seq_file *s)
2112 {
2113         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2114
2115         dsi_dump_dsidev_regs(dsidev, s);
2116 }
2117
2118 static void dsi2_dump_regs(struct seq_file *s)
2119 {
2120         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2121
2122         dsi_dump_dsidev_regs(dsidev, s);
2123 }
2124
2125 enum dsi_cio_power_state {
2126         DSI_COMPLEXIO_POWER_OFF         = 0x0,
2127         DSI_COMPLEXIO_POWER_ON          = 0x1,
2128         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
2129 };
2130
2131 static int dsi_cio_power(struct platform_device *dsidev,
2132                 enum dsi_cio_power_state state)
2133 {
2134         int t = 0;
2135
2136         /* PWR_CMD */
2137         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2138
2139         /* PWR_STATUS */
2140         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2141                         26, 25) != state) {
2142                 if (++t > 1000) {
2143                         DSSERR("failed to set complexio power state to "
2144                                         "%d\n", state);
2145                         return -ENODEV;
2146                 }
2147                 udelay(1);
2148         }
2149
2150         return 0;
2151 }
2152
2153 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2154 {
2155         int val;
2156
2157         /* line buffer on OMAP3 is 1024 x 24bits */
2158         /* XXX: for some reason using full buffer size causes
2159          * considerable TX slowdown with update sizes that fill the
2160          * whole buffer */
2161         if (!dss_has_feature(FEAT_DSI_GNQ))
2162                 return 1023 * 3;
2163
2164         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2165
2166         switch (val) {
2167         case 1:
2168                 return 512 * 3;         /* 512x24 bits */
2169         case 2:
2170                 return 682 * 3;         /* 682x24 bits */
2171         case 3:
2172                 return 853 * 3;         /* 853x24 bits */
2173         case 4:
2174                 return 1024 * 3;        /* 1024x24 bits */
2175         case 5:
2176                 return 1194 * 3;        /* 1194x24 bits */
2177         case 6:
2178                 return 1365 * 3;        /* 1365x24 bits */
2179         case 7:
2180                 return 1920 * 3;        /* 1920x24 bits */
2181         default:
2182                 BUG();
2183                 return 0;
2184         }
2185 }
2186
2187 static int dsi_set_lane_config(struct platform_device *dsidev)
2188 {
2189         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2190         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2191         static const enum dsi_lane_function functions[] = {
2192                 DSI_LANE_CLK,
2193                 DSI_LANE_DATA1,
2194                 DSI_LANE_DATA2,
2195                 DSI_LANE_DATA3,
2196                 DSI_LANE_DATA4,
2197         };
2198         u32 r;
2199         int i;
2200
2201         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2202
2203         for (i = 0; i < dsi->num_lanes_used; ++i) {
2204                 unsigned offset = offsets[i];
2205                 unsigned polarity, lane_number;
2206                 unsigned t;
2207
2208                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2209                         if (dsi->lanes[t].function == functions[i])
2210                                 break;
2211
2212                 if (t == dsi->num_lanes_supported)
2213                         return -EINVAL;
2214
2215                 lane_number = t;
2216                 polarity = dsi->lanes[t].polarity;
2217
2218                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2219                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2220         }
2221
2222         /* clear the unused lanes */
2223         for (; i < dsi->num_lanes_supported; ++i) {
2224                 unsigned offset = offsets[i];
2225
2226                 r = FLD_MOD(r, 0, offset + 2, offset);
2227                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2228         }
2229
2230         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2231
2232         return 0;
2233 }
2234
2235 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2236 {
2237         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2238
2239         /* convert time in ns to ddr ticks, rounding up */
2240         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2241         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2242 }
2243
2244 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2245 {
2246         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2247
2248         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2249         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2250 }
2251
2252 static void dsi_cio_timings(struct platform_device *dsidev)
2253 {
2254         u32 r;
2255         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2256         u32 tlpx_half, tclk_trail, tclk_zero;
2257         u32 tclk_prepare;
2258
2259         /* calculate timings */
2260
2261         /* 1 * DDR_CLK = 2 * UI */
2262
2263         /* min 40ns + 4*UI      max 85ns + 6*UI */
2264         ths_prepare = ns2ddr(dsidev, 70) + 2;
2265
2266         /* min 145ns + 10*UI */
2267         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2268
2269         /* min max(8*UI, 60ns+4*UI) */
2270         ths_trail = ns2ddr(dsidev, 60) + 5;
2271
2272         /* min 100ns */
2273         ths_exit = ns2ddr(dsidev, 145);
2274
2275         /* tlpx min 50n */
2276         tlpx_half = ns2ddr(dsidev, 25);
2277
2278         /* min 60ns */
2279         tclk_trail = ns2ddr(dsidev, 60) + 2;
2280
2281         /* min 38ns, max 95ns */
2282         tclk_prepare = ns2ddr(dsidev, 65);
2283
2284         /* min tclk-prepare + tclk-zero = 300ns */
2285         tclk_zero = ns2ddr(dsidev, 260);
2286
2287         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2288                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2289                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2290         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2291                         ths_trail, ddr2ns(dsidev, ths_trail),
2292                         ths_exit, ddr2ns(dsidev, ths_exit));
2293
2294         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2295                         "tclk_zero %u (%uns)\n",
2296                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2297                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2298                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2299         DSSDBG("tclk_prepare %u (%uns)\n",
2300                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2301
2302         /* program timings */
2303
2304         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2305         r = FLD_MOD(r, ths_prepare, 31, 24);
2306         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2307         r = FLD_MOD(r, ths_trail, 15, 8);
2308         r = FLD_MOD(r, ths_exit, 7, 0);
2309         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2310
2311         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2312         r = FLD_MOD(r, tlpx_half, 20, 16);
2313         r = FLD_MOD(r, tclk_trail, 15, 8);
2314         r = FLD_MOD(r, tclk_zero, 7, 0);
2315
2316         if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2317                 r = FLD_MOD(r, 0, 21, 21);      /* DCCEN = disable */
2318                 r = FLD_MOD(r, 1, 22, 22);      /* CLKINP_DIVBY2EN = enable */
2319                 r = FLD_MOD(r, 1, 23, 23);      /* CLKINP_SEL = enable */
2320         }
2321
2322         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2323
2324         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2325         r = FLD_MOD(r, tclk_prepare, 7, 0);
2326         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2327 }
2328
2329 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2330 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2331                 unsigned mask_p, unsigned mask_n)
2332 {
2333         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2334         int i;
2335         u32 l;
2336         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2337
2338         l = 0;
2339
2340         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2341                 unsigned p = dsi->lanes[i].polarity;
2342
2343                 if (mask_p & (1 << i))
2344                         l |= 1 << (i * 2 + (p ? 0 : 1));
2345
2346                 if (mask_n & (1 << i))
2347                         l |= 1 << (i * 2 + (p ? 1 : 0));
2348         }
2349
2350         /*
2351          * Bits in REGLPTXSCPDAT4TO0DXDY:
2352          * 17: DY0 18: DX0
2353          * 19: DY1 20: DX1
2354          * 21: DY2 22: DX2
2355          * 23: DY3 24: DX3
2356          * 25: DY4 26: DX4
2357          */
2358
2359         /* Set the lane override configuration */
2360
2361         /* REGLPTXSCPDAT4TO0DXDY */
2362         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2363
2364         /* Enable lane override */
2365
2366         /* ENLPTXSCPDAT */
2367         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2368 }
2369
2370 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2371 {
2372         /* Disable lane override */
2373         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2374         /* Reset the lane override configuration */
2375         /* REGLPTXSCPDAT4TO0DXDY */
2376         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2377 }
2378
2379 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2380 {
2381         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2382         int t, i;
2383         bool in_use[DSI_MAX_NR_LANES];
2384         static const u8 offsets_old[] = { 28, 27, 26 };
2385         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2386         const u8 *offsets;
2387
2388         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2389                 offsets = offsets_old;
2390         else
2391                 offsets = offsets_new;
2392
2393         for (i = 0; i < dsi->num_lanes_supported; ++i)
2394                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2395
2396         t = 100000;
2397         while (true) {
2398                 u32 l;
2399                 int ok;
2400
2401                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2402
2403                 ok = 0;
2404                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2405                         if (!in_use[i] || (l & (1 << offsets[i])))
2406                                 ok++;
2407                 }
2408
2409                 if (ok == dsi->num_lanes_supported)
2410                         break;
2411
2412                 if (--t == 0) {
2413                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2414                                 if (!in_use[i] || (l & (1 << offsets[i])))
2415                                         continue;
2416
2417                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2418                                                 "out of reset\n", i);
2419                         }
2420                         return -EIO;
2421                 }
2422         }
2423
2424         return 0;
2425 }
2426
2427 /* return bitmask of enabled lanes, lane0 being the lsb */
2428 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2429 {
2430         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2431         unsigned mask = 0;
2432         int i;
2433
2434         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2435                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2436                         mask |= 1 << i;
2437         }
2438
2439         return mask;
2440 }
2441
2442 static int dsi_cio_init(struct platform_device *dsidev)
2443 {
2444         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2445         int r;
2446         u32 l;
2447
2448         DSSDBG("DSI CIO init starts");
2449
2450         r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2451         if (r)
2452                 return r;
2453
2454         dsi_enable_scp_clk(dsidev);
2455
2456         /* A dummy read using the SCP interface to any DSIPHY register is
2457          * required after DSIPHY reset to complete the reset of the DSI complex
2458          * I/O. */
2459         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2460
2461         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2462                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2463                 r = -EIO;
2464                 goto err_scp_clk_dom;
2465         }
2466
2467         r = dsi_set_lane_config(dsidev);
2468         if (r)
2469                 goto err_scp_clk_dom;
2470
2471         /* set TX STOP MODE timer to maximum for this operation */
2472         l = dsi_read_reg(dsidev, DSI_TIMING1);
2473         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2474         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2475         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2476         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2477         dsi_write_reg(dsidev, DSI_TIMING1, l);
2478
2479         if (dsi->ulps_enabled) {
2480                 unsigned mask_p;
2481                 int i;
2482
2483                 DSSDBG("manual ulps exit\n");
2484
2485                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2486                  * stop state. DSS HW cannot do this via the normal
2487                  * ULPS exit sequence, as after reset the DSS HW thinks
2488                  * that we are not in ULPS mode, and refuses to send the
2489                  * sequence. So we need to send the ULPS exit sequence
2490                  * manually by setting positive lines high and negative lines
2491                  * low for 1ms.
2492                  */
2493
2494                 mask_p = 0;
2495
2496                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2497                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2498                                 continue;
2499                         mask_p |= 1 << i;
2500                 }
2501
2502                 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2503         }
2504
2505         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2506         if (r)
2507                 goto err_cio_pwr;
2508
2509         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2510                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2511                 r = -ENODEV;
2512                 goto err_cio_pwr_dom;
2513         }
2514
2515         dsi_if_enable(dsidev, true);
2516         dsi_if_enable(dsidev, false);
2517         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2518
2519         r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2520         if (r)
2521                 goto err_tx_clk_esc_rst;
2522
2523         if (dsi->ulps_enabled) {
2524                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2525                 ktime_t wait = ns_to_ktime(1000 * 1000);
2526                 set_current_state(TASK_UNINTERRUPTIBLE);
2527                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2528
2529                 /* Disable the override. The lanes should be set to Mark-11
2530                  * state by the HW */
2531                 dsi_cio_disable_lane_override(dsidev);
2532         }
2533
2534         /* FORCE_TX_STOP_MODE_IO */
2535         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2536
2537         dsi_cio_timings(dsidev);
2538
2539         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2540                 /* DDR_CLK_ALWAYS_ON */
2541                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2542                         dsi->vm_timings.ddr_clk_always_on, 13, 13);
2543         }
2544
2545         dsi->ulps_enabled = false;
2546
2547         DSSDBG("CIO init done\n");
2548
2549         return 0;
2550
2551 err_tx_clk_esc_rst:
2552         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2553 err_cio_pwr_dom:
2554         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2555 err_cio_pwr:
2556         if (dsi->ulps_enabled)
2557                 dsi_cio_disable_lane_override(dsidev);
2558 err_scp_clk_dom:
2559         dsi_disable_scp_clk(dsidev);
2560         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2561         return r;
2562 }
2563
2564 static void dsi_cio_uninit(struct platform_device *dsidev)
2565 {
2566         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2567
2568         /* DDR_CLK_ALWAYS_ON */
2569         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2570
2571         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2572         dsi_disable_scp_clk(dsidev);
2573         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2574 }
2575
2576 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2577                 enum fifo_size size1, enum fifo_size size2,
2578                 enum fifo_size size3, enum fifo_size size4)
2579 {
2580         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2581         u32 r = 0;
2582         int add = 0;
2583         int i;
2584
2585         dsi->vc[0].fifo_size = size1;
2586         dsi->vc[1].fifo_size = size2;
2587         dsi->vc[2].fifo_size = size3;
2588         dsi->vc[3].fifo_size = size4;
2589
2590         for (i = 0; i < 4; i++) {
2591                 u8 v;
2592                 int size = dsi->vc[i].fifo_size;
2593
2594                 if (add + size > 4) {
2595                         DSSERR("Illegal FIFO configuration\n");
2596                         BUG();
2597                         return;
2598                 }
2599
2600                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2601                 r |= v << (8 * i);
2602                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2603                 add += size;
2604         }
2605
2606         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2607 }
2608
2609 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2610                 enum fifo_size size1, enum fifo_size size2,
2611                 enum fifo_size size3, enum fifo_size size4)
2612 {
2613         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2614         u32 r = 0;
2615         int add = 0;
2616         int i;
2617
2618         dsi->vc[0].fifo_size = size1;
2619         dsi->vc[1].fifo_size = size2;
2620         dsi->vc[2].fifo_size = size3;
2621         dsi->vc[3].fifo_size = size4;
2622
2623         for (i = 0; i < 4; i++) {
2624                 u8 v;
2625                 int size = dsi->vc[i].fifo_size;
2626
2627                 if (add + size > 4) {
2628                         DSSERR("Illegal FIFO configuration\n");
2629                         BUG();
2630                         return;
2631                 }
2632
2633                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2634                 r |= v << (8 * i);
2635                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2636                 add += size;
2637         }
2638
2639         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2640 }
2641
2642 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2643 {
2644         u32 r;
2645
2646         r = dsi_read_reg(dsidev, DSI_TIMING1);
2647         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2648         dsi_write_reg(dsidev, DSI_TIMING1, r);
2649
2650         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2651                 DSSERR("TX_STOP bit not going down\n");
2652                 return -EIO;
2653         }
2654
2655         return 0;
2656 }
2657
2658 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2659 {
2660         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2661 }
2662
2663 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2664 {
2665         struct dsi_packet_sent_handler_data *vp_data =
2666                 (struct dsi_packet_sent_handler_data *) data;
2667         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2668         const int channel = dsi->update_channel;
2669         u8 bit = dsi->te_enabled ? 30 : 31;
2670
2671         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2672                 complete(vp_data->completion);
2673 }
2674
2675 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2676 {
2677         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2678         DECLARE_COMPLETION_ONSTACK(completion);
2679         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2680         int r = 0;
2681         u8 bit;
2682
2683         bit = dsi->te_enabled ? 30 : 31;
2684
2685         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2686                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2687         if (r)
2688                 goto err0;
2689
2690         /* Wait for completion only if TE_EN/TE_START is still set */
2691         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2692                 if (wait_for_completion_timeout(&completion,
2693                                 msecs_to_jiffies(10)) == 0) {
2694                         DSSERR("Failed to complete previous frame transfer\n");
2695                         r = -EIO;
2696                         goto err1;
2697                 }
2698         }
2699
2700         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2701                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2702
2703         return 0;
2704 err1:
2705         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2706                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2707 err0:
2708         return r;
2709 }
2710
2711 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2712 {
2713         struct dsi_packet_sent_handler_data *l4_data =
2714                 (struct dsi_packet_sent_handler_data *) data;
2715         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2716         const int channel = dsi->update_channel;
2717
2718         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2719                 complete(l4_data->completion);
2720 }
2721
2722 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2723 {
2724         DECLARE_COMPLETION_ONSTACK(completion);
2725         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2726         int r = 0;
2727
2728         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2729                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2730         if (r)
2731                 goto err0;
2732
2733         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2734         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2735                 if (wait_for_completion_timeout(&completion,
2736                                 msecs_to_jiffies(10)) == 0) {
2737                         DSSERR("Failed to complete previous l4 transfer\n");
2738                         r = -EIO;
2739                         goto err1;
2740                 }
2741         }
2742
2743         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2744                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2745
2746         return 0;
2747 err1:
2748         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2749                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2750 err0:
2751         return r;
2752 }
2753
2754 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2755 {
2756         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2757
2758         WARN_ON(!dsi_bus_is_locked(dsidev));
2759
2760         WARN_ON(in_interrupt());
2761
2762         if (!dsi_vc_is_enabled(dsidev, channel))
2763                 return 0;
2764
2765         switch (dsi->vc[channel].source) {
2766         case DSI_VC_SOURCE_VP:
2767                 return dsi_sync_vc_vp(dsidev, channel);
2768         case DSI_VC_SOURCE_L4:
2769                 return dsi_sync_vc_l4(dsidev, channel);
2770         default:
2771                 BUG();
2772                 return -EINVAL;
2773         }
2774 }
2775
2776 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2777                 bool enable)
2778 {
2779         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2780                         channel, enable);
2781
2782         enable = enable ? 1 : 0;
2783
2784         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2785
2786         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2787                 0, enable) != enable) {
2788                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2789                         return -EIO;
2790         }
2791
2792         return 0;
2793 }
2794
2795 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2796 {
2797         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2798         u32 r;
2799
2800         DSSDBG("Initial config of virtual channel %d", channel);
2801
2802         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2803
2804         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2805                 DSSERR("VC(%d) busy when trying to configure it!\n",
2806                                 channel);
2807
2808         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2809         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2810         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2811         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2812         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2813         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2814         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2815         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2816                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2817
2818         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2819         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2820
2821         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2822
2823         dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2824 }
2825
2826 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2827                 enum dsi_vc_source source)
2828 {
2829         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2830
2831         if (dsi->vc[channel].source == source)
2832                 return 0;
2833
2834         DSSDBG("Source config of virtual channel %d", channel);
2835
2836         dsi_sync_vc(dsidev, channel);
2837
2838         dsi_vc_enable(dsidev, channel, 0);
2839
2840         /* VC_BUSY */
2841         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2842                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2843                 return -EIO;
2844         }
2845
2846         /* SOURCE, 0 = L4, 1 = video port */
2847         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2848
2849         /* DCS_CMD_ENABLE */
2850         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2851                 bool enable = source == DSI_VC_SOURCE_VP;
2852                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2853         }
2854
2855         dsi_vc_enable(dsidev, channel, 1);
2856
2857         dsi->vc[channel].source = source;
2858
2859         return 0;
2860 }
2861
2862 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2863                 bool enable)
2864 {
2865         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2866         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2867
2868         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2869
2870         WARN_ON(!dsi_bus_is_locked(dsidev));
2871
2872         dsi_vc_enable(dsidev, channel, 0);
2873         dsi_if_enable(dsidev, 0);
2874
2875         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2876
2877         dsi_vc_enable(dsidev, channel, 1);
2878         dsi_if_enable(dsidev, 1);
2879
2880         dsi_force_tx_stop_mode_io(dsidev);
2881
2882         /* start the DDR clock by sending a NULL packet */
2883         if (dsi->vm_timings.ddr_clk_always_on && enable)
2884                 dsi_vc_send_null(dssdev, channel);
2885 }
2886 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2887
2888 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2889 {
2890         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2891                 u32 val;
2892                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2893                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2894                                 (val >> 0) & 0xff,
2895                                 (val >> 8) & 0xff,
2896                                 (val >> 16) & 0xff,
2897                                 (val >> 24) & 0xff);
2898         }
2899 }
2900
2901 static void dsi_show_rx_ack_with_err(u16 err)
2902 {
2903         DSSERR("\tACK with ERROR (%#x):\n", err);
2904         if (err & (1 << 0))
2905                 DSSERR("\t\tSoT Error\n");
2906         if (err & (1 << 1))
2907                 DSSERR("\t\tSoT Sync Error\n");
2908         if (err & (1 << 2))
2909                 DSSERR("\t\tEoT Sync Error\n");
2910         if (err & (1 << 3))
2911                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2912         if (err & (1 << 4))
2913                 DSSERR("\t\tLP Transmit Sync Error\n");
2914         if (err & (1 << 5))
2915                 DSSERR("\t\tHS Receive Timeout Error\n");
2916         if (err & (1 << 6))
2917                 DSSERR("\t\tFalse Control Error\n");
2918         if (err & (1 << 7))
2919                 DSSERR("\t\t(reserved7)\n");
2920         if (err & (1 << 8))
2921                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2922         if (err & (1 << 9))
2923                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2924         if (err & (1 << 10))
2925                 DSSERR("\t\tChecksum Error\n");
2926         if (err & (1 << 11))
2927                 DSSERR("\t\tData type not recognized\n");
2928         if (err & (1 << 12))
2929                 DSSERR("\t\tInvalid VC ID\n");
2930         if (err & (1 << 13))
2931                 DSSERR("\t\tInvalid Transmission Length\n");
2932         if (err & (1 << 14))
2933                 DSSERR("\t\t(reserved14)\n");
2934         if (err & (1 << 15))
2935                 DSSERR("\t\tDSI Protocol Violation\n");
2936 }
2937
2938 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2939                 int channel)
2940 {
2941         /* RX_FIFO_NOT_EMPTY */
2942         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2943                 u32 val;
2944                 u8 dt;
2945                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2946                 DSSERR("\trawval %#08x\n", val);
2947                 dt = FLD_GET(val, 5, 0);
2948                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2949                         u16 err = FLD_GET(val, 23, 8);
2950                         dsi_show_rx_ack_with_err(err);
2951                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2952                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2953                                         FLD_GET(val, 23, 8));
2954                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2955                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2956                                         FLD_GET(val, 23, 8));
2957                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2958                         DSSERR("\tDCS long response, len %d\n",
2959                                         FLD_GET(val, 23, 8));
2960                         dsi_vc_flush_long_data(dsidev, channel);
2961                 } else {
2962                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2963                 }
2964         }
2965         return 0;
2966 }
2967
2968 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2969 {
2970         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2971
2972         if (dsi->debug_write || dsi->debug_read)
2973                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2974
2975         WARN_ON(!dsi_bus_is_locked(dsidev));
2976
2977         /* RX_FIFO_NOT_EMPTY */
2978         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2979                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2980                 dsi_vc_flush_receive_data(dsidev, channel);
2981         }
2982
2983         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2984
2985         /* flush posted write */
2986         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2987
2988         return 0;
2989 }
2990
2991 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2992 {
2993         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2994         DECLARE_COMPLETION_ONSTACK(completion);
2995         int r = 0;
2996         u32 err;
2997
2998         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2999                         &completion, DSI_VC_IRQ_BTA);
3000         if (r)
3001                 goto err0;
3002
3003         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
3004                         DSI_IRQ_ERROR_MASK);
3005         if (r)
3006                 goto err1;
3007
3008         r = dsi_vc_send_bta(dsidev, channel);
3009         if (r)
3010                 goto err2;
3011
3012         if (wait_for_completion_timeout(&completion,
3013                                 msecs_to_jiffies(500)) == 0) {
3014                 DSSERR("Failed to receive BTA\n");
3015                 r = -EIO;
3016                 goto err2;
3017         }
3018
3019         err = dsi_get_errors(dsidev);
3020         if (err) {
3021                 DSSERR("Error while sending BTA: %x\n", err);
3022                 r = -EIO;
3023                 goto err2;
3024         }
3025 err2:
3026         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
3027                         DSI_IRQ_ERROR_MASK);
3028 err1:
3029         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
3030                         &completion, DSI_VC_IRQ_BTA);
3031 err0:
3032         return r;
3033 }
3034 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
3035
3036 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
3037                 int channel, u8 data_type, u16 len, u8 ecc)
3038 {
3039         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3040         u32 val;
3041         u8 data_id;
3042
3043         WARN_ON(!dsi_bus_is_locked(dsidev));
3044
3045         data_id = data_type | dsi->vc[channel].vc_id << 6;
3046
3047         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
3048                 FLD_VAL(ecc, 31, 24);
3049
3050         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
3051 }
3052
3053 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
3054                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
3055 {
3056         u32 val;
3057
3058         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
3059
3060 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3061                         b1, b2, b3, b4, val); */
3062
3063         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3064 }
3065
3066 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3067                 u8 data_type, u8 *data, u16 len, u8 ecc)
3068 {
3069         /*u32 val; */
3070         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3071         int i;
3072         u8 *p;
3073         int r = 0;
3074         u8 b1, b2, b3, b4;
3075
3076         if (dsi->debug_write)
3077                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3078
3079         /* len + header */
3080         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3081                 DSSERR("unable to send long packet: packet too long.\n");
3082                 return -EINVAL;
3083         }
3084
3085         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3086
3087         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3088
3089         p = data;
3090         for (i = 0; i < len >> 2; i++) {
3091                 if (dsi->debug_write)
3092                         DSSDBG("\tsending full packet %d\n", i);
3093
3094                 b1 = *p++;
3095                 b2 = *p++;
3096                 b3 = *p++;
3097                 b4 = *p++;
3098
3099                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3100         }
3101
3102         i = len % 4;
3103         if (i) {
3104                 b1 = 0; b2 = 0; b3 = 0;
3105
3106                 if (dsi->debug_write)
3107                         DSSDBG("\tsending remainder bytes %d\n", i);
3108
3109                 switch (i) {
3110                 case 3:
3111                         b1 = *p++;
3112                         b2 = *p++;
3113                         b3 = *p++;
3114                         break;
3115                 case 2:
3116                         b1 = *p++;
3117                         b2 = *p++;
3118                         break;
3119                 case 1:
3120                         b1 = *p++;
3121                         break;
3122                 }
3123
3124                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3125         }
3126
3127         return r;
3128 }
3129
3130 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3131                 u8 data_type, u16 data, u8 ecc)
3132 {
3133         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3134         u32 r;
3135         u8 data_id;
3136
3137         WARN_ON(!dsi_bus_is_locked(dsidev));
3138
3139         if (dsi->debug_write)
3140                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3141                                 channel,
3142                                 data_type, data & 0xff, (data >> 8) & 0xff);
3143
3144         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3145
3146         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3147                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3148                 return -EINVAL;
3149         }
3150
3151         data_id = data_type | dsi->vc[channel].vc_id << 6;
3152
3153         r = (data_id << 0) | (data << 8) | (ecc << 24);
3154
3155         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3156
3157         return 0;
3158 }
3159
3160 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3161 {
3162         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3163
3164         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3165                 0, 0);
3166 }
3167 EXPORT_SYMBOL(dsi_vc_send_null);
3168
3169 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3170                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3171 {
3172         int r;
3173
3174         if (len == 0) {
3175                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3176                 r = dsi_vc_send_short(dsidev, channel,
3177                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3178         } else if (len == 1) {
3179                 r = dsi_vc_send_short(dsidev, channel,
3180                                 type == DSS_DSI_CONTENT_GENERIC ?
3181                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3182                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3183         } else if (len == 2) {
3184                 r = dsi_vc_send_short(dsidev, channel,
3185                                 type == DSS_DSI_CONTENT_GENERIC ?
3186                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3187                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3188                                 data[0] | (data[1] << 8), 0);
3189         } else {
3190                 r = dsi_vc_send_long(dsidev, channel,
3191                                 type == DSS_DSI_CONTENT_GENERIC ?
3192                                 MIPI_DSI_GENERIC_LONG_WRITE :
3193                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3194         }
3195
3196         return r;
3197 }
3198
3199 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3200                 u8 *data, int len)
3201 {
3202         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3203
3204         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3205                         DSS_DSI_CONTENT_DCS);
3206 }
3207 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3208
3209 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3210                 u8 *data, int len)
3211 {
3212         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3213
3214         return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3215                         DSS_DSI_CONTENT_GENERIC);
3216 }
3217 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3218
3219 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3220                 u8 *data, int len, enum dss_dsi_content_type type)
3221 {
3222         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3223         int r;
3224
3225         r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3226         if (r)
3227                 goto err;
3228
3229         r = dsi_vc_send_bta_sync(dssdev, channel);
3230         if (r)
3231                 goto err;
3232
3233         /* RX_FIFO_NOT_EMPTY */
3234         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3235                 DSSERR("rx fifo not empty after write, dumping data:\n");
3236                 dsi_vc_flush_receive_data(dsidev, channel);
3237                 r = -EIO;
3238                 goto err;
3239         }
3240
3241         return 0;
3242 err:
3243         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3244                         channel, data[0], len);
3245         return r;
3246 }
3247
3248 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3249                 int len)
3250 {
3251         return dsi_vc_write_common(dssdev, channel, data, len,
3252                         DSS_DSI_CONTENT_DCS);
3253 }
3254 EXPORT_SYMBOL(dsi_vc_dcs_write);
3255
3256 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3257                 int len)
3258 {
3259         return dsi_vc_write_common(dssdev, channel, data, len,
3260                         DSS_DSI_CONTENT_GENERIC);
3261 }
3262 EXPORT_SYMBOL(dsi_vc_generic_write);
3263
3264 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3265 {
3266         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3267 }
3268 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3269
3270 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3271 {
3272         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3273 }
3274 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3275
3276 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3277                 u8 param)
3278 {
3279         u8 buf[2];
3280         buf[0] = dcs_cmd;
3281         buf[1] = param;
3282         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3283 }
3284 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3285
3286 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3287                 u8 param)
3288 {
3289         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3290 }
3291 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3292
3293 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3294                 u8 param1, u8 param2)
3295 {
3296         u8 buf[2];
3297         buf[0] = param1;
3298         buf[1] = param2;
3299         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3300 }
3301 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3302
3303 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3304                 int channel, u8 dcs_cmd)
3305 {
3306         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3307         int r;
3308
3309         if (dsi->debug_read)
3310                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3311                         channel, dcs_cmd);
3312
3313         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3314         if (r) {
3315                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3316                         " failed\n", channel, dcs_cmd);
3317                 return r;
3318         }
3319
3320         return 0;
3321 }
3322
3323 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3324                 int channel, u8 *reqdata, int reqlen)
3325 {
3326         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3327         u16 data;
3328         u8 data_type;
3329         int r;
3330
3331         if (dsi->debug_read)
3332                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3333                         channel, reqlen);
3334
3335         if (reqlen == 0) {
3336                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3337                 data = 0;
3338         } else if (reqlen == 1) {
3339                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3340                 data = reqdata[0];
3341         } else if (reqlen == 2) {
3342                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3343                 data = reqdata[0] | (reqdata[1] << 8);
3344         } else {
3345                 BUG();
3346                 return -EINVAL;
3347         }
3348
3349         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3350         if (r) {
3351                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3352                         " failed\n", channel, reqlen);
3353                 return r;
3354         }
3355
3356         return 0;
3357 }
3358
3359 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3360                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3361 {
3362         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3363         u32 val;
3364         u8 dt;
3365         int r;
3366
3367         /* RX_FIFO_NOT_EMPTY */
3368         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3369                 DSSERR("RX fifo empty when trying to read.\n");
3370                 r = -EIO;
3371                 goto err;
3372         }
3373
3374         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3375         if (dsi->debug_read)
3376                 DSSDBG("\theader: %08x\n", val);
3377         dt = FLD_GET(val, 5, 0);
3378         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3379                 u16 err = FLD_GET(val, 23, 8);
3380                 dsi_show_rx_ack_with_err(err);
3381                 r = -EIO;
3382                 goto err;
3383
3384         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3385                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3386                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3387                 u8 data = FLD_GET(val, 15, 8);
3388                 if (dsi->debug_read)
3389                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3390                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3391                                 "DCS", data);
3392
3393                 if (buflen < 1) {
3394                         r = -EIO;
3395                         goto err;
3396                 }
3397
3398                 buf[0] = data;
3399
3400                 return 1;
3401         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3402                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3403                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3404                 u16 data = FLD_GET(val, 23, 8);
3405                 if (dsi->debug_read)
3406                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3407                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3408                                 "DCS", data);
3409
3410                 if (buflen < 2) {
3411                         r = -EIO;
3412                         goto err;
3413                 }
3414
3415                 buf[0] = data & 0xff;
3416                 buf[1] = (data >> 8) & 0xff;
3417
3418                 return 2;
3419         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3420                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3421                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3422                 int w;
3423                 int len = FLD_GET(val, 23, 8);
3424                 if (dsi->debug_read)
3425                         DSSDBG("\t%s long response, len %d\n",
3426                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3427                                 "DCS", len);
3428
3429                 if (len > buflen) {
3430                         r = -EIO;
3431                         goto err;
3432                 }
3433
3434                 /* two byte checksum ends the packet, not included in len */
3435                 for (w = 0; w < len + 2;) {
3436                         int b;
3437                         val = dsi_read_reg(dsidev,
3438                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3439                         if (dsi->debug_read)
3440                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3441                                                 (val >> 0) & 0xff,
3442                                                 (val >> 8) & 0xff,
3443                                                 (val >> 16) & 0xff,
3444                                                 (val >> 24) & 0xff);
3445
3446                         for (b = 0; b < 4; ++b) {
3447                                 if (w < len)
3448                                         buf[w] = (val >> (b * 8)) & 0xff;
3449                                 /* we discard the 2 byte checksum */
3450                                 ++w;
3451                         }
3452                 }
3453
3454                 return len;
3455         } else {
3456                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3457                 r = -EIO;
3458                 goto err;
3459         }
3460
3461 err:
3462         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3463                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3464
3465         return r;
3466 }
3467
3468 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3469                 u8 *buf, int buflen)
3470 {
3471         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3472         int r;
3473
3474         r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3475         if (r)
3476                 goto err;
3477
3478         r = dsi_vc_send_bta_sync(dssdev, channel);
3479         if (r)
3480                 goto err;
3481
3482         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3483                 DSS_DSI_CONTENT_DCS);
3484         if (r < 0)
3485                 goto err;
3486
3487         if (r != buflen) {
3488                 r = -EIO;
3489                 goto err;
3490         }
3491
3492         return 0;
3493 err:
3494         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3495         return r;
3496 }
3497 EXPORT_SYMBOL(dsi_vc_dcs_read);
3498
3499 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3500                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3501 {
3502         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3503         int r;
3504
3505         r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3506         if (r)
3507                 return r;
3508
3509         r = dsi_vc_send_bta_sync(dssdev, channel);
3510         if (r)
3511                 return r;
3512
3513         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3514                 DSS_DSI_CONTENT_GENERIC);
3515         if (r < 0)
3516                 return r;
3517
3518         if (r != buflen) {
3519                 r = -EIO;
3520                 return r;
3521         }
3522
3523         return 0;
3524 }
3525
3526 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3527                 int buflen)
3528 {
3529         int r;
3530
3531         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3532         if (r) {
3533                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3534                 return r;
3535         }
3536
3537         return 0;
3538 }
3539 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3540
3541 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3542                 u8 *buf, int buflen)
3543 {
3544         int r;
3545
3546         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3547         if (r) {
3548                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3549                 return r;
3550         }
3551
3552         return 0;
3553 }
3554 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3555
3556 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3557                 u8 param1, u8 param2, u8 *buf, int buflen)
3558 {
3559         int r;
3560         u8 reqdata[2];
3561
3562         reqdata[0] = param1;
3563         reqdata[1] = param2;
3564
3565         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3566         if (r) {
3567                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3568                 return r;
3569         }
3570
3571         return 0;
3572 }
3573 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3574
3575 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3576                 u16 len)
3577 {
3578         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3579
3580         return dsi_vc_send_short(dsidev, channel,
3581                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3582 }
3583 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3584
3585 static int dsi_enter_ulps(struct platform_device *dsidev)
3586 {
3587         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3588         DECLARE_COMPLETION_ONSTACK(completion);
3589         int r, i;
3590         unsigned mask;
3591
3592         DSSDBG("Entering ULPS");
3593
3594         WARN_ON(!dsi_bus_is_locked(dsidev));
3595
3596         WARN_ON(dsi->ulps_enabled);
3597
3598         if (dsi->ulps_enabled)
3599                 return 0;
3600
3601         /* DDR_CLK_ALWAYS_ON */
3602         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3603                 dsi_if_enable(dsidev, 0);
3604                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3605                 dsi_if_enable(dsidev, 1);
3606         }
3607
3608         dsi_sync_vc(dsidev, 0);
3609         dsi_sync_vc(dsidev, 1);
3610         dsi_sync_vc(dsidev, 2);
3611         dsi_sync_vc(dsidev, 3);
3612
3613         dsi_force_tx_stop_mode_io(dsidev);
3614
3615         dsi_vc_enable(dsidev, 0, false);
3616         dsi_vc_enable(dsidev, 1, false);
3617         dsi_vc_enable(dsidev, 2, false);
3618         dsi_vc_enable(dsidev, 3, false);
3619
3620         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3621                 DSSERR("HS busy when enabling ULPS\n");
3622                 return -EIO;
3623         }
3624
3625         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3626                 DSSERR("LP busy when enabling ULPS\n");
3627                 return -EIO;
3628         }
3629
3630         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3631                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3632         if (r)
3633                 return r;
3634
3635         mask = 0;
3636
3637         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3638                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3639                         continue;
3640                 mask |= 1 << i;
3641         }
3642         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3643         /* LANEx_ULPS_SIG2 */
3644         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3645
3646         /* flush posted write and wait for SCP interface to finish the write */
3647         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3648
3649         if (wait_for_completion_timeout(&completion,
3650                                 msecs_to_jiffies(1000)) == 0) {
3651                 DSSERR("ULPS enable timeout\n");
3652                 r = -EIO;
3653                 goto err;
3654         }
3655
3656         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3657                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3658
3659         /* Reset LANEx_ULPS_SIG2 */
3660         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3661
3662         /* flush posted write and wait for SCP interface to finish the write */
3663         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3664
3665         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3666
3667         dsi_if_enable(dsidev, false);
3668
3669         dsi->ulps_enabled = true;
3670
3671         return 0;
3672
3673 err:
3674         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3675                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3676         return r;
3677 }
3678
3679 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3680                 unsigned ticks, bool x4, bool x16)
3681 {
3682         unsigned long fck;
3683         unsigned long total_ticks;
3684         u32 r;
3685
3686         BUG_ON(ticks > 0x1fff);
3687
3688         /* ticks in DSI_FCK */
3689         fck = dsi_fclk_rate(dsidev);
3690
3691         r = dsi_read_reg(dsidev, DSI_TIMING2);
3692         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3693         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3694         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3695         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3696         dsi_write_reg(dsidev, DSI_TIMING2, r);
3697
3698         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3699
3700         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3701                         total_ticks,
3702                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3703                         (total_ticks * 1000) / (fck / 1000 / 1000));
3704 }
3705
3706 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3707                 bool x8, bool x16)
3708 {
3709         unsigned long fck;
3710         unsigned long total_ticks;
3711         u32 r;
3712
3713         BUG_ON(ticks > 0x1fff);
3714
3715         /* ticks in DSI_FCK */
3716         fck = dsi_fclk_rate(dsidev);
3717
3718         r = dsi_read_reg(dsidev, DSI_TIMING1);
3719         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3720         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3721         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3722         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3723         dsi_write_reg(dsidev, DSI_TIMING1, r);
3724
3725         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3726
3727         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3728                         total_ticks,
3729                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3730                         (total_ticks * 1000) / (fck / 1000 / 1000));
3731 }
3732
3733 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3734                 unsigned ticks, bool x4, bool x16)
3735 {
3736         unsigned long fck;
3737         unsigned long total_ticks;
3738         u32 r;
3739
3740         BUG_ON(ticks > 0x1fff);
3741
3742         /* ticks in DSI_FCK */
3743         fck = dsi_fclk_rate(dsidev);
3744
3745         r = dsi_read_reg(dsidev, DSI_TIMING1);
3746         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3747         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3748         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3749         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3750         dsi_write_reg(dsidev, DSI_TIMING1, r);
3751
3752         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3753
3754         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3755                         total_ticks,
3756                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3757                         (total_ticks * 1000) / (fck / 1000 / 1000));
3758 }
3759
3760 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3761                 unsigned ticks, bool x4, bool x16)
3762 {
3763         unsigned long fck;
3764         unsigned long total_ticks;
3765         u32 r;
3766
3767         BUG_ON(ticks > 0x1fff);
3768
3769         /* ticks in TxByteClkHS */
3770         fck = dsi_get_txbyteclkhs(dsidev);
3771
3772         r = dsi_read_reg(dsidev, DSI_TIMING2);
3773         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3774         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3775         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3776         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3777         dsi_write_reg(dsidev, DSI_TIMING2, r);
3778
3779         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3780
3781         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3782                         total_ticks,
3783                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3784                         (total_ticks * 1000) / (fck / 1000 / 1000));
3785 }
3786
3787 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3788 {
3789         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3790         int num_line_buffers;
3791
3792         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3793                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3794                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3795                 struct omap_video_timings *timings = &dsi->timings;
3796                 /*
3797                  * Don't use line buffers if width is greater than the video
3798                  * port's line buffer size
3799                  */
3800                 if (line_buf_size <= timings->x_res * bpp / 8)
3801                         num_line_buffers = 0;
3802                 else
3803                         num_line_buffers = 2;
3804         } else {
3805                 /* Use maximum number of line buffers in command mode */
3806                 num_line_buffers = 2;
3807         }
3808
3809         /* LINE_BUFFER */
3810         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3811 }
3812
3813 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3814 {
3815         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3816         bool vsync_end = dsi->vm_timings.vp_vsync_end;
3817         bool hsync_end = dsi->vm_timings.vp_hsync_end;
3818         u32 r;
3819
3820         r = dsi_read_reg(dsidev, DSI_CTRL);
3821         r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
3822         r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
3823         r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
3824         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3825         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3826         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3827         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3828         dsi_write_reg(dsidev, DSI_CTRL, r);
3829 }
3830
3831 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3832 {
3833         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3834         int blanking_mode = dsi->vm_timings.blanking_mode;
3835         int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3836         int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3837         int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3838         u32 r;
3839
3840         /*
3841          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3842          * 1 = Long blanking packets are sent in corresponding blanking periods
3843          */
3844         r = dsi_read_reg(dsidev, DSI_CTRL);
3845         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3846         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3847         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3848         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3849         dsi_write_reg(dsidev, DSI_CTRL, r);
3850 }
3851
3852 /*
3853  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3854  * results in maximum transition time for data and clock lanes to enter and
3855  * exit HS mode. Hence, this is the scenario where the least amount of command
3856  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3857  * clock cycles that can be used to interleave command mode data in HS so that
3858  * all scenarios are satisfied.
3859  */
3860 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3861                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3862 {
3863         int transition;
3864
3865         /*
3866          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3867          * time of data lanes only, if it isn't set, we need to consider HS
3868          * transition time of both data and clock lanes. HS transition time
3869          * of Scenario 3 is considered.
3870          */
3871         if (ddr_alwon) {
3872                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3873         } else {
3874                 int trans1, trans2;
3875                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3876                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3877                                 enter_hs + 1;
3878                 transition = max(trans1, trans2);
3879         }
3880
3881         return blank > transition ? blank - transition : 0;
3882 }
3883
3884 /*
3885  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3886  * results in maximum transition time for data lanes to enter and exit LP mode.
3887  * Hence, this is the scenario where the least amount of command mode data can
3888  * be interleaved. We program the minimum amount of bytes that can be
3889  * interleaved in LP so that all scenarios are satisfied.
3890  */
3891 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3892                 int lp_clk_div, int tdsi_fclk)
3893 {
3894         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3895         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3896         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3897         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3898         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3899
3900         /* maximum LP transition time according to Scenario 1 */
3901         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3902
3903         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3904         tlp_avail = thsbyte_clk * (blank - trans_lp);
3905
3906         ttxclkesc = tdsi_fclk * lp_clk_div;
3907
3908         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3909                         26) / 16;
3910
3911         return max(lp_inter, 0);
3912 }
3913
3914 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3915 {
3916         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3917         int blanking_mode;
3918         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3919         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3920         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3921         int tclk_trail, ths_exit, exiths_clk;
3922         bool ddr_alwon;
3923         struct omap_video_timings *timings = &dsi->timings;
3924         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3925         int ndl = dsi->num_lanes_used - 1;
3926         int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3927         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3928         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3929         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3930         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3931         u32 r;
3932
3933         r = dsi_read_reg(dsidev, DSI_CTRL);
3934         blanking_mode = FLD_GET(r, 20, 20);
3935         hfp_blanking_mode = FLD_GET(r, 21, 21);
3936         hbp_blanking_mode = FLD_GET(r, 22, 22);
3937         hsa_blanking_mode = FLD_GET(r, 23, 23);
3938
3939         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3940         hbp = FLD_GET(r, 11, 0);
3941         hfp = FLD_GET(r, 23, 12);
3942         hsa = FLD_GET(r, 31, 24);
3943
3944         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3945         ddr_clk_post = FLD_GET(r, 7, 0);
3946         ddr_clk_pre = FLD_GET(r, 15, 8);
3947
3948         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3949         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3950         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3951
3952         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3953         lp_clk_div = FLD_GET(r, 12, 0);
3954         ddr_alwon = FLD_GET(r, 13, 13);
3955
3956         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3957         ths_exit = FLD_GET(r, 7, 0);
3958
3959         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3960         tclk_trail = FLD_GET(r, 15, 8);
3961
3962         exiths_clk = ths_exit + tclk_trail;
3963
3964         width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3965         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3966
3967         if (!hsa_blanking_mode) {
3968                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3969                                         enter_hs_mode_lat, exit_hs_mode_lat,
3970                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3971                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3972                                         enter_hs_mode_lat, exit_hs_mode_lat,
3973                                         lp_clk_div, dsi_fclk_hsdiv);
3974         }
3975
3976         if (!hfp_blanking_mode) {
3977                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3978                                         enter_hs_mode_lat, exit_hs_mode_lat,
3979                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3980                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3981                                         enter_hs_mode_lat, exit_hs_mode_lat,
3982                                         lp_clk_div, dsi_fclk_hsdiv);
3983         }
3984
3985         if (!hbp_blanking_mode) {
3986                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3987                                         enter_hs_mode_lat, exit_hs_mode_lat,
3988                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3989
3990                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3991                                         enter_hs_mode_lat, exit_hs_mode_lat,
3992                                         lp_clk_div, dsi_fclk_hsdiv);
3993         }
3994
3995         if (!blanking_mode) {
3996                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3997                                         enter_hs_mode_lat, exit_hs_mode_lat,
3998                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3999
4000                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
4001                                         enter_hs_mode_lat, exit_hs_mode_lat,
4002                                         lp_clk_div, dsi_fclk_hsdiv);
4003         }
4004
4005         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
4006                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
4007                 bl_interleave_hs);
4008
4009         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
4010                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
4011                 bl_interleave_lp);
4012
4013         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
4014         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
4015         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
4016         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
4017         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
4018
4019         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
4020         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
4021         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
4022         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
4023         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
4024
4025         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
4026         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
4027         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
4028         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
4029 }
4030
4031 static int dsi_proto_config(struct platform_device *dsidev)
4032 {
4033         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4034         u32 r;
4035         int buswidth = 0;
4036
4037         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
4038                         DSI_FIFO_SIZE_32,
4039                         DSI_FIFO_SIZE_32,
4040                         DSI_FIFO_SIZE_32);
4041
4042         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
4043                         DSI_FIFO_SIZE_32,
4044                         DSI_FIFO_SIZE_32,
4045                         DSI_FIFO_SIZE_32);
4046
4047         /* XXX what values for the timeouts? */
4048         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
4049         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
4050         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
4051         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
4052
4053         switch (dsi_get_pixel_size(dsi->pix_fmt)) {
4054         case 16:
4055                 buswidth = 0;
4056                 break;
4057         case 18:
4058                 buswidth = 1;
4059                 break;
4060         case 24:
4061                 buswidth = 2;
4062                 break;
4063         default:
4064                 BUG();
4065                 return -EINVAL;
4066         }
4067
4068         r = dsi_read_reg(dsidev, DSI_CTRL);
4069         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
4070         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
4071         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
4072         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
4073         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
4074         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
4075         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
4076         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
4077         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
4078                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
4079                 /* DCS_CMD_CODE, 1=start, 0=continue */
4080                 r = FLD_MOD(r, 0, 25, 25);
4081         }
4082
4083         dsi_write_reg(dsidev, DSI_CTRL, r);
4084
4085         dsi_config_vp_num_line_buffers(dsidev);
4086
4087         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4088                 dsi_config_vp_sync_events(dsidev);
4089                 dsi_config_blanking_modes(dsidev);
4090                 dsi_config_cmd_mode_interleaving(dsidev);
4091         }
4092
4093         dsi_vc_initial_config(dsidev, 0);
4094         dsi_vc_initial_config(dsidev, 1);
4095         dsi_vc_initial_config(dsidev, 2);
4096         dsi_vc_initial_config(dsidev, 3);
4097
4098         return 0;
4099 }
4100
4101 static void dsi_proto_timings(struct platform_device *dsidev)
4102 {
4103         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4104         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
4105         unsigned tclk_pre, tclk_post;
4106         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
4107         unsigned ths_trail, ths_exit;
4108         unsigned ddr_clk_pre, ddr_clk_post;
4109         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
4110         unsigned ths_eot;
4111         int ndl = dsi->num_lanes_used - 1;
4112         u32 r;
4113
4114         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
4115         ths_prepare = FLD_GET(r, 31, 24);
4116         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
4117         ths_zero = ths_prepare_ths_zero - ths_prepare;
4118         ths_trail = FLD_GET(r, 15, 8);
4119         ths_exit = FLD_GET(r, 7, 0);
4120
4121         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
4122         tlpx = FLD_GET(r, 20, 16) * 2;
4123         tclk_trail = FLD_GET(r, 15, 8);
4124         tclk_zero = FLD_GET(r, 7, 0);
4125
4126         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
4127         tclk_prepare = FLD_GET(r, 7, 0);
4128
4129         /* min 8*UI */
4130         tclk_pre = 20;
4131         /* min 60ns + 52*UI */
4132         tclk_post = ns2ddr(dsidev, 60) + 26;
4133
4134         ths_eot = DIV_ROUND_UP(4, ndl);
4135
4136         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4137                         4);
4138         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
4139
4140         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
4141         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
4142
4143         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
4144         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
4145         r = FLD_MOD(r, ddr_clk_post, 7, 0);
4146         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
4147
4148         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
4149                         ddr_clk_pre,
4150                         ddr_clk_post);
4151
4152         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
4153                 DIV_ROUND_UP(ths_prepare, 4) +
4154                 DIV_ROUND_UP(ths_zero + 3, 4);
4155
4156         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
4157
4158         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
4159                 FLD_VAL(exit_hs_mode_lat, 15, 0);
4160         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
4161
4162         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4163                         enter_hs_mode_lat, exit_hs_mode_lat);
4164
4165          if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4166                 /* TODO: Implement a video mode check_timings function */
4167                 int hsa = dsi->vm_timings.hsa;
4168                 int hfp = dsi->vm_timings.hfp;
4169                 int hbp = dsi->vm_timings.hbp;
4170                 int vsa = dsi->vm_timings.vsa;
4171                 int vfp = dsi->vm_timings.vfp;
4172                 int vbp = dsi->vm_timings.vbp;
4173                 int window_sync = dsi->vm_timings.window_sync;
4174                 bool hsync_end = dsi->vm_timings.vp_hsync_end;
4175                 struct omap_video_timings *timings = &dsi->timings;
4176                 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4177                 int tl, t_he, width_bytes;
4178
4179                 t_he = hsync_end ?
4180                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4181
4182                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4183
4184                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4185                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4186                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4187
4188                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4189                         hfp, hsync_end ? hsa : 0, tl);
4190                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4191                         vsa, timings->y_res);
4192
4193                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4194                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
4195                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
4196                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
4197                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4198
4199                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4200                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
4201                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
4202                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
4203                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
4204                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4205
4206                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4207                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
4208                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
4209                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4210         }
4211 }
4212
4213 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4214                 const struct omap_dsi_pin_config *pin_cfg)
4215 {
4216         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4217         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4218         int num_pins;
4219         const int *pins;
4220         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4221         int num_lanes;
4222         int i;
4223
4224         static const enum dsi_lane_function functions[] = {
4225                 DSI_LANE_CLK,
4226                 DSI_LANE_DATA1,
4227                 DSI_LANE_DATA2,
4228                 DSI_LANE_DATA3,
4229                 DSI_LANE_DATA4,
4230         };
4231
4232         num_pins = pin_cfg->num_pins;
4233         pins = pin_cfg->pins;
4234
4235         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4236                         || num_pins % 2 != 0)
4237                 return -EINVAL;
4238
4239         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4240                 lanes[i].function = DSI_LANE_UNUSED;
4241
4242         num_lanes = 0;
4243
4244         for (i = 0; i < num_pins; i += 2) {
4245                 u8 lane, pol;
4246                 int dx, dy;
4247
4248                 dx = pins[i];
4249                 dy = pins[i + 1];
4250
4251                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4252                         return -EINVAL;
4253
4254                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4255                         return -EINVAL;
4256
4257                 if (dx & 1) {
4258                         if (dy != dx - 1)
4259                                 return -EINVAL;
4260                         pol = 1;
4261                 } else {
4262                         if (dy != dx + 1)
4263                                 return -EINVAL;
4264                         pol = 0;
4265                 }
4266
4267                 lane = dx / 2;
4268
4269                 lanes[lane].function = functions[i / 2];
4270                 lanes[lane].polarity = pol;
4271                 num_lanes++;
4272         }
4273
4274         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4275         dsi->num_lanes_used = num_lanes;
4276
4277         return 0;
4278 }
4279 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4280
4281 static int dsi_set_clocks(struct omap_dss_device *dssdev,
4282                 unsigned long ddr_clk, unsigned long lp_clk)
4283 {
4284         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4285         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4286         struct dsi_clock_info cinfo;
4287         struct dispc_clock_info dispc_cinfo;
4288         unsigned lp_clk_div;
4289         unsigned long dsi_fclk;
4290         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4291         unsigned long pck;
4292         int r;
4293
4294         DSSDBG("Setting DSI clocks: ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
4295
4296         /* Calculate PLL output clock */
4297         r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
4298         if (r)
4299                 goto err;
4300
4301         /* Calculate PLL's DSI clock */
4302         dsi_pll_calc_dsi_fck(dsidev, &cinfo);
4303
4304         /* Calculate PLL's DISPC clock and pck & lck divs */
4305         pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
4306         DSSDBG("finding dispc dividers for pck %lu\n", pck);
4307         r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
4308         if (r)
4309                 goto err;
4310
4311         /* Calculate LP clock */
4312         dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
4313         lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
4314
4315         dsi->user_dsi_cinfo.regn = cinfo.regn;
4316         dsi->user_dsi_cinfo.regm = cinfo.regm;
4317         dsi->user_dsi_cinfo.regm_dispc = cinfo.regm_dispc;
4318         dsi->user_dsi_cinfo.regm_dsi = cinfo.regm_dsi;
4319
4320         dsi->user_dsi_cinfo.lp_clk_div = lp_clk_div;
4321
4322         dsi->user_dispc_cinfo.lck_div = dispc_cinfo.lck_div;
4323         dsi->user_dispc_cinfo.pck_div = dispc_cinfo.pck_div;
4324
4325         dsi->user_dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
4326
4327         dsi->user_lcd_clk_src =
4328                 dsi->module_id == 0 ?
4329                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4330                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
4331
4332         dsi->user_dsi_fclk_src =
4333                 dsi->module_id == 0 ?
4334                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4335                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI;
4336
4337         return 0;
4338 err:
4339         return r;
4340 }
4341
4342 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4343 {
4344         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4345         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4346         struct omap_overlay_manager *mgr = dsi->output.manager;
4347         int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4348         struct omap_dss_output *out = &dsi->output;
4349         u8 data_type;
4350         u16 word_count;
4351         int r;
4352
4353         if (out == NULL || out->manager == NULL) {
4354                 DSSERR("failed to enable display: no output/manager\n");
4355                 return -ENODEV;
4356         }
4357
4358         r = dsi_display_init_dispc(dsidev, mgr);
4359         if (r)
4360                 goto err_init_dispc;
4361
4362         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4363                 switch (dsi->pix_fmt) {
4364                 case OMAP_DSS_DSI_FMT_RGB888:
4365                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4366                         break;
4367                 case OMAP_DSS_DSI_FMT_RGB666:
4368                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4369                         break;
4370                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4371                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4372                         break;
4373                 case OMAP_DSS_DSI_FMT_RGB565:
4374                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4375                         break;
4376                 default:
4377                         r = -EINVAL;
4378                         goto err_pix_fmt;
4379                 };
4380
4381                 dsi_if_enable(dsidev, false);
4382                 dsi_vc_enable(dsidev, channel, false);
4383
4384                 /* MODE, 1 = video mode */
4385                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4386
4387                 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4388
4389                 dsi_vc_write_long_header(dsidev, channel, data_type,
4390                                 word_count, 0);
4391
4392                 dsi_vc_enable(dsidev, channel, true);
4393                 dsi_if_enable(dsidev, true);
4394         }
4395
4396         r = dss_mgr_enable(mgr);
4397         if (r)
4398                 goto err_mgr_enable;
4399
4400         return 0;
4401
4402 err_mgr_enable:
4403         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4404                 dsi_if_enable(dsidev, false);
4405                 dsi_vc_enable(dsidev, channel, false);
4406         }
4407 err_pix_fmt:
4408         dsi_display_uninit_dispc(dsidev, mgr);
4409 err_init_dispc:
4410         return r;
4411 }
4412 EXPORT_SYMBOL(dsi_enable_video_output);
4413
4414 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4415 {
4416         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4417         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4418         struct omap_overlay_manager *mgr = dsi->output.manager;
4419
4420         if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4421                 dsi_if_enable(dsidev, false);
4422                 dsi_vc_enable(dsidev, channel, false);
4423
4424                 /* MODE, 0 = command mode */
4425                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4426
4427                 dsi_vc_enable(dsidev, channel, true);
4428                 dsi_if_enable(dsidev, true);
4429         }
4430
4431         dss_mgr_disable(mgr);
4432
4433         dsi_display_uninit_dispc(dsidev, mgr);
4434 }
4435 EXPORT_SYMBOL(dsi_disable_video_output);
4436
4437 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4438 {
4439         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4440         struct omap_overlay_manager *mgr = dsi->output.manager;
4441         unsigned bytespp;
4442         unsigned bytespl;
4443         unsigned bytespf;
4444         unsigned total_len;
4445         unsigned packet_payload;
4446         unsigned packet_len;
4447         u32 l;
4448         int r;
4449         const unsigned channel = dsi->update_channel;
4450         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4451         u16 w = dsi->timings.x_res;
4452         u16 h = dsi->timings.y_res;
4453
4454         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4455
4456         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4457
4458         bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4459         bytespl = w * bytespp;
4460         bytespf = bytespl * h;
4461
4462         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4463          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4464
4465         if (bytespf < line_buf_size)
4466                 packet_payload = bytespf;
4467         else
4468                 packet_payload = (line_buf_size) / bytespl * bytespl;
4469
4470         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4471         total_len = (bytespf / packet_payload) * packet_len;
4472
4473         if (bytespf % packet_payload)
4474                 total_len += (bytespf % packet_payload) + 1;
4475
4476         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4477         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4478
4479         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4480                 packet_len, 0);
4481
4482         if (dsi->te_enabled)
4483                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4484         else
4485                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4486         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4487
4488         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4489          * because DSS interrupts are not capable of waking up the CPU and the
4490          * framedone interrupt could be delayed for quite a long time. I think
4491          * the same goes for any DSS interrupts, but for some reason I have not
4492          * seen the problem anywhere else than here.
4493          */
4494         dispc_disable_sidle();
4495
4496         dsi_perf_mark_start(dsidev);
4497
4498         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4499                 msecs_to_jiffies(250));
4500         BUG_ON(r == 0);
4501
4502         dss_mgr_set_timings(mgr, &dsi->timings);
4503
4504         dss_mgr_start_update(mgr);
4505
4506         if (dsi->te_enabled) {
4507                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4508                  * for TE is longer than the timer allows */
4509                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4510
4511                 dsi_vc_send_bta(dsidev, channel);
4512
4513 #ifdef DSI_CATCH_MISSING_TE
4514                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4515 #endif
4516         }
4517 }
4518
4519 #ifdef DSI_CATCH_MISSING_TE
4520 static void dsi_te_timeout(unsigned long arg)
4521 {
4522         DSSERR("TE not received for 250ms!\n");
4523 }
4524 #endif
4525
4526 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4527 {
4528         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4529
4530         /* SIDLEMODE back to smart-idle */
4531         dispc_enable_sidle();
4532
4533         if (dsi->te_enabled) {
4534                 /* enable LP_RX_TO again after the TE */
4535                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4536         }
4537
4538         dsi->framedone_callback(error, dsi->framedone_data);
4539
4540         if (!error)
4541                 dsi_perf_show(dsidev, "DISPC");
4542 }
4543
4544 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4545 {
4546         struct dsi_data *dsi = container_of(work, struct dsi_data,
4547                         framedone_timeout_work.work);
4548         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4549          * 250ms which would conflict with this timeout work. What should be
4550          * done is first cancel the transfer on the HW, and then cancel the
4551          * possibly scheduled framedone work. However, cancelling the transfer
4552          * on the HW is buggy, and would probably require resetting the whole
4553          * DSI */
4554
4555         DSSERR("Framedone not received for 250ms!\n");
4556
4557         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4558 }
4559
4560 static void dsi_framedone_irq_callback(void *data)
4561 {
4562         struct platform_device *dsidev = (struct platform_device *) data;
4563         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4564
4565         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4566          * turns itself off. However, DSI still has the pixels in its buffers,
4567          * and is sending the data.
4568          */
4569
4570         cancel_delayed_work(&dsi->framedone_timeout_work);
4571
4572         dsi_handle_framedone(dsidev, 0);
4573 }
4574
4575 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4576                 void (*callback)(int, void *), void *data)
4577 {
4578         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4579         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4580         u16 dw, dh;
4581
4582         dsi_perf_mark_setup(dsidev);
4583
4584         dsi->update_channel = channel;
4585
4586         dsi->framedone_callback = callback;
4587         dsi->framedone_data = data;
4588
4589         dw = dsi->timings.x_res;
4590         dh = dsi->timings.y_res;
4591
4592 #ifdef DEBUG
4593         dsi->update_bytes = dw * dh *
4594                 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4595 #endif
4596         dsi_update_screen_dispc(dsidev);
4597
4598         return 0;
4599 }
4600 EXPORT_SYMBOL(omap_dsi_update);
4601
4602 /* Display funcs */
4603
4604 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4605 {
4606         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4607         struct dispc_clock_info dispc_cinfo;
4608         int r;
4609         unsigned long fck;
4610
4611         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4612
4613         dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4614         dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4615
4616         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4617         if (r) {
4618                 DSSERR("Failed to calc dispc clocks\n");
4619                 return r;
4620         }
4621
4622         dsi->mgr_config.clock_info = dispc_cinfo;
4623
4624         return 0;
4625 }
4626
4627 static int dsi_display_init_dispc(struct platform_device *dsidev,
4628                 struct omap_overlay_manager *mgr)
4629 {
4630         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4631         int r;
4632
4633         dss_select_lcd_clk_source(mgr->id, dsi->user_lcd_clk_src);
4634
4635         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4636                 dsi->timings.hsw = 1;
4637                 dsi->timings.hfp = 1;
4638                 dsi->timings.hbp = 1;
4639                 dsi->timings.vsw = 1;
4640                 dsi->timings.vfp = 0;
4641                 dsi->timings.vbp = 0;
4642
4643                 r = dss_mgr_register_framedone_handler(mgr,
4644                                 dsi_framedone_irq_callback, dsidev);
4645                 if (r) {
4646                         DSSERR("can't register FRAMEDONE handler\n");
4647                         goto err;
4648                 }
4649
4650                 dsi->mgr_config.stallmode = true;
4651                 dsi->mgr_config.fifohandcheck = true;
4652         } else {
4653                 dsi->mgr_config.stallmode = false;
4654                 dsi->mgr_config.fifohandcheck = false;
4655         }
4656
4657         /*
4658          * override interlace, logic level and edge related parameters in
4659          * omap_video_timings with default values
4660          */
4661         dsi->timings.interlace = false;
4662         dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4663         dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4664         dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4665         dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4666         dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4667
4668         dss_mgr_set_timings(mgr, &dsi->timings);
4669
4670         r = dsi_configure_dispc_clocks(dsidev);
4671         if (r)
4672                 goto err1;
4673
4674         dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4675         dsi->mgr_config.video_port_width =
4676                         dsi_get_pixel_size(dsi->pix_fmt);
4677         dsi->mgr_config.lcden_sig_polarity = 0;
4678
4679         dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4680
4681         return 0;
4682 err1:
4683         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4684                 dss_mgr_unregister_framedone_handler(mgr,
4685                                 dsi_framedone_irq_callback, dsidev);
4686 err:
4687         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4688         return r;
4689 }
4690
4691 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4692                 struct omap_overlay_manager *mgr)
4693 {
4694         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4695
4696         if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4697                 dss_mgr_unregister_framedone_handler(mgr,
4698                                 dsi_framedone_irq_callback, dsidev);
4699
4700         dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4701 }
4702
4703 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4704 {
4705         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4706         struct dsi_clock_info cinfo;
4707         int r;
4708
4709         cinfo = dsi->user_dsi_cinfo;
4710
4711         r = dsi_calc_clock_rates(dsidev, &cinfo);
4712         if (r) {
4713                 DSSERR("Failed to calc dsi clocks\n");
4714                 return r;
4715         }
4716
4717         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4718         if (r) {
4719                 DSSERR("Failed to set dsi clocks\n");
4720                 return r;
4721         }
4722
4723         return 0;
4724 }
4725
4726 static int dsi_display_init_dsi(struct platform_device *dsidev)
4727 {
4728         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4729         int r;
4730
4731         r = dsi_pll_init(dsidev, true, true);
4732         if (r)
4733                 goto err0;
4734
4735         r = dsi_configure_dsi_clocks(dsidev);
4736         if (r)
4737                 goto err1;
4738
4739         dss_select_dsi_clk_source(dsi->module_id, dsi->user_dsi_fclk_src);
4740
4741         DSSDBG("PLL OK\n");
4742
4743         r = dsi_cio_init(dsidev);
4744         if (r)
4745                 goto err2;
4746
4747         _dsi_print_reset_status(dsidev);
4748
4749         dsi_proto_timings(dsidev);
4750         dsi_set_lp_clk_divisor(dsidev);
4751
4752         if (1)
4753                 _dsi_print_reset_status(dsidev);
4754
4755         r = dsi_proto_config(dsidev);
4756         if (r)
4757                 goto err3;
4758
4759         /* enable interface */
4760         dsi_vc_enable(dsidev, 0, 1);
4761         dsi_vc_enable(dsidev, 1, 1);
4762         dsi_vc_enable(dsidev, 2, 1);
4763         dsi_vc_enable(dsidev, 3, 1);
4764         dsi_if_enable(dsidev, 1);
4765         dsi_force_tx_stop_mode_io(dsidev);
4766
4767         return 0;
4768 err3:
4769         dsi_cio_uninit(dsidev);
4770 err2:
4771         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4772 err1:
4773         dsi_pll_uninit(dsidev, true);
4774 err0:
4775         return r;
4776 }
4777
4778 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4779                 bool disconnect_lanes, bool enter_ulps)
4780 {
4781         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4782
4783         if (enter_ulps && !dsi->ulps_enabled)
4784                 dsi_enter_ulps(dsidev);
4785
4786         /* disable interface */
4787         dsi_if_enable(dsidev, 0);
4788         dsi_vc_enable(dsidev, 0, 0);
4789         dsi_vc_enable(dsidev, 1, 0);
4790         dsi_vc_enable(dsidev, 2, 0);
4791         dsi_vc_enable(dsidev, 3, 0);
4792
4793         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4794         dsi_cio_uninit(dsidev);
4795         dsi_pll_uninit(dsidev, disconnect_lanes);
4796 }
4797
4798 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4799 {
4800         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4801         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4802         int r = 0;
4803
4804         DSSDBG("dsi_display_enable\n");
4805
4806         WARN_ON(!dsi_bus_is_locked(dsidev));
4807
4808         mutex_lock(&dsi->lock);
4809
4810         r = omap_dss_start_device(dssdev);
4811         if (r) {
4812                 DSSERR("failed to start device\n");
4813                 goto err_start_dev;
4814         }
4815
4816         r = dsi_runtime_get(dsidev);
4817         if (r)
4818                 goto err_get_dsi;
4819
4820         dsi_enable_pll_clock(dsidev, 1);
4821
4822         _dsi_initialize_irq(dsidev);
4823
4824         r = dsi_display_init_dsi(dsidev);
4825         if (r)
4826                 goto err_init_dsi;
4827
4828         mutex_unlock(&dsi->lock);
4829
4830         return 0;
4831
4832 err_init_dsi:
4833         dsi_enable_pll_clock(dsidev, 0);
4834         dsi_runtime_put(dsidev);
4835 err_get_dsi:
4836         omap_dss_stop_device(dssdev);
4837 err_start_dev:
4838         mutex_unlock(&dsi->lock);
4839         DSSDBG("dsi_display_enable FAILED\n");
4840         return r;
4841 }
4842 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4843
4844 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4845                 bool disconnect_lanes, bool enter_ulps)
4846 {
4847         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4848         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4849
4850         DSSDBG("dsi_display_disable\n");
4851
4852         WARN_ON(!dsi_bus_is_locked(dsidev));
4853
4854         mutex_lock(&dsi->lock);
4855
4856         dsi_sync_vc(dsidev, 0);
4857         dsi_sync_vc(dsidev, 1);
4858         dsi_sync_vc(dsidev, 2);
4859         dsi_sync_vc(dsidev, 3);
4860
4861         dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4862
4863         dsi_runtime_put(dsidev);
4864         dsi_enable_pll_clock(dsidev, 0);
4865
4866         omap_dss_stop_device(dssdev);
4867
4868         mutex_unlock(&dsi->lock);
4869 }
4870 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4871
4872 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4873 {
4874         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4875         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4876
4877         dsi->te_enabled = enable;
4878         return 0;
4879 }
4880 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4881
4882 int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
4883                 const struct omap_dss_dsi_config *config)
4884 {
4885         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4886         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4887
4888         mutex_lock(&dsi->lock);
4889
4890         dsi->timings = *config->timings;
4891         dsi->vm_timings = *config->vm_timings;
4892         dsi->pix_fmt = config->pixel_format;
4893         dsi->mode = config->mode;
4894
4895         dsi_set_clocks(dssdev, config->hs_clk, config->lp_clk);
4896
4897         mutex_unlock(&dsi->lock);
4898
4899         return 0;
4900 }
4901 EXPORT_SYMBOL(omapdss_dsi_set_config);
4902
4903 /*
4904  * Return a hardcoded channel for the DSI output. This should work for
4905  * current use cases, but this can be later expanded to either resolve
4906  * the channel in some more dynamic manner, or get the channel as a user
4907  * parameter.
4908  */
4909 static enum omap_channel dsi_get_channel(int module_id)
4910 {
4911         switch (omapdss_get_version()) {
4912         case OMAPDSS_VER_OMAP24xx:
4913                 DSSWARN("DSI not supported\n");
4914                 return OMAP_DSS_CHANNEL_LCD;
4915
4916         case OMAPDSS_VER_OMAP34xx_ES1:
4917         case OMAPDSS_VER_OMAP34xx_ES3:
4918         case OMAPDSS_VER_OMAP3630:
4919         case OMAPDSS_VER_AM35xx:
4920                 return OMAP_DSS_CHANNEL_LCD;
4921
4922         case OMAPDSS_VER_OMAP4430_ES1:
4923         case OMAPDSS_VER_OMAP4430_ES2:
4924         case OMAPDSS_VER_OMAP4:
4925                 switch (module_id) {
4926                 case 0:
4927                         return OMAP_DSS_CHANNEL_LCD;
4928                 case 1:
4929                         return OMAP_DSS_CHANNEL_LCD2;
4930                 default:
4931                         DSSWARN("unsupported module id\n");
4932                         return OMAP_DSS_CHANNEL_LCD;
4933                 }
4934
4935         case OMAPDSS_VER_OMAP5:
4936                 switch (module_id) {
4937                 case 0:
4938                         return OMAP_DSS_CHANNEL_LCD;
4939                 case 1:
4940                         return OMAP_DSS_CHANNEL_LCD3;
4941                 default:
4942                         DSSWARN("unsupported module id\n");
4943                         return OMAP_DSS_CHANNEL_LCD;
4944                 }
4945
4946         default:
4947                 DSSWARN("unsupported DSS version\n");
4948                 return OMAP_DSS_CHANNEL_LCD;
4949         }
4950 }
4951
4952 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4953 {
4954         struct platform_device *dsidev =
4955                         dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
4956         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4957
4958         DSSDBG("DSI init\n");
4959
4960         if (dsi->vdds_dsi_reg == NULL) {
4961                 struct regulator *vdds_dsi;
4962
4963                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4964
4965                 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
4966                 if (IS_ERR(vdds_dsi))
4967                         vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
4968
4969                 if (IS_ERR(vdds_dsi)) {
4970                         DSSERR("can't get VDDS_DSI regulator\n");
4971                         return PTR_ERR(vdds_dsi);
4972                 }
4973
4974                 dsi->vdds_dsi_reg = vdds_dsi;
4975         }
4976
4977         return 0;
4978 }
4979
4980 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4981 {
4982         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4983         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4984         int i;
4985
4986         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4987                 if (!dsi->vc[i].dssdev) {
4988                         dsi->vc[i].dssdev = dssdev;
4989                         *channel = i;
4990                         return 0;
4991                 }
4992         }
4993
4994         DSSERR("cannot get VC for display %s", dssdev->name);
4995         return -ENOSPC;
4996 }
4997 EXPORT_SYMBOL(omap_dsi_request_vc);
4998
4999 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5000 {
5001         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5002         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5003
5004         if (vc_id < 0 || vc_id > 3) {
5005                 DSSERR("VC ID out of range\n");
5006                 return -EINVAL;
5007         }
5008
5009         if (channel < 0 || channel > 3) {
5010                 DSSERR("Virtual Channel out of range\n");
5011                 return -EINVAL;
5012         }
5013
5014         if (dsi->vc[channel].dssdev != dssdev) {
5015                 DSSERR("Virtual Channel not allocated to display %s\n",
5016                         dssdev->name);
5017                 return -EINVAL;
5018         }
5019
5020         dsi->vc[channel].vc_id = vc_id;
5021
5022         return 0;
5023 }
5024 EXPORT_SYMBOL(omap_dsi_set_vc_id);
5025
5026 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5027 {
5028         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5029         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5030
5031         if ((channel >= 0 && channel <= 3) &&
5032                 dsi->vc[channel].dssdev == dssdev) {
5033                 dsi->vc[channel].dssdev = NULL;
5034                 dsi->vc[channel].vc_id = 0;
5035         }
5036 }
5037 EXPORT_SYMBOL(omap_dsi_release_vc);
5038
5039 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5040 {
5041         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5042                 DSSERR("%s (%s) not active\n",
5043                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5044                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5045 }
5046
5047 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5048 {
5049         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5050                 DSSERR("%s (%s) not active\n",
5051                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5052                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5053 }
5054
5055 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5056 {
5057         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5058
5059         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5060         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5061         dsi->regm_dispc_max =
5062                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5063         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5064         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5065         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5066         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5067 }
5068
5069 static int dsi_get_clocks(struct platform_device *dsidev)
5070 {
5071         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5072         struct clk *clk;
5073
5074         clk = clk_get(&dsidev->dev, "fck");
5075         if (IS_ERR(clk)) {
5076                 DSSERR("can't get fck\n");
5077                 return PTR_ERR(clk);
5078         }
5079
5080         dsi->dss_clk = clk;
5081
5082         clk = clk_get(&dsidev->dev, "sys_clk");
5083         if (IS_ERR(clk)) {
5084                 DSSERR("can't get sys_clk\n");
5085                 clk_put(dsi->dss_clk);
5086                 dsi->dss_clk = NULL;
5087                 return PTR_ERR(clk);
5088         }
5089
5090         dsi->sys_clk = clk;
5091
5092         return 0;
5093 }
5094
5095 static void dsi_put_clocks(struct platform_device *dsidev)
5096 {
5097         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5098
5099         if (dsi->dss_clk)
5100                 clk_put(dsi->dss_clk);
5101         if (dsi->sys_clk)
5102                 clk_put(dsi->sys_clk);
5103 }
5104
5105 static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev)
5106 {
5107         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5108         struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5109         const char *def_disp_name = omapdss_get_default_display_name();
5110         struct omap_dss_device *def_dssdev;
5111         int i;
5112
5113         def_dssdev = NULL;
5114
5115         for (i = 0; i < pdata->num_devices; ++i) {
5116                 struct omap_dss_device *dssdev = pdata->devices[i];
5117
5118                 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5119                         continue;
5120
5121                 if (dssdev->phy.dsi.module != dsi->module_id)
5122                         continue;
5123
5124                 if (def_dssdev == NULL)
5125                         def_dssdev = dssdev;
5126
5127                 if (def_disp_name != NULL &&
5128                                 strcmp(dssdev->name, def_disp_name) == 0) {
5129                         def_dssdev = dssdev;
5130                         break;
5131                 }
5132         }
5133
5134         return def_dssdev;
5135 }
5136
5137 static void __init dsi_probe_pdata(struct platform_device *dsidev)
5138 {
5139         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5140         struct omap_dss_device *plat_dssdev;
5141         struct omap_dss_device *dssdev;
5142         int r;
5143
5144         plat_dssdev = dsi_find_dssdev(dsidev);
5145
5146         if (!plat_dssdev)
5147                 return;
5148
5149         dssdev = dss_alloc_and_init_device(&dsidev->dev);
5150         if (!dssdev)
5151                 return;
5152
5153         dss_copy_device_pdata(dssdev, plat_dssdev);
5154
5155         r = dsi_init_display(dssdev);
5156         if (r) {
5157                 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5158                 dss_put_device(dssdev);
5159                 return;
5160         }
5161
5162         r = omapdss_output_set_device(&dsi->output, dssdev);
5163         if (r) {
5164                 DSSERR("failed to connect output to new device: %s\n",
5165                                 dssdev->name);
5166                 dss_put_device(dssdev);
5167                 return;
5168         }
5169
5170         r = dss_add_device(dssdev);
5171         if (r) {
5172                 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5173                 omapdss_output_unset_device(&dsi->output);
5174                 dss_put_device(dssdev);
5175                 return;
5176         }
5177 }
5178
5179 static void __init dsi_init_output(struct platform_device *dsidev)
5180 {
5181         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5182         struct omap_dss_output *out = &dsi->output;
5183
5184         out->pdev = dsidev;
5185         out->id = dsi->module_id == 0 ?
5186                         OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5187
5188         out->type = OMAP_DISPLAY_TYPE_DSI;
5189         out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5190         out->dispc_channel = dsi_get_channel(dsi->module_id);
5191
5192         dss_register_output(out);
5193 }
5194
5195 static void __exit dsi_uninit_output(struct platform_device *dsidev)
5196 {
5197         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5198         struct omap_dss_output *out = &dsi->output;
5199
5200         dss_unregister_output(out);
5201 }
5202
5203 /* DSI1 HW IP initialisation */
5204 static int __init omap_dsihw_probe(struct platform_device *dsidev)
5205 {
5206         u32 rev;
5207         int r, i;
5208         struct resource *dsi_mem;
5209         struct dsi_data *dsi;
5210
5211         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5212         if (!dsi)
5213                 return -ENOMEM;
5214
5215         dsi->module_id = dsidev->id;
5216         dsi->pdev = dsidev;
5217         dev_set_drvdata(&dsidev->dev, dsi);
5218
5219         spin_lock_init(&dsi->irq_lock);
5220         spin_lock_init(&dsi->errors_lock);
5221         dsi->errors = 0;
5222
5223 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5224         spin_lock_init(&dsi->irq_stats_lock);
5225         dsi->irq_stats.last_reset = jiffies;
5226 #endif
5227
5228         mutex_init(&dsi->lock);
5229         sema_init(&dsi->bus_lock, 1);
5230
5231         INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5232                              dsi_framedone_timeout_work_callback);
5233
5234 #ifdef DSI_CATCH_MISSING_TE
5235         init_timer(&dsi->te_timer);
5236         dsi->te_timer.function = dsi_te_timeout;
5237         dsi->te_timer.data = 0;
5238 #endif
5239         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5240         if (!dsi_mem) {
5241                 DSSERR("can't get IORESOURCE_MEM DSI\n");
5242                 return -EINVAL;
5243         }
5244
5245         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5246                                  resource_size(dsi_mem));
5247         if (!dsi->base) {
5248                 DSSERR("can't ioremap DSI\n");
5249                 return -ENOMEM;
5250         }
5251
5252         dsi->irq = platform_get_irq(dsi->pdev, 0);
5253         if (dsi->irq < 0) {
5254                 DSSERR("platform_get_irq failed\n");
5255                 return -ENODEV;
5256         }
5257
5258         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5259                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5260         if (r < 0) {
5261                 DSSERR("request_irq failed\n");
5262                 return r;
5263         }
5264
5265         /* DSI VCs initialization */
5266         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5267                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5268                 dsi->vc[i].dssdev = NULL;
5269                 dsi->vc[i].vc_id = 0;
5270         }
5271
5272         dsi_calc_clock_param_ranges(dsidev);
5273
5274         r = dsi_get_clocks(dsidev);
5275         if (r)
5276                 return r;
5277
5278         pm_runtime_enable(&dsidev->dev);
5279
5280         r = dsi_runtime_get(dsidev);
5281         if (r)
5282                 goto err_runtime_get;
5283
5284         rev = dsi_read_reg(dsidev, DSI_REVISION);
5285         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5286                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5287
5288         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5289          * of data to 3 by default */
5290         if (dss_has_feature(FEAT_DSI_GNQ))
5291                 /* NB_DATA_LANES */
5292                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5293         else
5294                 dsi->num_lanes_supported = 3;
5295
5296         dsi_init_output(dsidev);
5297
5298         dsi_probe_pdata(dsidev);
5299
5300         dsi_runtime_put(dsidev);
5301
5302         if (dsi->module_id == 0)
5303                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5304         else if (dsi->module_id == 1)
5305                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5306
5307 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5308         if (dsi->module_id == 0)
5309                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5310         else if (dsi->module_id == 1)
5311                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5312 #endif
5313         return 0;
5314
5315 err_runtime_get:
5316         pm_runtime_disable(&dsidev->dev);
5317         dsi_put_clocks(dsidev);
5318         return r;
5319 }
5320
5321 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5322 {
5323         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5324
5325         WARN_ON(dsi->scp_clk_refcount > 0);
5326
5327         dss_unregister_child_devices(&dsidev->dev);
5328
5329         dsi_uninit_output(dsidev);
5330
5331         pm_runtime_disable(&dsidev->dev);
5332
5333         dsi_put_clocks(dsidev);
5334
5335         if (dsi->vdds_dsi_reg != NULL) {
5336                 if (dsi->vdds_dsi_enabled) {
5337                         regulator_disable(dsi->vdds_dsi_reg);
5338                         dsi->vdds_dsi_enabled = false;
5339                 }
5340
5341                 regulator_put(dsi->vdds_dsi_reg);
5342                 dsi->vdds_dsi_reg = NULL;
5343         }
5344
5345         return 0;
5346 }
5347
5348 static int dsi_runtime_suspend(struct device *dev)
5349 {
5350         dispc_runtime_put();
5351
5352         return 0;
5353 }
5354
5355 static int dsi_runtime_resume(struct device *dev)
5356 {
5357         int r;
5358
5359         r = dispc_runtime_get();
5360         if (r)
5361                 return r;
5362
5363         return 0;
5364 }
5365
5366 static const struct dev_pm_ops dsi_pm_ops = {
5367         .runtime_suspend = dsi_runtime_suspend,
5368         .runtime_resume = dsi_runtime_resume,
5369 };
5370
5371 static struct platform_driver omap_dsihw_driver = {
5372         .remove         = __exit_p(omap_dsihw_remove),
5373         .driver         = {
5374                 .name   = "omapdss_dsi",
5375                 .owner  = THIS_MODULE,
5376                 .pm     = &dsi_pm_ops,
5377         },
5378 };
5379
5380 int __init dsi_init_platform_driver(void)
5381 {
5382         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
5383 }
5384
5385 void __exit dsi_uninit_platform_driver(void)
5386 {
5387         platform_driver_unregister(&omap_dsihw_driver);
5388 }