2 * linux/drivers/video/omap2/dss/dispc.h
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef __OMAP2_DISPC_REG_H
22 #define __OMAP2_DISPC_REG_H
24 /* DISPC common registers */
25 #define DISPC_REVISION 0x0000
26 #define DISPC_SYSCONFIG 0x0010
27 #define DISPC_SYSSTATUS 0x0014
28 #define DISPC_IRQSTATUS 0x0018
29 #define DISPC_IRQENABLE 0x001C
30 #define DISPC_CONTROL 0x0040
31 #define DISPC_CONFIG 0x0044
32 #define DISPC_CAPABLE 0x0048
33 #define DISPC_LINE_STATUS 0x005C
34 #define DISPC_LINE_NUMBER 0x0060
35 #define DISPC_GLOBAL_ALPHA 0x0074
36 #define DISPC_CONTROL2 0x0238
37 #define DISPC_CONFIG2 0x0620
38 #define DISPC_DIVISOR 0x0804
40 /* DISPC overlay registers */
41 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
43 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
45 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
46 DISPC_BA0_UV_OFFSET(n))
47 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
48 DISPC_BA1_UV_OFFSET(n))
49 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
51 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
53 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
55 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
56 DISPC_ATTR2_OFFSET(n))
57 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
58 DISPC_FIFO_THRESH_OFFSET(n))
59 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
60 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
61 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
62 DISPC_ROW_INC_OFFSET(n))
63 #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
64 DISPC_PIX_INC_OFFSET(n))
65 #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
66 DISPC_WINDOW_SKIP_OFFSET(n))
67 #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
68 DISPC_TABLE_BA_OFFSET(n))
69 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
71 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
73 #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
74 DISPC_PIC_SIZE_OFFSET(n))
75 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
76 DISPC_ACCU0_OFFSET(n))
77 #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
78 DISPC_ACCU1_OFFSET(n))
79 #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
80 DISPC_ACCU2_0_OFFSET(n))
81 #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
82 DISPC_ACCU2_1_OFFSET(n))
83 #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
84 DISPC_FIR_COEF_H_OFFSET(n, i))
85 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
86 DISPC_FIR_COEF_HV_OFFSET(n, i))
87 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
88 DISPC_FIR_COEF_H2_OFFSET(n, i))
89 #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
90 DISPC_FIR_COEF_HV2_OFFSET(n, i))
91 #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
92 DISPC_CONV_COEF_OFFSET(n, i))
93 #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
94 DISPC_FIR_COEF_V_OFFSET(n, i))
95 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
96 DISPC_FIR_COEF_V2_OFFSET(n, i))
97 #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
98 DISPC_PRELOAD_OFFSET(n))
100 /* DISPC up/downsampling FIR filter coefficient structure */
109 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
111 /* DISPC manager/channel specific registers */
112 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
115 case OMAP_DSS_CHANNEL_LCD:
117 case OMAP_DSS_CHANNEL_DIGIT:
119 case OMAP_DSS_CHANNEL_LCD2:
126 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
129 case OMAP_DSS_CHANNEL_LCD:
131 case OMAP_DSS_CHANNEL_DIGIT:
133 case OMAP_DSS_CHANNEL_LCD2:
140 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
143 case OMAP_DSS_CHANNEL_LCD:
145 case OMAP_DSS_CHANNEL_DIGIT:
147 case OMAP_DSS_CHANNEL_LCD2:
154 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
157 case OMAP_DSS_CHANNEL_LCD:
159 case OMAP_DSS_CHANNEL_DIGIT:
161 case OMAP_DSS_CHANNEL_LCD2:
168 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
171 case OMAP_DSS_CHANNEL_LCD:
173 case OMAP_DSS_CHANNEL_DIGIT:
175 case OMAP_DSS_CHANNEL_LCD2:
182 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
185 case OMAP_DSS_CHANNEL_LCD:
187 case OMAP_DSS_CHANNEL_DIGIT:
189 case OMAP_DSS_CHANNEL_LCD2:
196 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
197 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
200 case OMAP_DSS_CHANNEL_LCD:
202 case OMAP_DSS_CHANNEL_DIGIT:
204 case OMAP_DSS_CHANNEL_LCD2:
211 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
214 case OMAP_DSS_CHANNEL_LCD:
216 case OMAP_DSS_CHANNEL_DIGIT:
218 case OMAP_DSS_CHANNEL_LCD2:
225 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
228 case OMAP_DSS_CHANNEL_LCD:
230 case OMAP_DSS_CHANNEL_DIGIT:
232 case OMAP_DSS_CHANNEL_LCD2:
239 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
242 case OMAP_DSS_CHANNEL_LCD:
244 case OMAP_DSS_CHANNEL_DIGIT:
246 case OMAP_DSS_CHANNEL_LCD2:
253 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
256 case OMAP_DSS_CHANNEL_LCD:
258 case OMAP_DSS_CHANNEL_DIGIT:
260 case OMAP_DSS_CHANNEL_LCD2:
267 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
270 case OMAP_DSS_CHANNEL_LCD:
272 case OMAP_DSS_CHANNEL_DIGIT:
274 case OMAP_DSS_CHANNEL_LCD2:
281 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
284 case OMAP_DSS_CHANNEL_LCD:
286 case OMAP_DSS_CHANNEL_DIGIT:
288 case OMAP_DSS_CHANNEL_LCD2:
295 /* DISPC overlay register base addresses */
296 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
301 case OMAP_DSS_VIDEO1:
303 case OMAP_DSS_VIDEO2:
305 case OMAP_DSS_VIDEO3:
312 /* DISPC overlay register offsets */
313 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
317 case OMAP_DSS_VIDEO1:
318 case OMAP_DSS_VIDEO2:
320 case OMAP_DSS_VIDEO3:
327 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
331 case OMAP_DSS_VIDEO1:
332 case OMAP_DSS_VIDEO2:
334 case OMAP_DSS_VIDEO3:
341 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
346 case OMAP_DSS_VIDEO1:
348 case OMAP_DSS_VIDEO2:
350 case OMAP_DSS_VIDEO3:
357 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
362 case OMAP_DSS_VIDEO1:
364 case OMAP_DSS_VIDEO2:
366 case OMAP_DSS_VIDEO3:
373 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
377 case OMAP_DSS_VIDEO1:
378 case OMAP_DSS_VIDEO2:
380 case OMAP_DSS_VIDEO3:
387 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
391 case OMAP_DSS_VIDEO1:
392 case OMAP_DSS_VIDEO2:
394 case OMAP_DSS_VIDEO3:
401 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
406 case OMAP_DSS_VIDEO1:
407 case OMAP_DSS_VIDEO2:
409 case OMAP_DSS_VIDEO3:
416 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
421 case OMAP_DSS_VIDEO1:
423 case OMAP_DSS_VIDEO2:
425 case OMAP_DSS_VIDEO3:
432 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
437 case OMAP_DSS_VIDEO1:
438 case OMAP_DSS_VIDEO2:
440 case OMAP_DSS_VIDEO3:
447 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
452 case OMAP_DSS_VIDEO1:
453 case OMAP_DSS_VIDEO2:
455 case OMAP_DSS_VIDEO3:
462 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
467 case OMAP_DSS_VIDEO1:
468 case OMAP_DSS_VIDEO2:
470 case OMAP_DSS_VIDEO3:
477 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
482 case OMAP_DSS_VIDEO1:
483 case OMAP_DSS_VIDEO2:
485 case OMAP_DSS_VIDEO3:
492 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
497 case OMAP_DSS_VIDEO1:
498 case OMAP_DSS_VIDEO2:
499 case OMAP_DSS_VIDEO3:
506 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
511 case OMAP_DSS_VIDEO1:
512 case OMAP_DSS_VIDEO2:
513 case OMAP_DSS_VIDEO3:
520 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
525 case OMAP_DSS_VIDEO1:
526 case OMAP_DSS_VIDEO2:
528 case OMAP_DSS_VIDEO3:
535 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
540 case OMAP_DSS_VIDEO1:
542 case OMAP_DSS_VIDEO2:
544 case OMAP_DSS_VIDEO3:
551 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
556 case OMAP_DSS_VIDEO1:
557 case OMAP_DSS_VIDEO2:
559 case OMAP_DSS_VIDEO3:
567 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
572 case OMAP_DSS_VIDEO1:
573 case OMAP_DSS_VIDEO2:
575 case OMAP_DSS_VIDEO3:
582 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
587 case OMAP_DSS_VIDEO1:
589 case OMAP_DSS_VIDEO2:
591 case OMAP_DSS_VIDEO3:
598 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
603 case OMAP_DSS_VIDEO1:
604 case OMAP_DSS_VIDEO2:
606 case OMAP_DSS_VIDEO3:
613 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
618 case OMAP_DSS_VIDEO1:
620 case OMAP_DSS_VIDEO2:
622 case OMAP_DSS_VIDEO3:
629 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
630 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
635 case OMAP_DSS_VIDEO1:
636 case OMAP_DSS_VIDEO2:
637 return 0x0034 + i * 0x8;
638 case OMAP_DSS_VIDEO3:
639 return 0x0010 + i * 0x8;
645 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
646 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
651 case OMAP_DSS_VIDEO1:
652 return 0x058C + i * 0x8;
653 case OMAP_DSS_VIDEO2:
654 return 0x0568 + i * 0x8;
655 case OMAP_DSS_VIDEO3:
656 return 0x0430 + i * 0x8;
662 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
663 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
668 case OMAP_DSS_VIDEO1:
669 case OMAP_DSS_VIDEO2:
670 return 0x0038 + i * 0x8;
671 case OMAP_DSS_VIDEO3:
672 return 0x0014 + i * 0x8;
678 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
679 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
684 case OMAP_DSS_VIDEO1:
685 return 0x0590 + i * 8;
686 case OMAP_DSS_VIDEO2:
687 return 0x056C + i * 0x8;
688 case OMAP_DSS_VIDEO3:
689 return 0x0434 + i * 0x8;
695 /* coef index i = {0, 1, 2, 3, 4,} */
696 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
701 case OMAP_DSS_VIDEO1:
702 case OMAP_DSS_VIDEO2:
703 case OMAP_DSS_VIDEO3:
704 return 0x0074 + i * 0x4;
710 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
711 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
716 case OMAP_DSS_VIDEO1:
717 return 0x0124 + i * 0x4;
718 case OMAP_DSS_VIDEO2:
719 return 0x00B4 + i * 0x4;
720 case OMAP_DSS_VIDEO3:
721 return 0x0050 + i * 0x4;
727 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
728 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
733 case OMAP_DSS_VIDEO1:
734 return 0x05CC + i * 0x4;
735 case OMAP_DSS_VIDEO2:
736 return 0x05A8 + i * 0x4;
737 case OMAP_DSS_VIDEO3:
738 return 0x0470 + i * 0x4;
744 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
749 case OMAP_DSS_VIDEO1:
751 case OMAP_DSS_VIDEO2:
753 case OMAP_DSS_VIDEO3: