drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42 #include "dss_features.h"
  43
  44 /* DISPC */
  45 #define DISPC_BASE                      0x48050400
  46
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 struct dispc_reg { u16 idx; };
  50
  51 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  52
  53 /*
  54  * DISPC common registers and
  55  * DISPC channel registers , ch = 0 for LCD, ch = 1 for
  56  * DIGIT, and ch = 2 for LCD2
  57  */
  58 #define DISPC_REVISION                  DISPC_REG(0x0000)
  59 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  60 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  61 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  62 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  63 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  64 #define DISPC_CONTROL2                  DISPC_REG(0x0238)
  65 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  66 #define DISPC_CONFIG2                   DISPC_REG(0x0620)
  67 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  68 #define DISPC_DEFAULT_COLOR(ch)         DISPC_REG(ch == 0 ? 0x004C : \
  69                                         (ch == 1 ? 0x0050 : 0x03AC))
  70 #define DISPC_TRANS_COLOR(ch)           DISPC_REG(ch == 0 ? 0x0054 : \
  71                                         (ch == 1 ? 0x0058 : 0x03B0))
  72 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  73 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  74 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
  75 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
  76 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
  77 #define DISPC_DIVISOR(ch)               DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
  78 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  79 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  80 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
  81
  82 /* DISPC GFX plane */
  83 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  84 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  85 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  86 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  87 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  88 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  89 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  90 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  91 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  92 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  93 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  94
  95 #define DISPC_DATA_CYCLE1(ch)           DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
  96 #define DISPC_DATA_CYCLE2(ch)           DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
  97 #define DISPC_DATA_CYCLE3(ch)           DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
  98 #define DISPC_CPR_COEF_R(ch)            DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
  99 #define DISPC_CPR_COEF_G(ch)            DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
 100 #define DISPC_CPR_COEF_B(ch)            DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
 101
 102 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
 103
 104 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 105 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 106
 107 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 108 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 109 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 110 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 111 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 112 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 113 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 114 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 115 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 116 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 117 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 118 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 119 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 120
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 123 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 124 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 125 /* coef index i = {0, 1, 2, 3, 4} */
 126 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 127 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 128 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 129
 130 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 131
 132
 133 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 134                                          DISPC_IRQ_OCP_ERR | \
 135                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 136                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 137                                          DISPC_IRQ_SYNC_LOST | \
 138                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 139
 140 #define DISPC_MAX_NR_ISRS               8
 141
 142 struct omap_dispc_isr_data {
 143         omap_dispc_isr_t        isr;
 144         void                    *arg;
 145         u32                     mask;
 146 };
 147
 148 struct dispc_h_coef {
 149         s8 hc4;
 150         s8 hc3;
 151         u8 hc2;
 152         s8 hc1;
 153         s8 hc0;
 154 };
 155
 156 struct dispc_v_coef {
 157         s8 vc22;
 158         s8 vc2;
 159         u8 vc1;
 160         s8 vc0;
 161         s8 vc00;
 162 };
 163
 164 #define REG_GET(idx, start, end) \
 165         FLD_GET(dispc_read_reg(idx), start, end)
 166
 167 #define REG_FLD_MOD(idx, val, start, end)                               \
 168         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 169
 170 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 171         DISPC_VID_ATTRIBUTES(0),
 172         DISPC_VID_ATTRIBUTES(1) };
 173
 174 struct dispc_irq_stats {
 175         unsigned long last_reset;
 176         unsigned irq_count;
 177         unsigned irqs[32];
 178 };
 179
 180 static struct {
 181         void __iomem    *base;
 182
 183         u32     fifo_size[3];
 184
 185         spinlock_t irq_lock;
 186         u32 irq_error_mask;
 187         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 188         u32 error_irqs;
 189         struct work_struct error_work;
 190
 191         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 192
 193 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 194         spinlock_t irq_stats_lock;
 195         struct dispc_irq_stats irq_stats;
 196 #endif
 197 } dispc;
 198
 199 static void _omap_dispc_set_irqs(void);
 200
 201 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 202 {
 203         __raw_writel(val, dispc.base + idx.idx);
 204 }
 205
 206 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 207 {
 208         return __raw_readl(dispc.base + idx.idx);
 209 }
 210
 211 #define SR(reg) \
 212         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 213 #define RR(reg) \
 214         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 215
 216 void dispc_save_context(void)
 217 {
 218         if (cpu_is_omap24xx())
 219                 return;
 220
 221         SR(SYSCONFIG);
 222         SR(IRQENABLE);
 223         SR(CONTROL);
 224         SR(CONFIG);
 225         SR(DEFAULT_COLOR(0));
 226         SR(DEFAULT_COLOR(1));
 227         SR(TRANS_COLOR(0));
 228         SR(TRANS_COLOR(1));
 229         SR(LINE_NUMBER);
 230         SR(TIMING_H(0));
 231         SR(TIMING_V(0));
 232         SR(POL_FREQ(0));
 233         SR(DIVISOR(0));
 234         SR(GLOBAL_ALPHA);
 235         SR(SIZE_DIG);
 236         SR(SIZE_LCD(0));
 237         if (dss_has_feature(FEAT_MGR_LCD2)) {
 238                 SR(CONTROL2);
 239                 SR(DEFAULT_COLOR(2));
 240                 SR(TRANS_COLOR(2));
 241                 SR(SIZE_LCD(2));
 242                 SR(TIMING_H(2));
 243                 SR(TIMING_V(2));
 244                 SR(POL_FREQ(2));
 245                 SR(DIVISOR(2));
 246                 SR(CONFIG2);
 247         }
 248
 249         SR(GFX_BA0);
 250         SR(GFX_BA1);
 251         SR(GFX_POSITION);
 252         SR(GFX_SIZE);
 253         SR(GFX_ATTRIBUTES);
 254         SR(GFX_FIFO_THRESHOLD);
 255         SR(GFX_ROW_INC);
 256         SR(GFX_PIXEL_INC);
 257         SR(GFX_WINDOW_SKIP);
 258         SR(GFX_TABLE_BA);
 259
 260         SR(DATA_CYCLE1(0));
 261         SR(DATA_CYCLE2(0));
 262         SR(DATA_CYCLE3(0));
 263
 264         SR(CPR_COEF_R(0));
 265         SR(CPR_COEF_G(0));
 266         SR(CPR_COEF_B(0));
 267         if (dss_has_feature(FEAT_MGR_LCD2)) {
 268                 SR(CPR_COEF_B(2));
 269                 SR(CPR_COEF_G(2));
 270                 SR(CPR_COEF_R(2));
 271
 272                 SR(DATA_CYCLE1(2));
 273                 SR(DATA_CYCLE2(2));
 274                 SR(DATA_CYCLE3(2));
 275         }
 276
 277         SR(GFX_PRELOAD);
 278
 279         /* VID1 */
 280         SR(VID_BA0(0));
 281         SR(VID_BA1(0));
 282         SR(VID_POSITION(0));
 283         SR(VID_SIZE(0));
 284         SR(VID_ATTRIBUTES(0));
 285         SR(VID_FIFO_THRESHOLD(0));
 286         SR(VID_ROW_INC(0));
 287         SR(VID_PIXEL_INC(0));
 288         SR(VID_FIR(0));
 289         SR(VID_PICTURE_SIZE(0));
 290         SR(VID_ACCU0(0));
 291         SR(VID_ACCU1(0));
 292
 293         SR(VID_FIR_COEF_H(0, 0));
 294         SR(VID_FIR_COEF_H(0, 1));
 295         SR(VID_FIR_COEF_H(0, 2));
 296         SR(VID_FIR_COEF_H(0, 3));
 297         SR(VID_FIR_COEF_H(0, 4));
 298         SR(VID_FIR_COEF_H(0, 5));
 299         SR(VID_FIR_COEF_H(0, 6));
 300         SR(VID_FIR_COEF_H(0, 7));
 301
 302         SR(VID_FIR_COEF_HV(0, 0));
 303         SR(VID_FIR_COEF_HV(0, 1));
 304         SR(VID_FIR_COEF_HV(0, 2));
 305         SR(VID_FIR_COEF_HV(0, 3));
 306         SR(VID_FIR_COEF_HV(0, 4));
 307         SR(VID_FIR_COEF_HV(0, 5));
 308         SR(VID_FIR_COEF_HV(0, 6));
 309         SR(VID_FIR_COEF_HV(0, 7));
 310
 311         SR(VID_CONV_COEF(0, 0));
 312         SR(VID_CONV_COEF(0, 1));
 313         SR(VID_CONV_COEF(0, 2));
 314         SR(VID_CONV_COEF(0, 3));
 315         SR(VID_CONV_COEF(0, 4));
 316
 317         SR(VID_FIR_COEF_V(0, 0));
 318         SR(VID_FIR_COEF_V(0, 1));
 319         SR(VID_FIR_COEF_V(0, 2));
 320         SR(VID_FIR_COEF_V(0, 3));
 321         SR(VID_FIR_COEF_V(0, 4));
 322         SR(VID_FIR_COEF_V(0, 5));
 323         SR(VID_FIR_COEF_V(0, 6));
 324         SR(VID_FIR_COEF_V(0, 7));
 325
 326         SR(VID_PRELOAD(0));
 327
 328         /* VID2 */
 329         SR(VID_BA0(1));
 330         SR(VID_BA1(1));
 331         SR(VID_POSITION(1));
 332         SR(VID_SIZE(1));
 333         SR(VID_ATTRIBUTES(1));
 334         SR(VID_FIFO_THRESHOLD(1));
 335         SR(VID_ROW_INC(1));
 336         SR(VID_PIXEL_INC(1));
 337         SR(VID_FIR(1));
 338         SR(VID_PICTURE_SIZE(1));
 339         SR(VID_ACCU0(1));
 340         SR(VID_ACCU1(1));
 341
 342         SR(VID_FIR_COEF_H(1, 0));
 343         SR(VID_FIR_COEF_H(1, 1));
 344         SR(VID_FIR_COEF_H(1, 2));
 345         SR(VID_FIR_COEF_H(1, 3));
 346         SR(VID_FIR_COEF_H(1, 4));
 347         SR(VID_FIR_COEF_H(1, 5));
 348         SR(VID_FIR_COEF_H(1, 6));
 349         SR(VID_FIR_COEF_H(1, 7));
 350
 351         SR(VID_FIR_COEF_HV(1, 0));
 352         SR(VID_FIR_COEF_HV(1, 1));
 353         SR(VID_FIR_COEF_HV(1, 2));
 354         SR(VID_FIR_COEF_HV(1, 3));
 355         SR(VID_FIR_COEF_HV(1, 4));
 356         SR(VID_FIR_COEF_HV(1, 5));
 357         SR(VID_FIR_COEF_HV(1, 6));
 358         SR(VID_FIR_COEF_HV(1, 7));
 359
 360         SR(VID_CONV_COEF(1, 0));
 361         SR(VID_CONV_COEF(1, 1));
 362         SR(VID_CONV_COEF(1, 2));
 363         SR(VID_CONV_COEF(1, 3));
 364         SR(VID_CONV_COEF(1, 4));
 365
 366         SR(VID_FIR_COEF_V(1, 0));
 367         SR(VID_FIR_COEF_V(1, 1));
 368         SR(VID_FIR_COEF_V(1, 2));
 369         SR(VID_FIR_COEF_V(1, 3));
 370         SR(VID_FIR_COEF_V(1, 4));
 371         SR(VID_FIR_COEF_V(1, 5));
 372         SR(VID_FIR_COEF_V(1, 6));
 373         SR(VID_FIR_COEF_V(1, 7));
 374
 375         SR(VID_PRELOAD(1));
 376 }
 377
 378 void dispc_restore_context(void)
 379 {
 380         RR(SYSCONFIG);
 381         /*RR(IRQENABLE);*/
 382         /*RR(CONTROL);*/
 383         RR(CONFIG);
 384         RR(DEFAULT_COLOR(0));
 385         RR(DEFAULT_COLOR(1));
 386         RR(TRANS_COLOR(0));
 387         RR(TRANS_COLOR(1));
 388         RR(LINE_NUMBER);
 389         RR(TIMING_H(0));
 390         RR(TIMING_V(0));
 391         RR(POL_FREQ(0));
 392         RR(DIVISOR(0));
 393         RR(GLOBAL_ALPHA);
 394         RR(SIZE_DIG);
 395         RR(SIZE_LCD(0));
 396         if (dss_has_feature(FEAT_MGR_LCD2)) {
 397                 RR(DEFAULT_COLOR(2));
 398                 RR(TRANS_COLOR(2));
 399                 RR(SIZE_LCD(2));
 400                 RR(TIMING_H(2));
 401                 RR(TIMING_V(2));
 402                 RR(POL_FREQ(2));
 403                 RR(DIVISOR(2));
 404                 RR(CONFIG2);
 405         }
 406
 407         RR(GFX_BA0);
 408         RR(GFX_BA1);
 409         RR(GFX_POSITION);
 410         RR(GFX_SIZE);
 411         RR(GFX_ATTRIBUTES);
 412         RR(GFX_FIFO_THRESHOLD);
 413         RR(GFX_ROW_INC);
 414         RR(GFX_PIXEL_INC);
 415         RR(GFX_WINDOW_SKIP);
 416         RR(GFX_TABLE_BA);
 417
 418         RR(DATA_CYCLE1(0));
 419         RR(DATA_CYCLE2(0));
 420         RR(DATA_CYCLE3(0));
 421
 422         RR(CPR_COEF_R(0));
 423         RR(CPR_COEF_G(0));
 424         RR(CPR_COEF_B(0));
 425         if (dss_has_feature(FEAT_MGR_LCD2)) {
 426                 RR(DATA_CYCLE1(2));
 427                 RR(DATA_CYCLE2(2));
 428                 RR(DATA_CYCLE3(2));
 429
 430                 RR(CPR_COEF_B(2));
 431                 RR(CPR_COEF_G(2));
 432                 RR(CPR_COEF_R(2));
 433         }
 434
 435         RR(GFX_PRELOAD);
 436
 437         /* VID1 */
 438         RR(VID_BA0(0));
 439         RR(VID_BA1(0));
 440         RR(VID_POSITION(0));
 441         RR(VID_SIZE(0));
 442         RR(VID_ATTRIBUTES(0));
 443         RR(VID_FIFO_THRESHOLD(0));
 444         RR(VID_ROW_INC(0));
 445         RR(VID_PIXEL_INC(0));
 446         RR(VID_FIR(0));
 447         RR(VID_PICTURE_SIZE(0));
 448         RR(VID_ACCU0(0));
 449         RR(VID_ACCU1(0));
 450
 451         RR(VID_FIR_COEF_H(0, 0));
 452         RR(VID_FIR_COEF_H(0, 1));
 453         RR(VID_FIR_COEF_H(0, 2));
 454         RR(VID_FIR_COEF_H(0, 3));
 455         RR(VID_FIR_COEF_H(0, 4));
 456         RR(VID_FIR_COEF_H(0, 5));
 457         RR(VID_FIR_COEF_H(0, 6));
 458         RR(VID_FIR_COEF_H(0, 7));
 459
 460         RR(VID_FIR_COEF_HV(0, 0));
 461         RR(VID_FIR_COEF_HV(0, 1));
 462         RR(VID_FIR_COEF_HV(0, 2));
 463         RR(VID_FIR_COEF_HV(0, 3));
 464         RR(VID_FIR_COEF_HV(0, 4));
 465         RR(VID_FIR_COEF_HV(0, 5));
 466         RR(VID_FIR_COEF_HV(0, 6));
 467         RR(VID_FIR_COEF_HV(0, 7));
 468
 469         RR(VID_CONV_COEF(0, 0));
 470         RR(VID_CONV_COEF(0, 1));
 471         RR(VID_CONV_COEF(0, 2));
 472         RR(VID_CONV_COEF(0, 3));
 473         RR(VID_CONV_COEF(0, 4));
 474
 475         RR(VID_FIR_COEF_V(0, 0));
 476         RR(VID_FIR_COEF_V(0, 1));
 477         RR(VID_FIR_COEF_V(0, 2));
 478         RR(VID_FIR_COEF_V(0, 3));
 479         RR(VID_FIR_COEF_V(0, 4));
 480         RR(VID_FIR_COEF_V(0, 5));
 481         RR(VID_FIR_COEF_V(0, 6));
 482         RR(VID_FIR_COEF_V(0, 7));
 483
 484         RR(VID_PRELOAD(0));
 485
 486         /* VID2 */
 487         RR(VID_BA0(1));
 488         RR(VID_BA1(1));
 489         RR(VID_POSITION(1));
 490         RR(VID_SIZE(1));
 491         RR(VID_ATTRIBUTES(1));
 492         RR(VID_FIFO_THRESHOLD(1));
 493         RR(VID_ROW_INC(1));
 494         RR(VID_PIXEL_INC(1));
 495         RR(VID_FIR(1));
 496         RR(VID_PICTURE_SIZE(1));
 497         RR(VID_ACCU0(1));
 498         RR(VID_ACCU1(1));
 499
 500         RR(VID_FIR_COEF_H(1, 0));
 501         RR(VID_FIR_COEF_H(1, 1));
 502         RR(VID_FIR_COEF_H(1, 2));
 503         RR(VID_FIR_COEF_H(1, 3));
 504         RR(VID_FIR_COEF_H(1, 4));
 505         RR(VID_FIR_COEF_H(1, 5));
 506         RR(VID_FIR_COEF_H(1, 6));
 507         RR(VID_FIR_COEF_H(1, 7));
 508
 509         RR(VID_FIR_COEF_HV(1, 0));
 510         RR(VID_FIR_COEF_HV(1, 1));
 511         RR(VID_FIR_COEF_HV(1, 2));
 512         RR(VID_FIR_COEF_HV(1, 3));
 513         RR(VID_FIR_COEF_HV(1, 4));
 514         RR(VID_FIR_COEF_HV(1, 5));
 515         RR(VID_FIR_COEF_HV(1, 6));
 516         RR(VID_FIR_COEF_HV(1, 7));
 517
 518         RR(VID_CONV_COEF(1, 0));
 519         RR(VID_CONV_COEF(1, 1));
 520         RR(VID_CONV_COEF(1, 2));
 521         RR(VID_CONV_COEF(1, 3));
 522         RR(VID_CONV_COEF(1, 4));
 523
 524         RR(VID_FIR_COEF_V(1, 0));
 525         RR(VID_FIR_COEF_V(1, 1));
 526         RR(VID_FIR_COEF_V(1, 2));
 527         RR(VID_FIR_COEF_V(1, 3));
 528         RR(VID_FIR_COEF_V(1, 4));
 529         RR(VID_FIR_COEF_V(1, 5));
 530         RR(VID_FIR_COEF_V(1, 6));
 531         RR(VID_FIR_COEF_V(1, 7));
 532
 533         RR(VID_PRELOAD(1));
 534
 535         /* enable last, because LCD & DIGIT enable are here */
 536         RR(CONTROL);
 537         if (dss_has_feature(FEAT_MGR_LCD2))
 538                 RR(CONTROL2);
 539         /* clear spurious SYNC_LOST_DIGIT interrupts */
 540         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 541
 542         /*
 543          * enable last so IRQs won't trigger before
 544          * the context is fully restored
 545          */
 546         RR(IRQENABLE);
 547 }
 548
 549 #undef SR
 550 #undef RR
 551
 552 static inline void enable_clocks(bool enable)
 553 {
 554         if (enable)
 555                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 556         else
 557                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 558 }
 559
 560 bool dispc_go_busy(enum omap_channel channel)
 561 {
 562         int bit;
 563
 564         if (channel == OMAP_DSS_CHANNEL_LCD ||
 565                         channel == OMAP_DSS_CHANNEL_LCD2)
 566                 bit = 5; /* GOLCD */
 567         else
 568                 bit = 6; /* GODIGIT */
 569
 570         if (channel == OMAP_DSS_CHANNEL_LCD2)
 571                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 572         else
 573                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 574 }
 575
 576 void dispc_go(enum omap_channel channel)
 577 {
 578         int bit;
 579         bool enable_bit, go_bit;
 580
 581         enable_clocks(1);
 582
 583         if (channel == OMAP_DSS_CHANNEL_LCD ||
 584                         channel == OMAP_DSS_CHANNEL_LCD2)
 585                 bit = 0; /* LCDENABLE */
 586         else
 587                 bit = 1; /* DIGITALENABLE */
 588
 589         /* if the channel is not enabled, we don't need GO */
 590         if (channel == OMAP_DSS_CHANNEL_LCD2)
 591                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 592         else
 593                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 594
 595         if (!enable_bit)
 596                 goto end;
 597
 598         if (channel == OMAP_DSS_CHANNEL_LCD ||
 599                         channel == OMAP_DSS_CHANNEL_LCD2)
 600                 bit = 5; /* GOLCD */
 601         else
 602                 bit = 6; /* GODIGIT */
 603
 604         if (channel == OMAP_DSS_CHANNEL_LCD2)
 605                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 606         else
 607                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 608
 609         if (go_bit) {
 610                 DSSERR("GO bit not down for channel %d\n", channel);
 611                 goto end;
 612         }
 613
 614         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 615                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 616
 617         if (channel == OMAP_DSS_CHANNEL_LCD2)
 618                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 619         else
 620                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 621 end:
 622         enable_clocks(0);
 623 }
 624
 625 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 626 {
 627         BUG_ON(plane == OMAP_DSS_GFX);
 628
 629         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 630 }
 631
 632 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 633 {
 634         BUG_ON(plane == OMAP_DSS_GFX);
 635
 636         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 637 }
 638
 639 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 640 {
 641         BUG_ON(plane == OMAP_DSS_GFX);
 642
 643         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 644 }
 645
 646 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 647                 int vscaleup, int five_taps)
 648 {
 649         /* Coefficients for horizontal up-sampling */
 650         static const struct dispc_h_coef coef_hup[8] = {
 651                 {  0,   0, 128,   0,  0 },
 652                 { -1,  13, 124,  -8,  0 },
 653                 { -2,  30, 112, -11, -1 },
 654                 { -5,  51,  95, -11, -2 },
 655                 {  0,  -9,  73,  73, -9 },
 656                 { -2, -11,  95,  51, -5 },
 657                 { -1, -11, 112,  30, -2 },
 658                 {  0,  -8, 124,  13, -1 },
 659         };
 660
 661         /* Coefficients for vertical up-sampling */
 662         static const struct dispc_v_coef coef_vup_3tap[8] = {
 663                 { 0,  0, 128,  0, 0 },
 664                 { 0,  3, 123,  2, 0 },
 665                 { 0, 12, 111,  5, 0 },
 666                 { 0, 32,  89,  7, 0 },
 667                 { 0,  0,  64, 64, 0 },
 668                 { 0,  7,  89, 32, 0 },
 669                 { 0,  5, 111, 12, 0 },
 670                 { 0,  2, 123,  3, 0 },
 671         };
 672
 673         static const struct dispc_v_coef coef_vup_5tap[8] = {
 674                 {  0,   0, 128,   0,  0 },
 675                 { -1,  13, 124,  -8,  0 },
 676                 { -2,  30, 112, -11, -1 },
 677                 { -5,  51,  95, -11, -2 },
 678                 {  0,  -9,  73,  73, -9 },
 679                 { -2, -11,  95,  51, -5 },
 680                 { -1, -11, 112,  30, -2 },
 681                 {  0,  -8, 124,  13, -1 },
 682         };
 683
 684         /* Coefficients for horizontal down-sampling */
 685         static const struct dispc_h_coef coef_hdown[8] = {
 686                 {   0, 36, 56, 36,  0 },
 687                 {   4, 40, 55, 31, -2 },
 688                 {   8, 44, 54, 27, -5 },
 689                 {  12, 48, 53, 22, -7 },
 690                 {  -9, 17, 52, 51, 17 },
 691                 {  -7, 22, 53, 48, 12 },
 692                 {  -5, 27, 54, 44,  8 },
 693                 {  -2, 31, 55, 40,  4 },
 694         };
 695
 696         /* Coefficients for vertical down-sampling */
 697         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 698                 { 0, 36, 56, 36, 0 },
 699                 { 0, 40, 57, 31, 0 },
 700                 { 0, 45, 56, 27, 0 },
 701                 { 0, 50, 55, 23, 0 },
 702                 { 0, 18, 55, 55, 0 },
 703                 { 0, 23, 55, 50, 0 },
 704                 { 0, 27, 56, 45, 0 },
 705                 { 0, 31, 57, 40, 0 },
 706         };
 707
 708         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 709                 {   0, 36, 56, 36,  0 },
 710                 {   4, 40, 55, 31, -2 },
 711                 {   8, 44, 54, 27, -5 },
 712                 {  12, 48, 53, 22, -7 },
 713                 {  -9, 17, 52, 51, 17 },
 714                 {  -7, 22, 53, 48, 12 },
 715                 {  -5, 27, 54, 44,  8 },
 716                 {  -2, 31, 55, 40,  4 },
 717         };
 718
 719         const struct dispc_h_coef *h_coef;
 720         const struct dispc_v_coef *v_coef;
 721         int i;
 722
 723         if (hscaleup)
 724                 h_coef = coef_hup;
 725         else
 726                 h_coef = coef_hdown;
 727
 728         if (vscaleup)
 729                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 730         else
 731                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 732
 733         for (i = 0; i < 8; i++) {
 734                 u32 h, hv;
 735
 736                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 737                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 738                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 739                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 740                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 741                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 742                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 743                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 744
 745                 _dispc_write_firh_reg(plane, i, h);
 746                 _dispc_write_firhv_reg(plane, i, hv);
 747         }
 748
 749         if (five_taps) {
 750                 for (i = 0; i < 8; i++) {
 751                         u32 v;
 752                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 753                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 754                         _dispc_write_firv_reg(plane, i, v);
 755                 }
 756         }
 757 }
 758
 759 static void _dispc_setup_color_conv_coef(void)
 760 {
 761         const struct color_conv_coef {
 762                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 763                 int  full_range;
 764         }  ctbl_bt601_5 = {
 765                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 766         };
 767
 768         const struct color_conv_coef *ct;
 769
 770 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 771
 772         ct = &ctbl_bt601_5;
 773
 774         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 775         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 776         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 777         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 778         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 779
 780         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 781         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 782         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 783         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 784         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 785
 786 #undef CVAL
 787
 788         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 789         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 790 }
 791
 792
 793 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 794 {
 795         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 796                 DISPC_VID_BA0(0),
 797                 DISPC_VID_BA0(1) };
 798
 799         dispc_write_reg(ba0_reg[plane], paddr);
 800 }
 801
 802 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 803 {
 804         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 805                                       DISPC_VID_BA1(0),
 806                                       DISPC_VID_BA1(1) };
 807
 808         dispc_write_reg(ba1_reg[plane], paddr);
 809 }
 810
 811 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 812 {
 813         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 814                                       DISPC_VID_POSITION(0),
 815                                       DISPC_VID_POSITION(1) };
 816
 817         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 818         dispc_write_reg(pos_reg[plane], val);
 819 }
 820
 821 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 822 {
 823         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 824                                       DISPC_VID_PICTURE_SIZE(0),
 825                                       DISPC_VID_PICTURE_SIZE(1) };
 826         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 827         dispc_write_reg(siz_reg[plane], val);
 828 }
 829
 830 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 831 {
 832         u32 val;
 833         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 834                                       DISPC_VID_SIZE(1) };
 835
 836         BUG_ON(plane == OMAP_DSS_GFX);
 837
 838         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 839         dispc_write_reg(vsi_reg[plane-1], val);
 840 }
 841
 842 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 843 {
 844         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 845                 return;
 846
 847         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 848                 plane == OMAP_DSS_VIDEO1)
 849                 return;
 850
 851         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
 852 }
 853
 854 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 855 {
 856         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 857                 return;
 858
 859         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 860                 plane == OMAP_DSS_VIDEO1)
 861                 return;
 862
 863         if (plane == OMAP_DSS_GFX)
 864                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 865         else if (plane == OMAP_DSS_VIDEO2)
 866                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 867 }
 868
 869 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 870 {
 871         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 872                                      DISPC_VID_PIXEL_INC(0),
 873                                      DISPC_VID_PIXEL_INC(1) };
 874
 875         dispc_write_reg(ri_reg[plane], inc);
 876 }
 877
 878 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 879 {
 880         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 881                                      DISPC_VID_ROW_INC(0),
 882                                      DISPC_VID_ROW_INC(1) };
 883
 884         dispc_write_reg(ri_reg[plane], inc);
 885 }
 886
 887 static void _dispc_set_color_mode(enum omap_plane plane,
 888                 enum omap_color_mode color_mode)
 889 {
 890         u32 m = 0;
 891
 892         switch (color_mode) {
 893         case OMAP_DSS_COLOR_CLUT1:
 894                 m = 0x0; break;
 895         case OMAP_DSS_COLOR_CLUT2:
 896                 m = 0x1; break;
 897         case OMAP_DSS_COLOR_CLUT4:
 898                 m = 0x2; break;
 899         case OMAP_DSS_COLOR_CLUT8:
 900                 m = 0x3; break;
 901         case OMAP_DSS_COLOR_RGB12U:
 902                 m = 0x4; break;
 903         case OMAP_DSS_COLOR_ARGB16:
 904                 m = 0x5; break;
 905         case OMAP_DSS_COLOR_RGB16:
 906                 m = 0x6; break;
 907         case OMAP_DSS_COLOR_RGB24U:
 908                 m = 0x8; break;
 909         case OMAP_DSS_COLOR_RGB24P:
 910                 m = 0x9; break;
 911         case OMAP_DSS_COLOR_YUV2:
 912                 m = 0xa; break;
 913         case OMAP_DSS_COLOR_UYVY:
 914                 m = 0xb; break;
 915         case OMAP_DSS_COLOR_ARGB32:
 916                 m = 0xc; break;
 917         case OMAP_DSS_COLOR_RGBA32:
 918                 m = 0xd; break;
 919         case OMAP_DSS_COLOR_RGBX32:
 920                 m = 0xe; break;
 921         default:
 922                 BUG(); break;
 923         }
 924
 925         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 926 }
 927
 928 static void _dispc_set_channel_out(enum omap_plane plane,
 929                 enum omap_channel channel)
 930 {
 931         int shift;
 932         u32 val;
 933         int chan = 0, chan2 = 0;
 934
 935         switch (plane) {
 936         case OMAP_DSS_GFX:
 937                 shift = 8;
 938                 break;
 939         case OMAP_DSS_VIDEO1:
 940         case OMAP_DSS_VIDEO2:
 941                 shift = 16;
 942                 break;
 943         default:
 944                 BUG();
 945                 return;
 946         }
 947
 948         val = dispc_read_reg(dispc_reg_att[plane]);
 949         if (dss_has_feature(FEAT_MGR_LCD2)) {
 950                 switch (channel) {
 951                 case OMAP_DSS_CHANNEL_LCD:
 952                         chan = 0;
 953                         chan2 = 0;
 954                         break;
 955                 case OMAP_DSS_CHANNEL_DIGIT:
 956                         chan = 1;
 957                         chan2 = 0;
 958                         break;
 959                 case OMAP_DSS_CHANNEL_LCD2:
 960                         chan = 0;
 961                         chan2 = 1;
 962                         break;
 963                 default:
 964                         BUG();
 965                 }
 966
 967                 val = FLD_MOD(val, chan, shift, shift);
 968                 val = FLD_MOD(val, chan2, 31, 30);
 969         } else {
 970                 val = FLD_MOD(val, channel, shift, shift);
 971         }
 972         dispc_write_reg(dispc_reg_att[plane], val);
 973 }
 974
 975 void dispc_set_burst_size(enum omap_plane plane,
 976                 enum omap_burst_size burst_size)
 977 {
 978         int shift;
 979         u32 val;
 980
 981         enable_clocks(1);
 982
 983         switch (plane) {
 984         case OMAP_DSS_GFX:
 985                 shift = 6;
 986                 break;
 987         case OMAP_DSS_VIDEO1:
 988         case OMAP_DSS_VIDEO2:
 989                 shift = 14;
 990                 break;
 991         default:
 992                 BUG();
 993                 return;
 994         }
 995
 996         val = dispc_read_reg(dispc_reg_att[plane]);
 997         val = FLD_MOD(val, burst_size, shift+1, shift);
 998         dispc_write_reg(dispc_reg_att[plane], val);
 999
1000         enable_clocks(0);
1001 }
1002
1003 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1004 {
1005         u32 val;
1006
1007         BUG_ON(plane == OMAP_DSS_GFX);
1008
1009         val = dispc_read_reg(dispc_reg_att[plane]);
1010         val = FLD_MOD(val, enable, 9, 9);
1011         dispc_write_reg(dispc_reg_att[plane], val);
1012 }
1013
1014 void dispc_enable_replication(enum omap_plane plane, bool enable)
1015 {
1016         int bit;
1017
1018         if (plane == OMAP_DSS_GFX)
1019                 bit = 5;
1020         else
1021                 bit = 10;
1022
1023         enable_clocks(1);
1024         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1025         enable_clocks(0);
1026 }
1027
1028 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1029 {
1030         u32 val;
1031         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1032         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1033         enable_clocks(1);
1034         dispc_write_reg(DISPC_SIZE_LCD(channel), val);
1035         enable_clocks(0);
1036 }
1037
1038 void dispc_set_digit_size(u16 width, u16 height)
1039 {
1040         u32 val;
1041         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1042         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1043         enable_clocks(1);
1044         dispc_write_reg(DISPC_SIZE_DIG, val);
1045         enable_clocks(0);
1046 }
1047
1048 static void dispc_read_plane_fifo_sizes(void)
1049 {
1050         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1051                                       DISPC_VID_FIFO_SIZE_STATUS(0),
1052                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
1053         u32 size;
1054         int plane;
1055         u8 start, end;
1056
1057         enable_clocks(1);
1058
1059         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1060
1061         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1062                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
1063                 dispc.fifo_size[plane] = size;
1064         }
1065
1066         enable_clocks(0);
1067 }
1068
1069 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1070 {
1071         return dispc.fifo_size[plane];
1072 }
1073
1074 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1075 {
1076         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1077                                        DISPC_VID_FIFO_THRESHOLD(0),
1078                                        DISPC_VID_FIFO_THRESHOLD(1) };
1079         u8 hi_start, hi_end, lo_start, lo_end;
1080
1081         enable_clocks(1);
1082
1083         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1084                         plane,
1085                         REG_GET(ftrs_reg[plane], 11, 0),
1086                         REG_GET(ftrs_reg[plane], 27, 16),
1087                         low, high);
1088
1089         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1090         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1091
1092         dispc_write_reg(ftrs_reg[plane],
1093                         FLD_VAL(high, hi_start, hi_end) |
1094                         FLD_VAL(low, lo_start, lo_end));
1095
1096         enable_clocks(0);
1097 }
1098
1099 void dispc_enable_fifomerge(bool enable)
1100 {
1101         enable_clocks(1);
1102
1103         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1104         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1105
1106         enable_clocks(0);
1107 }
1108
1109 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1110 {
1111         u32 val;
1112         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1113                                       DISPC_VID_FIR(1) };
1114         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1115
1116         BUG_ON(plane == OMAP_DSS_GFX);
1117
1118         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1119         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1120
1121         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1122                         FLD_VAL(hinc, hinc_start, hinc_end);
1123
1124         dispc_write_reg(fir_reg[plane-1], val);
1125 }
1126
1127 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1128 {
1129         u32 val;
1130         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1131                                       DISPC_VID_ACCU0(1) };
1132
1133         BUG_ON(plane == OMAP_DSS_GFX);
1134
1135         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1136         dispc_write_reg(ac0_reg[plane-1], val);
1137 }
1138
1139 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1140 {
1141         u32 val;
1142         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1143                                       DISPC_VID_ACCU1(1) };
1144
1145         BUG_ON(plane == OMAP_DSS_GFX);
1146
1147         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1148         dispc_write_reg(ac1_reg[plane-1], val);
1149 }
1150
1151
1152 static void _dispc_set_scaling(enum omap_plane plane,
1153                 u16 orig_width, u16 orig_height,
1154                 u16 out_width, u16 out_height,
1155                 bool ilace, bool five_taps,
1156                 bool fieldmode)
1157 {
1158         int fir_hinc;
1159         int fir_vinc;
1160         int hscaleup, vscaleup;
1161         int accu0 = 0;
1162         int accu1 = 0;
1163         u32 l;
1164
1165         BUG_ON(plane == OMAP_DSS_GFX);
1166
1167         hscaleup = orig_width <= out_width;
1168         vscaleup = orig_height <= out_height;
1169
1170         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1171
1172         if (!orig_width || orig_width == out_width)
1173                 fir_hinc = 0;
1174         else
1175                 fir_hinc = 1024 * orig_width / out_width;
1176
1177         if (!orig_height || orig_height == out_height)
1178                 fir_vinc = 0;
1179         else
1180                 fir_vinc = 1024 * orig_height / out_height;
1181
1182         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1183
1184         l = dispc_read_reg(dispc_reg_att[plane]);
1185         l &= ~((0x0f << 5) | (0x3 << 21));
1186
1187         l |= fir_hinc ? (1 << 5) : 0;
1188         l |= fir_vinc ? (1 << 6) : 0;
1189
1190         l |= hscaleup ? 0 : (1 << 7);
1191         l |= vscaleup ? 0 : (1 << 8);
1192
1193         l |= five_taps ? (1 << 21) : 0;
1194         l |= five_taps ? (1 << 22) : 0;
1195
1196         dispc_write_reg(dispc_reg_att[plane], l);
1197
1198         /*
1199          * field 0 = even field = bottom field
1200          * field 1 = odd field = top field
1201          */
1202         if (ilace && !fieldmode) {
1203                 accu1 = 0;
1204                 accu0 = (fir_vinc / 2) & 0x3ff;
1205                 if (accu0 >= 1024/2) {
1206                         accu1 = 1024/2;
1207                         accu0 -= accu1;
1208                 }
1209         }
1210
1211         _dispc_set_vid_accu0(plane, 0, accu0);
1212         _dispc_set_vid_accu1(plane, 0, accu1);
1213 }
1214
1215 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1216                 bool mirroring, enum omap_color_mode color_mode)
1217 {
1218         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1219                         color_mode == OMAP_DSS_COLOR_UYVY) {
1220                 int vidrot = 0;
1221
1222                 if (mirroring) {
1223                         switch (rotation) {
1224                         case OMAP_DSS_ROT_0:
1225                                 vidrot = 2;
1226                                 break;
1227                         case OMAP_DSS_ROT_90:
1228                                 vidrot = 1;
1229                                 break;
1230                         case OMAP_DSS_ROT_180:
1231                                 vidrot = 0;
1232                                 break;
1233                         case OMAP_DSS_ROT_270:
1234                                 vidrot = 3;
1235                                 break;
1236                         }
1237                 } else {
1238                         switch (rotation) {
1239                         case OMAP_DSS_ROT_0:
1240                                 vidrot = 0;
1241                                 break;
1242                         case OMAP_DSS_ROT_90:
1243                                 vidrot = 1;
1244                                 break;
1245                         case OMAP_DSS_ROT_180:
1246                                 vidrot = 2;
1247                                 break;
1248                         case OMAP_DSS_ROT_270:
1249                                 vidrot = 3;
1250                                 break;
1251                         }
1252                 }
1253
1254                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1255
1256                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1257                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1258                 else
1259                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1260         } else {
1261                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1262                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1263         }
1264 }
1265
1266 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1267 {
1268         switch (color_mode) {
1269         case OMAP_DSS_COLOR_CLUT1:
1270                 return 1;
1271         case OMAP_DSS_COLOR_CLUT2:
1272                 return 2;
1273         case OMAP_DSS_COLOR_CLUT4:
1274                 return 4;
1275         case OMAP_DSS_COLOR_CLUT8:
1276                 return 8;
1277         case OMAP_DSS_COLOR_RGB12U:
1278         case OMAP_DSS_COLOR_RGB16:
1279         case OMAP_DSS_COLOR_ARGB16:
1280         case OMAP_DSS_COLOR_YUV2:
1281         case OMAP_DSS_COLOR_UYVY:
1282                 return 16;
1283         case OMAP_DSS_COLOR_RGB24P:
1284                 return 24;
1285         case OMAP_DSS_COLOR_RGB24U:
1286         case OMAP_DSS_COLOR_ARGB32:
1287         case OMAP_DSS_COLOR_RGBA32:
1288         case OMAP_DSS_COLOR_RGBX32:
1289                 return 32;
1290         default:
1291                 BUG();
1292         }
1293 }
1294
1295 static s32 pixinc(int pixels, u8 ps)
1296 {
1297         if (pixels == 1)
1298                 return 1;
1299         else if (pixels > 1)
1300                 return 1 + (pixels - 1) * ps;
1301         else if (pixels < 0)
1302                 return 1 - (-pixels + 1) * ps;
1303         else
1304                 BUG();
1305 }
1306
1307 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1308                 u16 screen_width,
1309                 u16 width, u16 height,
1310                 enum omap_color_mode color_mode, bool fieldmode,
1311                 unsigned int field_offset,
1312                 unsigned *offset0, unsigned *offset1,
1313                 s32 *row_inc, s32 *pix_inc)
1314 {
1315         u8 ps;
1316
1317         /* FIXME CLUT formats */
1318         switch (color_mode) {
1319         case OMAP_DSS_COLOR_CLUT1:
1320         case OMAP_DSS_COLOR_CLUT2:
1321         case OMAP_DSS_COLOR_CLUT4:
1322         case OMAP_DSS_COLOR_CLUT8:
1323                 BUG();
1324                 return;
1325         case OMAP_DSS_COLOR_YUV2:
1326         case OMAP_DSS_COLOR_UYVY:
1327                 ps = 4;
1328                 break;
1329         default:
1330                 ps = color_mode_to_bpp(color_mode) / 8;
1331                 break;
1332         }
1333
1334         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1335                         width, height);
1336
1337         /*
1338          * field 0 = even field = bottom field
1339          * field 1 = odd field = top field
1340          */
1341         switch (rotation + mirror * 4) {
1342         case OMAP_DSS_ROT_0:
1343         case OMAP_DSS_ROT_180:
1344                 /*
1345                  * If the pixel format is YUV or UYVY divide the width
1346                  * of the image by 2 for 0 and 180 degree rotation.
1347                  */
1348                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1349                         color_mode == OMAP_DSS_COLOR_UYVY)
1350                         width = width >> 1;
1351         case OMAP_DSS_ROT_90:
1352         case OMAP_DSS_ROT_270:
1353                 *offset1 = 0;
1354                 if (field_offset)
1355                         *offset0 = field_offset * screen_width * ps;
1356                 else
1357                         *offset0 = 0;
1358
1359                 *row_inc = pixinc(1 + (screen_width - width) +
1360                                 (fieldmode ? screen_width : 0),
1361                                 ps);
1362                 *pix_inc = pixinc(1, ps);
1363                 break;
1364
1365         case OMAP_DSS_ROT_0 + 4:
1366         case OMAP_DSS_ROT_180 + 4:
1367                 /* If the pixel format is YUV or UYVY divide the width
1368                  * of the image by 2  for 0 degree and 180 degree
1369                  */
1370                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1371                         color_mode == OMAP_DSS_COLOR_UYVY)
1372                         width = width >> 1;
1373         case OMAP_DSS_ROT_90 + 4:
1374         case OMAP_DSS_ROT_270 + 4:
1375                 *offset1 = 0;
1376                 if (field_offset)
1377                         *offset0 = field_offset * screen_width * ps;
1378                 else
1379                         *offset0 = 0;
1380                 *row_inc = pixinc(1 - (screen_width + width) -
1381                                 (fieldmode ? screen_width : 0),
1382                                 ps);
1383                 *pix_inc = pixinc(1, ps);
1384                 break;
1385
1386         default:
1387                 BUG();
1388         }
1389 }
1390
1391 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1392                 u16 screen_width,
1393                 u16 width, u16 height,
1394                 enum omap_color_mode color_mode, bool fieldmode,
1395                 unsigned int field_offset,
1396                 unsigned *offset0, unsigned *offset1,
1397                 s32 *row_inc, s32 *pix_inc)
1398 {
1399         u8 ps;
1400         u16 fbw, fbh;
1401
1402         /* FIXME CLUT formats */
1403         switch (color_mode) {
1404         case OMAP_DSS_COLOR_CLUT1:
1405         case OMAP_DSS_COLOR_CLUT2:
1406         case OMAP_DSS_COLOR_CLUT4:
1407         case OMAP_DSS_COLOR_CLUT8:
1408                 BUG();
1409                 return;
1410         default:
1411                 ps = color_mode_to_bpp(color_mode) / 8;
1412                 break;
1413         }
1414
1415         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1416                         width, height);
1417
1418         /* width & height are overlay sizes, convert to fb sizes */
1419
1420         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1421                 fbw = width;
1422                 fbh = height;
1423         } else {
1424                 fbw = height;
1425                 fbh = width;
1426         }
1427
1428         /*
1429          * field 0 = even field = bottom field
1430          * field 1 = odd field = top field
1431          */
1432         switch (rotation + mirror * 4) {
1433         case OMAP_DSS_ROT_0:
1434                 *offset1 = 0;
1435                 if (field_offset)
1436                         *offset0 = *offset1 + field_offset * screen_width * ps;
1437                 else
1438                         *offset0 = *offset1;
1439                 *row_inc = pixinc(1 + (screen_width - fbw) +
1440                                 (fieldmode ? screen_width : 0),
1441                                 ps);
1442                 *pix_inc = pixinc(1, ps);
1443                 break;
1444         case OMAP_DSS_ROT_90:
1445                 *offset1 = screen_width * (fbh - 1) * ps;
1446                 if (field_offset)
1447                         *offset0 = *offset1 + field_offset * ps;
1448                 else
1449                         *offset0 = *offset1;
1450                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1451                                 (fieldmode ? 1 : 0), ps);
1452                 *pix_inc = pixinc(-screen_width, ps);
1453                 break;
1454         case OMAP_DSS_ROT_180:
1455                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1456                 if (field_offset)
1457                         *offset0 = *offset1 - field_offset * screen_width * ps;
1458                 else
1459                         *offset0 = *offset1;
1460                 *row_inc = pixinc(-1 -
1461                                 (screen_width - fbw) -
1462                                 (fieldmode ? screen_width : 0),
1463                                 ps);
1464                 *pix_inc = pixinc(-1, ps);
1465                 break;
1466         case OMAP_DSS_ROT_270:
1467                 *offset1 = (fbw - 1) * ps;
1468                 if (field_offset)
1469                         *offset0 = *offset1 - field_offset * ps;
1470                 else
1471                         *offset0 = *offset1;
1472                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1473                                 (fieldmode ? 1 : 0), ps);
1474                 *pix_inc = pixinc(screen_width, ps);
1475                 break;
1476
1477         /* mirroring */
1478         case OMAP_DSS_ROT_0 + 4:
1479                 *offset1 = (fbw - 1) * ps;
1480                 if (field_offset)
1481                         *offset0 = *offset1 + field_offset * screen_width * ps;
1482                 else
1483                         *offset0 = *offset1;
1484                 *row_inc = pixinc(screen_width * 2 - 1 +
1485                                 (fieldmode ? screen_width : 0),
1486                                 ps);
1487                 *pix_inc = pixinc(-1, ps);
1488                 break;
1489
1490         case OMAP_DSS_ROT_90 + 4:
1491                 *offset1 = 0;
1492                 if (field_offset)
1493                         *offset0 = *offset1 + field_offset * ps;
1494                 else
1495                         *offset0 = *offset1;
1496                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1497                                 (fieldmode ? 1 : 0),
1498                                 ps);
1499                 *pix_inc = pixinc(screen_width, ps);
1500                 break;
1501
1502         case OMAP_DSS_ROT_180 + 4:
1503                 *offset1 = screen_width * (fbh - 1) * ps;
1504                 if (field_offset)
1505                         *offset0 = *offset1 - field_offset * screen_width * ps;
1506                 else
1507                         *offset0 = *offset1;
1508                 *row_inc = pixinc(1 - screen_width * 2 -
1509                                 (fieldmode ? screen_width : 0),
1510                                 ps);
1511                 *pix_inc = pixinc(1, ps);
1512                 break;
1513
1514         case OMAP_DSS_ROT_270 + 4:
1515                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1516                 if (field_offset)
1517                         *offset0 = *offset1 - field_offset * ps;
1518                 else
1519                         *offset0 = *offset1;
1520                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1521                                 (fieldmode ? 1 : 0),
1522                                 ps);
1523                 *pix_inc = pixinc(-screen_width, ps);
1524                 break;
1525
1526         default:
1527                 BUG();
1528         }
1529 }
1530
1531 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1532                 u16 height, u16 out_width, u16 out_height,
1533                 enum omap_color_mode color_mode)
1534 {
1535         u32 fclk = 0;
1536         /* FIXME venc pclk? */
1537         u64 tmp, pclk = dispc_pclk_rate(channel);
1538
1539         if (height > out_height) {
1540                 /* FIXME get real display PPL */
1541                 unsigned int ppl = 800;
1542
1543                 tmp = pclk * height * out_width;
1544                 do_div(tmp, 2 * out_height * ppl);
1545                 fclk = tmp;
1546
1547                 if (height > 2 * out_height) {
1548                         if (ppl == out_width)
1549                                 return 0;
1550
1551                         tmp = pclk * (height - 2 * out_height) * out_width;
1552                         do_div(tmp, 2 * out_height * (ppl - out_width));
1553                         fclk = max(fclk, (u32) tmp);
1554                 }
1555         }
1556
1557         if (width > out_width) {
1558                 tmp = pclk * width;
1559                 do_div(tmp, out_width);
1560                 fclk = max(fclk, (u32) tmp);
1561
1562                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1563                         fclk <<= 1;
1564         }
1565
1566         return fclk;
1567 }
1568
1569 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1570                 u16 height, u16 out_width, u16 out_height)
1571 {
1572         unsigned int hf, vf;
1573
1574         /*
1575          * FIXME how to determine the 'A' factor
1576          * for the no downscaling case ?
1577          */
1578
1579         if (width > 3 * out_width)
1580                 hf = 4;
1581         else if (width > 2 * out_width)
1582                 hf = 3;
1583         else if (width > out_width)
1584                 hf = 2;
1585         else
1586                 hf = 1;
1587
1588         if (height > out_height)
1589                 vf = 2;
1590         else
1591                 vf = 1;
1592
1593         /* FIXME venc pclk? */
1594         return dispc_pclk_rate(channel) * vf * hf;
1595 }
1596
1597 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1598 {
1599         enable_clocks(1);
1600         _dispc_set_channel_out(plane, channel_out);
1601         enable_clocks(0);
1602 }
1603
1604 static int _dispc_setup_plane(enum omap_plane plane,
1605                 u32 paddr, u16 screen_width,
1606                 u16 pos_x, u16 pos_y,
1607                 u16 width, u16 height,
1608                 u16 out_width, u16 out_height,
1609                 enum omap_color_mode color_mode,
1610                 bool ilace,
1611                 enum omap_dss_rotation_type rotation_type,
1612                 u8 rotation, int mirror,
1613                 u8 global_alpha, u8 pre_mult_alpha,
1614                 enum omap_channel channel)
1615 {
1616         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1617         bool five_taps = 0;
1618         bool fieldmode = 0;
1619         int cconv = 0;
1620         unsigned offset0, offset1;
1621         s32 row_inc;
1622         s32 pix_inc;
1623         u16 frame_height = height;
1624         unsigned int field_offset = 0;
1625
1626         if (paddr == 0)
1627                 return -EINVAL;
1628
1629         if (ilace && height == out_height)
1630                 fieldmode = 1;
1631
1632         if (ilace) {
1633                 if (fieldmode)
1634                         height /= 2;
1635                 pos_y /= 2;
1636                 out_height /= 2;
1637
1638                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1639                                 "out_height %d\n",
1640                                 height, pos_y, out_height);
1641         }
1642
1643         if (!dss_feat_color_mode_supported(plane, color_mode))
1644                 return -EINVAL;
1645
1646         if (plane == OMAP_DSS_GFX) {
1647                 if (width != out_width || height != out_height)
1648                         return -EINVAL;
1649         } else {
1650                 /* video plane */
1651
1652                 unsigned long fclk = 0;
1653
1654                 if (out_width < width / maxdownscale ||
1655                    out_width > width * 8)
1656                         return -EINVAL;
1657
1658                 if (out_height < height / maxdownscale ||
1659                    out_height > height * 8)
1660                         return -EINVAL;
1661
1662                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1663                         color_mode == OMAP_DSS_COLOR_UYVY)
1664                         cconv = 1;
1665
1666                 /* Must use 5-tap filter? */
1667                 five_taps = height > out_height * 2;
1668
1669                 if (!five_taps) {
1670                         fclk = calc_fclk(channel, width, height, out_width,
1671                                         out_height);
1672
1673                         /* Try 5-tap filter if 3-tap fclk is too high */
1674                         if (cpu_is_omap34xx() && height > out_height &&
1675                                         fclk > dispc_fclk_rate())
1676                                 five_taps = true;
1677                 }
1678
1679                 if (width > (2048 >> five_taps)) {
1680                         DSSERR("failed to set up scaling, fclk too low\n");
1681                         return -EINVAL;
1682                 }
1683
1684                 if (five_taps)
1685                         fclk = calc_fclk_five_taps(channel, width, height,
1686                                         out_width, out_height, color_mode);
1687
1688                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1689                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1690
1691                 if (!fclk || fclk > dispc_fclk_rate()) {
1692                         DSSERR("failed to set up scaling, "
1693                                         "required fclk rate = %lu Hz, "
1694                                         "current fclk rate = %lu Hz\n",
1695                                         fclk, dispc_fclk_rate());
1696                         return -EINVAL;
1697                 }
1698         }
1699
1700         if (ilace && !fieldmode) {
1701                 /*
1702                  * when downscaling the bottom field may have to start several
1703                  * source lines below the top field. Unfortunately ACCUI
1704                  * registers will only hold the fractional part of the offset
1705                  * so the integer part must be added to the base address of the
1706                  * bottom field.
1707                  */
1708                 if (!height || height == out_height)
1709                         field_offset = 0;
1710                 else
1711                         field_offset = height / out_height / 2;
1712         }
1713
1714         /* Fields are independent but interleaved in memory. */
1715         if (fieldmode)
1716                 field_offset = 1;
1717
1718         if (rotation_type == OMAP_DSS_ROT_DMA)
1719                 calc_dma_rotation_offset(rotation, mirror,
1720                                 screen_width, width, frame_height, color_mode,
1721                                 fieldmode, field_offset,
1722                                 &offset0, &offset1, &row_inc, &pix_inc);
1723         else
1724                 calc_vrfb_rotation_offset(rotation, mirror,
1725                                 screen_width, width, frame_height, color_mode,
1726                                 fieldmode, field_offset,
1727                                 &offset0, &offset1, &row_inc, &pix_inc);
1728
1729         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1730                         offset0, offset1, row_inc, pix_inc);
1731
1732         _dispc_set_color_mode(plane, color_mode);
1733
1734         _dispc_set_plane_ba0(plane, paddr + offset0);
1735         _dispc_set_plane_ba1(plane, paddr + offset1);
1736
1737         _dispc_set_row_inc(plane, row_inc);
1738         _dispc_set_pix_inc(plane, pix_inc);
1739
1740         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1741                         out_width, out_height);
1742
1743         _dispc_set_plane_pos(plane, pos_x, pos_y);
1744
1745         _dispc_set_pic_size(plane, width, height);
1746
1747         if (plane != OMAP_DSS_GFX) {
1748                 _dispc_set_scaling(plane, width, height,
1749                                    out_width, out_height,
1750                                    ilace, five_taps, fieldmode);
1751                 _dispc_set_vid_size(plane, out_width, out_height);
1752                 _dispc_set_vid_color_conv(plane, cconv);
1753         }
1754
1755         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1756
1757         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1758         _dispc_setup_global_alpha(plane, global_alpha);
1759
1760         return 0;
1761 }
1762
1763 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1764 {
1765         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1766 }
1767
1768 static void dispc_disable_isr(void *data, u32 mask)
1769 {
1770         struct completion *compl = data;
1771         complete(compl);
1772 }
1773
1774 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1775 {
1776         if (channel == OMAP_DSS_CHANNEL_LCD2)
1777                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1778         else
1779                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1780 }
1781
1782 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1783 {
1784         struct completion frame_done_completion;
1785         bool is_on;
1786         int r;
1787         u32 irq;
1788
1789         enable_clocks(1);
1790
1791         /* When we disable LCD output, we need to wait until frame is done.
1792          * Otherwise the DSS is still working, and turning off the clocks
1793          * prevents DSS from going to OFF mode */
1794         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1795                         REG_GET(DISPC_CONTROL2, 0, 0) :
1796                         REG_GET(DISPC_CONTROL, 0, 0);
1797
1798         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1799                         DISPC_IRQ_FRAMEDONE;
1800
1801         if (!enable && is_on) {
1802                 init_completion(&frame_done_completion);
1803
1804                 r = omap_dispc_register_isr(dispc_disable_isr,
1805                                 &frame_done_completion, irq);
1806
1807                 if (r)
1808                         DSSERR("failed to register FRAMEDONE isr\n");
1809         }
1810
1811         _enable_lcd_out(channel, enable);
1812
1813         if (!enable && is_on) {
1814                 if (!wait_for_completion_timeout(&frame_done_completion,
1815                                         msecs_to_jiffies(100)))
1816                         DSSERR("timeout waiting for FRAME DONE\n");
1817
1818                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1819                                 &frame_done_completion, irq);
1820
1821                 if (r)
1822                         DSSERR("failed to unregister FRAMEDONE isr\n");
1823         }
1824
1825         enable_clocks(0);
1826 }
1827
1828 static void _enable_digit_out(bool enable)
1829 {
1830         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1831 }
1832
1833 static void dispc_enable_digit_out(bool enable)
1834 {
1835         struct completion frame_done_completion;
1836         int r;
1837
1838         enable_clocks(1);
1839
1840         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1841                 enable_clocks(0);
1842                 return;
1843         }
1844
1845         if (enable) {
1846                 unsigned long flags;
1847                 /* When we enable digit output, we'll get an extra digit
1848                  * sync lost interrupt, that we need to ignore */
1849                 spin_lock_irqsave(&dispc.irq_lock, flags);
1850                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1851                 _omap_dispc_set_irqs();
1852                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1853         }
1854
1855         /* When we disable digit output, we need to wait until fields are done.
1856          * Otherwise the DSS is still working, and turning off the clocks
1857          * prevents DSS from going to OFF mode. And when enabling, we need to
1858          * wait for the extra sync losts */
1859         init_completion(&frame_done_completion);
1860
1861         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1862                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1863         if (r)
1864                 DSSERR("failed to register EVSYNC isr\n");
1865
1866         _enable_digit_out(enable);
1867
1868         /* XXX I understand from TRM that we should only wait for the
1869          * current field to complete. But it seems we have to wait
1870          * for both fields */
1871         if (!wait_for_completion_timeout(&frame_done_completion,
1872                                 msecs_to_jiffies(100)))
1873                 DSSERR("timeout waiting for EVSYNC\n");
1874
1875         if (!wait_for_completion_timeout(&frame_done_completion,
1876                                 msecs_to_jiffies(100)))
1877                 DSSERR("timeout waiting for EVSYNC\n");
1878
1879         r = omap_dispc_unregister_isr(dispc_disable_isr,
1880                         &frame_done_completion,
1881                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1882         if (r)
1883                 DSSERR("failed to unregister EVSYNC isr\n");
1884
1885         if (enable) {
1886                 unsigned long flags;
1887                 spin_lock_irqsave(&dispc.irq_lock, flags);
1888                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1889                 if (dss_has_feature(FEAT_MGR_LCD2))
1890                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1891                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1892                 _omap_dispc_set_irqs();
1893                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1894         }
1895
1896         enable_clocks(0);
1897 }
1898
1899 bool dispc_is_channel_enabled(enum omap_channel channel)
1900 {
1901         if (channel == OMAP_DSS_CHANNEL_LCD)
1902                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1903         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1904                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1905         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1906                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
1907         else
1908                 BUG();
1909 }
1910
1911 void dispc_enable_channel(enum omap_channel channel, bool enable)
1912 {
1913         if (channel == OMAP_DSS_CHANNEL_LCD ||
1914                         channel == OMAP_DSS_CHANNEL_LCD2)
1915                 dispc_enable_lcd_out(channel, enable);
1916         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1917                 dispc_enable_digit_out(enable);
1918         else
1919                 BUG();
1920 }
1921
1922 void dispc_lcd_enable_signal_polarity(bool act_high)
1923 {
1924         if (!dss_has_feature(FEAT_LCDENABLEPOL))
1925                 return;
1926
1927         enable_clocks(1);
1928         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1929         enable_clocks(0);
1930 }
1931
1932 void dispc_lcd_enable_signal(bool enable)
1933 {
1934         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1935                 return;
1936
1937         enable_clocks(1);
1938         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1939         enable_clocks(0);
1940 }
1941
1942 void dispc_pck_free_enable(bool enable)
1943 {
1944         if (!dss_has_feature(FEAT_PCKFREEENABLE))
1945                 return;
1946
1947         enable_clocks(1);
1948         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1949         enable_clocks(0);
1950 }
1951
1952 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
1953 {
1954         enable_clocks(1);
1955         if (channel == OMAP_DSS_CHANNEL_LCD2)
1956                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1957         else
1958                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1959         enable_clocks(0);
1960 }
1961
1962
1963 void dispc_set_lcd_display_type(enum omap_channel channel,
1964                 enum omap_lcd_display_type type)
1965 {
1966         int mode;
1967
1968         switch (type) {
1969         case OMAP_DSS_LCD_DISPLAY_STN:
1970                 mode = 0;
1971                 break;
1972
1973         case OMAP_DSS_LCD_DISPLAY_TFT:
1974                 mode = 1;
1975                 break;
1976
1977         default:
1978                 BUG();
1979                 return;
1980         }
1981
1982         enable_clocks(1);
1983         if (channel == OMAP_DSS_CHANNEL_LCD2)
1984                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1985         else
1986                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1987         enable_clocks(0);
1988 }
1989
1990 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1991 {
1992         enable_clocks(1);
1993         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1994         enable_clocks(0);
1995 }
1996
1997
1998 void dispc_set_default_color(enum omap_channel channel, u32 color)
1999 {
2000         enable_clocks(1);
2001         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2002         enable_clocks(0);
2003 }
2004
2005 u32 dispc_get_default_color(enum omap_channel channel)
2006 {
2007         u32 l;
2008
2009         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2010                 channel != OMAP_DSS_CHANNEL_LCD &&
2011                 channel != OMAP_DSS_CHANNEL_LCD2);
2012
2013         enable_clocks(1);
2014         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2015         enable_clocks(0);
2016
2017         return l;
2018 }
2019
2020 void dispc_set_trans_key(enum omap_channel ch,
2021                 enum omap_dss_trans_key_type type,
2022                 u32 trans_key)
2023 {
2024         enable_clocks(1);
2025         if (ch == OMAP_DSS_CHANNEL_LCD)
2026                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2027         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2028                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2029         else /* OMAP_DSS_CHANNEL_LCD2 */
2030                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2031
2032         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2033         enable_clocks(0);
2034 }
2035
2036 void dispc_get_trans_key(enum omap_channel ch,
2037                 enum omap_dss_trans_key_type *type,
2038                 u32 *trans_key)
2039 {
2040         enable_clocks(1);
2041         if (type) {
2042                 if (ch == OMAP_DSS_CHANNEL_LCD)
2043                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2044                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2045                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2046                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2047                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2048                 else
2049                         BUG();
2050         }
2051
2052         if (trans_key)
2053                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2054         enable_clocks(0);
2055 }
2056
2057 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2058 {
2059         enable_clocks(1);
2060         if (ch == OMAP_DSS_CHANNEL_LCD)
2061                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2062         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2063                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2064         else /* OMAP_DSS_CHANNEL_LCD2 */
2065                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2066         enable_clocks(0);
2067 }
2068 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2069 {
2070         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2071                 return;
2072
2073         enable_clocks(1);
2074         if (ch == OMAP_DSS_CHANNEL_LCD)
2075                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2076         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2077                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2078         else /* OMAP_DSS_CHANNEL_LCD2 */
2079                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2080         enable_clocks(0);
2081 }
2082 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2083 {
2084         bool enabled;
2085
2086         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2087                 return false;
2088
2089         enable_clocks(1);
2090         if (ch == OMAP_DSS_CHANNEL_LCD)
2091                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2092         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2093                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2094         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2095                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2096         else
2097                 BUG();
2098         enable_clocks(0);
2099
2100         return enabled;
2101 }
2102
2103
2104 bool dispc_trans_key_enabled(enum omap_channel ch)
2105 {
2106         bool enabled;
2107
2108         enable_clocks(1);
2109         if (ch == OMAP_DSS_CHANNEL_LCD)
2110                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2111         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2112                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2113         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2114                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2115         else
2116                 BUG();
2117         enable_clocks(0);
2118
2119         return enabled;
2120 }
2121
2122
2123 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2124 {
2125         int code;
2126
2127         switch (data_lines) {
2128         case 12:
2129                 code = 0;
2130                 break;
2131         case 16:
2132                 code = 1;
2133                 break;
2134         case 18:
2135                 code = 2;
2136                 break;
2137         case 24:
2138                 code = 3;
2139                 break;
2140         default:
2141                 BUG();
2142                 return;
2143         }
2144
2145         enable_clocks(1);
2146         if (channel == OMAP_DSS_CHANNEL_LCD2)
2147                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2148         else
2149                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2150         enable_clocks(0);
2151 }
2152
2153 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2154                 enum omap_parallel_interface_mode mode)
2155 {
2156         u32 l;
2157         int stallmode;
2158         int gpout0 = 1;
2159         int gpout1;
2160
2161         switch (mode) {
2162         case OMAP_DSS_PARALLELMODE_BYPASS:
2163                 stallmode = 0;
2164                 gpout1 = 1;
2165                 break;
2166
2167         case OMAP_DSS_PARALLELMODE_RFBI:
2168                 stallmode = 1;
2169                 gpout1 = 0;
2170                 break;
2171
2172         case OMAP_DSS_PARALLELMODE_DSI:
2173                 stallmode = 1;
2174                 gpout1 = 1;
2175                 break;
2176
2177         default:
2178                 BUG();
2179                 return;
2180         }
2181
2182         enable_clocks(1);
2183
2184         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2185                 l = dispc_read_reg(DISPC_CONTROL2);
2186                 l = FLD_MOD(l, stallmode, 11, 11);
2187                 dispc_write_reg(DISPC_CONTROL2, l);
2188         } else {
2189                 l = dispc_read_reg(DISPC_CONTROL);
2190                 l = FLD_MOD(l, stallmode, 11, 11);
2191                 l = FLD_MOD(l, gpout0, 15, 15);
2192                 l = FLD_MOD(l, gpout1, 16, 16);
2193                 dispc_write_reg(DISPC_CONTROL, l);
2194         }
2195
2196         enable_clocks(0);
2197 }
2198
2199 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2200                 int vsw, int vfp, int vbp)
2201 {
2202         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2203                 if (hsw < 1 || hsw > 64 ||
2204                                 hfp < 1 || hfp > 256 ||
2205                                 hbp < 1 || hbp > 256 ||
2206                                 vsw < 1 || vsw > 64 ||
2207                                 vfp < 0 || vfp > 255 ||
2208                                 vbp < 0 || vbp > 255)
2209                         return false;
2210         } else {
2211                 if (hsw < 1 || hsw > 256 ||
2212                                 hfp < 1 || hfp > 4096 ||
2213                                 hbp < 1 || hbp > 4096 ||
2214                                 vsw < 1 || vsw > 256 ||
2215                                 vfp < 0 || vfp > 4095 ||
2216                                 vbp < 0 || vbp > 4095)
2217                         return false;
2218         }
2219
2220         return true;
2221 }
2222
2223 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2224 {
2225         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2226                         timings->hbp, timings->vsw,
2227                         timings->vfp, timings->vbp);
2228 }
2229
2230 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2231                 int hfp, int hbp, int vsw, int vfp, int vbp)
2232 {
2233         u32 timing_h, timing_v;
2234
2235         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2236                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2237                         FLD_VAL(hbp-1, 27, 20);
2238
2239                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2240                         FLD_VAL(vbp, 27, 20);
2241         } else {
2242                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2243                         FLD_VAL(hbp-1, 31, 20);
2244
2245                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2246                         FLD_VAL(vbp, 31, 20);
2247         }
2248
2249         enable_clocks(1);
2250         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2251         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2252         enable_clocks(0);
2253 }
2254
2255 /* change name to mode? */
2256 void dispc_set_lcd_timings(enum omap_channel channel,
2257                 struct omap_video_timings *timings)
2258 {
2259         unsigned xtot, ytot;
2260         unsigned long ht, vt;
2261
2262         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2263                                 timings->hbp, timings->vsw,
2264                                 timings->vfp, timings->vbp))
2265                 BUG();
2266
2267         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2268                         timings->hbp, timings->vsw, timings->vfp,
2269                         timings->vbp);
2270
2271         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2272
2273         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2274         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2275
2276         ht = (timings->pixel_clock * 1000) / xtot;
2277         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2278
2279         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2280                         timings->y_res);
2281         DSSDBG("pck %u\n", timings->pixel_clock);
2282         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2283                         timings->hsw, timings->hfp, timings->hbp,
2284                         timings->vsw, timings->vfp, timings->vbp);
2285
2286         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2287 }
2288
2289 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2290                 u16 pck_div)
2291 {
2292         BUG_ON(lck_div < 1);
2293         BUG_ON(pck_div < 2);
2294
2295         enable_clocks(1);
2296         dispc_write_reg(DISPC_DIVISOR(channel),
2297                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2298         enable_clocks(0);
2299 }
2300
2301 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2302                 int *pck_div)
2303 {
2304         u32 l;
2305         l = dispc_read_reg(DISPC_DIVISOR(channel));
2306         *lck_div = FLD_GET(l, 23, 16);
2307         *pck_div = FLD_GET(l, 7, 0);
2308 }
2309
2310 unsigned long dispc_fclk_rate(void)
2311 {
2312         unsigned long r = 0;
2313
2314         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2315                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2316         else
2317 #ifdef CONFIG_OMAP2_DSS_DSI
2318                 r = dsi_get_dsi1_pll_rate();
2319 #else
2320         BUG();
2321 #endif
2322         return r;
2323 }
2324
2325 unsigned long dispc_lclk_rate(enum omap_channel channel)
2326 {
2327         int lcd;
2328         unsigned long r;
2329         u32 l;
2330
2331         l = dispc_read_reg(DISPC_DIVISOR(channel));
2332
2333         lcd = FLD_GET(l, 23, 16);
2334
2335         r = dispc_fclk_rate();
2336
2337         return r / lcd;
2338 }
2339
2340 unsigned long dispc_pclk_rate(enum omap_channel channel)
2341 {
2342         int lcd, pcd;
2343         unsigned long r;
2344         u32 l;
2345
2346         l = dispc_read_reg(DISPC_DIVISOR(channel));
2347
2348         lcd = FLD_GET(l, 23, 16);
2349         pcd = FLD_GET(l, 7, 0);
2350
2351         r = dispc_fclk_rate();
2352
2353         return r / lcd / pcd;
2354 }
2355
2356 void dispc_dump_clocks(struct seq_file *s)
2357 {
2358         int lcd, pcd;
2359
2360         enable_clocks(1);
2361
2362         seq_printf(s, "- DISPC -\n");
2363
2364         seq_printf(s, "dispc fclk source = %s\n",
2365                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2366                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2367
2368         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2369
2370         seq_printf(s, "- LCD1 -\n");
2371
2372         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2373
2374         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2375                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2376         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2377                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2378         if (dss_has_feature(FEAT_MGR_LCD2)) {
2379                 seq_printf(s, "- LCD2 -\n");
2380
2381                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2382
2383                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2384                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2385                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2386                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2387         }
2388         enable_clocks(0);
2389 }
2390
2391 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2392 void dispc_dump_irqs(struct seq_file *s)
2393 {
2394         unsigned long flags;
2395         struct dispc_irq_stats stats;
2396
2397         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2398
2399         stats = dispc.irq_stats;
2400         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2401         dispc.irq_stats.last_reset = jiffies;
2402
2403         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2404
2405         seq_printf(s, "period %u ms\n",
2406                         jiffies_to_msecs(jiffies - stats.last_reset));
2407
2408         seq_printf(s, "irqs %d\n", stats.irq_count);
2409 #define PIS(x) \
2410         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2411
2412         PIS(FRAMEDONE);
2413         PIS(VSYNC);
2414         PIS(EVSYNC_EVEN);
2415         PIS(EVSYNC_ODD);
2416         PIS(ACBIAS_COUNT_STAT);
2417         PIS(PROG_LINE_NUM);
2418         PIS(GFX_FIFO_UNDERFLOW);
2419         PIS(GFX_END_WIN);
2420         PIS(PAL_GAMMA_MASK);
2421         PIS(OCP_ERR);
2422         PIS(VID1_FIFO_UNDERFLOW);
2423         PIS(VID1_END_WIN);
2424         PIS(VID2_FIFO_UNDERFLOW);
2425         PIS(VID2_END_WIN);
2426         PIS(SYNC_LOST);
2427         PIS(SYNC_LOST_DIGIT);
2428         PIS(WAKEUP);
2429         if (dss_has_feature(FEAT_MGR_LCD2)) {
2430                 PIS(FRAMEDONE2);
2431                 PIS(VSYNC2);
2432                 PIS(ACBIAS_COUNT_STAT2);
2433                 PIS(SYNC_LOST2);
2434         }
2435 #undef PIS
2436 }
2437 #endif
2438
2439 void dispc_dump_regs(struct seq_file *s)
2440 {
2441 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2442
2443         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2444
2445         DUMPREG(DISPC_REVISION);
2446         DUMPREG(DISPC_SYSCONFIG);
2447         DUMPREG(DISPC_SYSSTATUS);
2448         DUMPREG(DISPC_IRQSTATUS);
2449         DUMPREG(DISPC_IRQENABLE);
2450         DUMPREG(DISPC_CONTROL);
2451         DUMPREG(DISPC_CONFIG);
2452         DUMPREG(DISPC_CAPABLE);
2453         DUMPREG(DISPC_DEFAULT_COLOR(0));
2454         DUMPREG(DISPC_DEFAULT_COLOR(1));
2455         DUMPREG(DISPC_TRANS_COLOR(0));
2456         DUMPREG(DISPC_TRANS_COLOR(1));
2457         DUMPREG(DISPC_LINE_STATUS);
2458         DUMPREG(DISPC_LINE_NUMBER);
2459         DUMPREG(DISPC_TIMING_H(0));
2460         DUMPREG(DISPC_TIMING_V(0));
2461         DUMPREG(DISPC_POL_FREQ(0));
2462         DUMPREG(DISPC_DIVISOR(0));
2463         DUMPREG(DISPC_GLOBAL_ALPHA);
2464         DUMPREG(DISPC_SIZE_DIG);
2465         DUMPREG(DISPC_SIZE_LCD(0));
2466         if (dss_has_feature(FEAT_MGR_LCD2)) {
2467                 DUMPREG(DISPC_CONTROL2);
2468                 DUMPREG(DISPC_CONFIG2);
2469                 DUMPREG(DISPC_DEFAULT_COLOR(2));
2470                 DUMPREG(DISPC_TRANS_COLOR(2));
2471                 DUMPREG(DISPC_TIMING_H(2));
2472                 DUMPREG(DISPC_TIMING_V(2));
2473                 DUMPREG(DISPC_POL_FREQ(2));
2474                 DUMPREG(DISPC_DIVISOR(2));
2475                 DUMPREG(DISPC_SIZE_LCD(2));
2476         }
2477
2478         DUMPREG(DISPC_GFX_BA0);
2479         DUMPREG(DISPC_GFX_BA1);
2480         DUMPREG(DISPC_GFX_POSITION);
2481         DUMPREG(DISPC_GFX_SIZE);
2482         DUMPREG(DISPC_GFX_ATTRIBUTES);
2483         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2484         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2485         DUMPREG(DISPC_GFX_ROW_INC);
2486         DUMPREG(DISPC_GFX_PIXEL_INC);
2487         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2488         DUMPREG(DISPC_GFX_TABLE_BA);
2489
2490         DUMPREG(DISPC_DATA_CYCLE1(0));
2491         DUMPREG(DISPC_DATA_CYCLE2(0));
2492         DUMPREG(DISPC_DATA_CYCLE3(0));
2493
2494         DUMPREG(DISPC_CPR_COEF_R(0));
2495         DUMPREG(DISPC_CPR_COEF_G(0));
2496         DUMPREG(DISPC_CPR_COEF_B(0));
2497         if (dss_has_feature(FEAT_MGR_LCD2)) {
2498                 DUMPREG(DISPC_DATA_CYCLE1(2));
2499                 DUMPREG(DISPC_DATA_CYCLE2(2));
2500                 DUMPREG(DISPC_DATA_CYCLE3(2));
2501
2502                 DUMPREG(DISPC_CPR_COEF_R(2));
2503                 DUMPREG(DISPC_CPR_COEF_G(2));
2504                 DUMPREG(DISPC_CPR_COEF_B(2));
2505         }
2506
2507         DUMPREG(DISPC_GFX_PRELOAD);
2508
2509         DUMPREG(DISPC_VID_BA0(0));
2510         DUMPREG(DISPC_VID_BA1(0));
2511         DUMPREG(DISPC_VID_POSITION(0));
2512         DUMPREG(DISPC_VID_SIZE(0));
2513         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2514         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2515         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2516         DUMPREG(DISPC_VID_ROW_INC(0));
2517         DUMPREG(DISPC_VID_PIXEL_INC(0));
2518         DUMPREG(DISPC_VID_FIR(0));
2519         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2520         DUMPREG(DISPC_VID_ACCU0(0));
2521         DUMPREG(DISPC_VID_ACCU1(0));
2522
2523         DUMPREG(DISPC_VID_BA0(1));
2524         DUMPREG(DISPC_VID_BA1(1));
2525         DUMPREG(DISPC_VID_POSITION(1));
2526         DUMPREG(DISPC_VID_SIZE(1));
2527         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2528         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2529         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2530         DUMPREG(DISPC_VID_ROW_INC(1));
2531         DUMPREG(DISPC_VID_PIXEL_INC(1));
2532         DUMPREG(DISPC_VID_FIR(1));
2533         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2534         DUMPREG(DISPC_VID_ACCU0(1));
2535         DUMPREG(DISPC_VID_ACCU1(1));
2536
2537         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2538         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2539         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2540         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2541         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2542         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2543         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2544         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2545         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2546         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2547         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2548         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2549         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2550         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2551         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2552         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2553         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2554         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2555         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2556         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2557         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2558         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2559         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2560         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2561         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2562         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2563         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2564         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2565         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2566
2567         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2568         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2569         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2570         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2571         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2572         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2573         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2574         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2575         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2576         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2577         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2578         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2579         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2580         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2581         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2582         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2583         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2584         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2585         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2586         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2587         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2588         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2589         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2590         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2591         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2592         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2593         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2594         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2595         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2596
2597         DUMPREG(DISPC_VID_PRELOAD(0));
2598         DUMPREG(DISPC_VID_PRELOAD(1));
2599
2600         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2601 #undef DUMPREG
2602 }
2603
2604 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2605                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2606 {
2607         u32 l = 0;
2608
2609         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2610                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2611
2612         l |= FLD_VAL(onoff, 17, 17);
2613         l |= FLD_VAL(rf, 16, 16);
2614         l |= FLD_VAL(ieo, 15, 15);
2615         l |= FLD_VAL(ipc, 14, 14);
2616         l |= FLD_VAL(ihs, 13, 13);
2617         l |= FLD_VAL(ivs, 12, 12);
2618         l |= FLD_VAL(acbi, 11, 8);
2619         l |= FLD_VAL(acb, 7, 0);
2620
2621         enable_clocks(1);
2622         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2623         enable_clocks(0);
2624 }
2625
2626 void dispc_set_pol_freq(enum omap_channel channel,
2627                 enum omap_panel_config config, u8 acbi, u8 acb)
2628 {
2629         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2630                         (config & OMAP_DSS_LCD_RF) != 0,
2631                         (config & OMAP_DSS_LCD_IEO) != 0,
2632                         (config & OMAP_DSS_LCD_IPC) != 0,
2633                         (config & OMAP_DSS_LCD_IHS) != 0,
2634                         (config & OMAP_DSS_LCD_IVS) != 0,
2635                         acbi, acb);
2636 }
2637
2638 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2639 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2640                 struct dispc_clock_info *cinfo)
2641 {
2642         u16 pcd_min = is_tft ? 2 : 3;
2643         unsigned long best_pck;
2644         u16 best_ld, cur_ld;
2645         u16 best_pd, cur_pd;
2646
2647         best_pck = 0;
2648         best_ld = 0;
2649         best_pd = 0;
2650
2651         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2652                 unsigned long lck = fck / cur_ld;
2653
2654                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2655                         unsigned long pck = lck / cur_pd;
2656                         long old_delta = abs(best_pck - req_pck);
2657                         long new_delta = abs(pck - req_pck);
2658
2659                         if (best_pck == 0 || new_delta < old_delta) {
2660                                 best_pck = pck;
2661                                 best_ld = cur_ld;
2662                                 best_pd = cur_pd;
2663
2664                                 if (pck == req_pck)
2665                                         goto found;
2666                         }
2667
2668                         if (pck < req_pck)
2669                                 break;
2670                 }
2671
2672                 if (lck / pcd_min < req_pck)
2673                         break;
2674         }
2675
2676 found:
2677         cinfo->lck_div = best_ld;
2678         cinfo->pck_div = best_pd;
2679         cinfo->lck = fck / cinfo->lck_div;
2680         cinfo->pck = cinfo->lck / cinfo->pck_div;
2681 }
2682
2683 /* calculate clock rates using dividers in cinfo */
2684 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2685                 struct dispc_clock_info *cinfo)
2686 {
2687         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2688                 return -EINVAL;
2689         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2690                 return -EINVAL;
2691
2692         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2693         cinfo->pck = cinfo->lck / cinfo->pck_div;
2694
2695         return 0;
2696 }
2697
2698 int dispc_set_clock_div(enum omap_channel channel,
2699                 struct dispc_clock_info *cinfo)
2700 {
2701         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2702         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2703
2704         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2705
2706         return 0;
2707 }
2708
2709 int dispc_get_clock_div(enum omap_channel channel,
2710                 struct dispc_clock_info *cinfo)
2711 {
2712         unsigned long fck;
2713
2714         fck = dispc_fclk_rate();
2715
2716         cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16);
2717         cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0);
2718
2719         cinfo->lck = fck / cinfo->lck_div;
2720         cinfo->pck = cinfo->lck / cinfo->pck_div;
2721
2722         return 0;
2723 }
2724
2725 /* dispc.irq_lock has to be locked by the caller */
2726 static void _omap_dispc_set_irqs(void)
2727 {
2728         u32 mask;
2729         u32 old_mask;
2730         int i;
2731         struct omap_dispc_isr_data *isr_data;
2732
2733         mask = dispc.irq_error_mask;
2734
2735         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2736                 isr_data = &dispc.registered_isr[i];
2737
2738                 if (isr_data->isr == NULL)
2739                         continue;
2740
2741                 mask |= isr_data->mask;
2742         }
2743
2744         enable_clocks(1);
2745
2746         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2747         /* clear the irqstatus for newly enabled irqs */
2748         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2749
2750         dispc_write_reg(DISPC_IRQENABLE, mask);
2751
2752         enable_clocks(0);
2753 }
2754
2755 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2756 {
2757         int i;
2758         int ret;
2759         unsigned long flags;
2760         struct omap_dispc_isr_data *isr_data;
2761
2762         if (isr == NULL)
2763                 return -EINVAL;
2764
2765         spin_lock_irqsave(&dispc.irq_lock, flags);
2766
2767         /* check for duplicate entry */
2768         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2769                 isr_data = &dispc.registered_isr[i];
2770                 if (isr_data->isr == isr && isr_data->arg == arg &&
2771                                 isr_data->mask == mask) {
2772                         ret = -EINVAL;
2773                         goto err;
2774                 }
2775         }
2776
2777         isr_data = NULL;
2778         ret = -EBUSY;
2779
2780         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2781                 isr_data = &dispc.registered_isr[i];
2782
2783                 if (isr_data->isr != NULL)
2784                         continue;
2785
2786                 isr_data->isr = isr;
2787                 isr_data->arg = arg;
2788                 isr_data->mask = mask;
2789                 ret = 0;
2790
2791                 break;
2792         }
2793
2794         _omap_dispc_set_irqs();
2795
2796         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2797
2798         return 0;
2799 err:
2800         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2801
2802         return ret;
2803 }
2804 EXPORT_SYMBOL(omap_dispc_register_isr);
2805
2806 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2807 {
2808         int i;
2809         unsigned long flags;
2810         int ret = -EINVAL;
2811         struct omap_dispc_isr_data *isr_data;
2812
2813         spin_lock_irqsave(&dispc.irq_lock, flags);
2814
2815         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2816                 isr_data = &dispc.registered_isr[i];
2817                 if (isr_data->isr != isr || isr_data->arg != arg ||
2818                                 isr_data->mask != mask)
2819                         continue;
2820
2821                 /* found the correct isr */
2822
2823                 isr_data->isr = NULL;
2824                 isr_data->arg = NULL;
2825                 isr_data->mask = 0;
2826
2827                 ret = 0;
2828                 break;
2829         }
2830
2831         if (ret == 0)
2832                 _omap_dispc_set_irqs();
2833
2834         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2835
2836         return ret;
2837 }
2838 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2839
2840 #ifdef DEBUG
2841 static void print_irq_status(u32 status)
2842 {
2843         if ((status & dispc.irq_error_mask) == 0)
2844                 return;
2845
2846         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2847
2848 #define PIS(x) \
2849         if (status & DISPC_IRQ_##x) \
2850                 printk(#x " ");
2851         PIS(GFX_FIFO_UNDERFLOW);
2852         PIS(OCP_ERR);
2853         PIS(VID1_FIFO_UNDERFLOW);
2854         PIS(VID2_FIFO_UNDERFLOW);
2855         PIS(SYNC_LOST);
2856         PIS(SYNC_LOST_DIGIT);
2857         if (dss_has_feature(FEAT_MGR_LCD2))
2858                 PIS(SYNC_LOST2);
2859 #undef PIS
2860
2861         printk("\n");
2862 }
2863 #endif
2864
2865 /* Called from dss.c. Note that we don't touch clocks here,
2866  * but we presume they are on because we got an IRQ. However,
2867  * an irq handler may turn the clocks off, so we may not have
2868  * clock later in the function. */
2869 void dispc_irq_handler(void)
2870 {
2871         int i;
2872         u32 irqstatus;
2873         u32 handledirqs = 0;
2874         u32 unhandled_errors;
2875         struct omap_dispc_isr_data *isr_data;
2876         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2877
2878         spin_lock(&dispc.irq_lock);
2879
2880         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2881
2882 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2883         spin_lock(&dispc.irq_stats_lock);
2884         dispc.irq_stats.irq_count++;
2885         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2886         spin_unlock(&dispc.irq_stats_lock);
2887 #endif
2888
2889 #ifdef DEBUG
2890         if (dss_debug)
2891                 print_irq_status(irqstatus);
2892 #endif
2893         /* Ack the interrupt. Do it here before clocks are possibly turned
2894          * off */
2895         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2896         /* flush posted write */
2897         dispc_read_reg(DISPC_IRQSTATUS);
2898
2899         /* make a copy and unlock, so that isrs can unregister
2900          * themselves */
2901         memcpy(registered_isr, dispc.registered_isr,
2902                         sizeof(registered_isr));
2903
2904         spin_unlock(&dispc.irq_lock);
2905
2906         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2907                 isr_data = &registered_isr[i];
2908
2909                 if (!isr_data->isr)
2910                         continue;
2911
2912                 if (isr_data->mask & irqstatus) {
2913                         isr_data->isr(isr_data->arg, irqstatus);
2914                         handledirqs |= isr_data->mask;
2915                 }
2916         }
2917
2918         spin_lock(&dispc.irq_lock);
2919
2920         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2921
2922         if (unhandled_errors) {
2923                 dispc.error_irqs |= unhandled_errors;
2924
2925                 dispc.irq_error_mask &= ~unhandled_errors;
2926                 _omap_dispc_set_irqs();
2927
2928                 schedule_work(&dispc.error_work);
2929         }
2930
2931         spin_unlock(&dispc.irq_lock);
2932 }
2933
2934 static void dispc_error_worker(struct work_struct *work)
2935 {
2936         int i;
2937         u32 errors;
2938         unsigned long flags;
2939
2940         spin_lock_irqsave(&dispc.irq_lock, flags);
2941         errors = dispc.error_irqs;
2942         dispc.error_irqs = 0;
2943         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2944
2945         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2946                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2947                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2948                         struct omap_overlay *ovl;
2949                         ovl = omap_dss_get_overlay(i);
2950
2951                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2952                                 continue;
2953
2954                         if (ovl->id == 0) {
2955                                 dispc_enable_plane(ovl->id, 0);
2956                                 dispc_go(ovl->manager->id);
2957                                 mdelay(50);
2958                                 break;
2959                         }
2960                 }
2961         }
2962
2963         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2964                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2965                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2966                         struct omap_overlay *ovl;
2967                         ovl = omap_dss_get_overlay(i);
2968
2969                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2970                                 continue;
2971
2972                         if (ovl->id == 1) {
2973                                 dispc_enable_plane(ovl->id, 0);
2974                                 dispc_go(ovl->manager->id);
2975                                 mdelay(50);
2976                                 break;
2977                         }
2978                 }
2979         }
2980
2981         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2982                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2983                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2984                         struct omap_overlay *ovl;
2985                         ovl = omap_dss_get_overlay(i);
2986
2987                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2988                                 continue;
2989
2990                         if (ovl->id == 2) {
2991                                 dispc_enable_plane(ovl->id, 0);
2992                                 dispc_go(ovl->manager->id);
2993                                 mdelay(50);
2994                                 break;
2995                         }
2996                 }
2997         }
2998
2999         if (errors & DISPC_IRQ_SYNC_LOST) {
3000                 struct omap_overlay_manager *manager = NULL;
3001                 bool enable = false;
3002
3003                 DSSERR("SYNC_LOST, disabling LCD\n");
3004
3005                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3006                         struct omap_overlay_manager *mgr;
3007                         mgr = omap_dss_get_overlay_manager(i);
3008
3009                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3010                                 manager = mgr;
3011                                 enable = mgr->device->state ==
3012                                                 OMAP_DSS_DISPLAY_ACTIVE;
3013                                 mgr->device->driver->disable(mgr->device);
3014                                 break;
3015                         }
3016                 }
3017
3018                 if (manager) {
3019                         struct omap_dss_device *dssdev = manager->device;
3020                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3021                                 struct omap_overlay *ovl;
3022                                 ovl = omap_dss_get_overlay(i);
3023
3024                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3025                                         continue;
3026
3027                                 if (ovl->id != 0 && ovl->manager == manager)
3028                                         dispc_enable_plane(ovl->id, 0);
3029                         }
3030
3031                         dispc_go(manager->id);
3032                         mdelay(50);
3033                         if (enable)
3034                                 dssdev->driver->enable(dssdev);
3035                 }
3036         }
3037
3038         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3039                 struct omap_overlay_manager *manager = NULL;
3040                 bool enable = false;
3041
3042                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3043
3044                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3045                         struct omap_overlay_manager *mgr;
3046                         mgr = omap_dss_get_overlay_manager(i);
3047
3048                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3049                                 manager = mgr;
3050                                 enable = mgr->device->state ==
3051                                                 OMAP_DSS_DISPLAY_ACTIVE;
3052                                 mgr->device->driver->disable(mgr->device);
3053                                 break;
3054                         }
3055                 }
3056
3057                 if (manager) {
3058                         struct omap_dss_device *dssdev = manager->device;
3059                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3060                                 struct omap_overlay *ovl;
3061                                 ovl = omap_dss_get_overlay(i);
3062
3063                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3064                                         continue;
3065
3066                                 if (ovl->id != 0 && ovl->manager == manager)
3067                                         dispc_enable_plane(ovl->id, 0);
3068                         }
3069
3070                         dispc_go(manager->id);
3071                         mdelay(50);
3072                         if (enable)
3073                                 dssdev->driver->enable(dssdev);
3074                 }
3075         }
3076
3077         if (errors & DISPC_IRQ_SYNC_LOST2) {
3078                 struct omap_overlay_manager *manager = NULL;
3079                 bool enable = false;
3080
3081                 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3082
3083                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3084                         struct omap_overlay_manager *mgr;
3085                         mgr = omap_dss_get_overlay_manager(i);
3086
3087                         if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3088                                 manager = mgr;
3089                                 enable = mgr->device->state ==
3090                                                 OMAP_DSS_DISPLAY_ACTIVE;
3091                                 mgr->device->driver->disable(mgr->device);
3092                                 break;
3093                         }
3094                 }
3095
3096                 if (manager) {
3097                         struct omap_dss_device *dssdev = manager->device;
3098                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3099                                 struct omap_overlay *ovl;
3100                                 ovl = omap_dss_get_overlay(i);
3101
3102                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3103                                         continue;
3104
3105                                 if (ovl->id != 0 && ovl->manager == manager)
3106                                         dispc_enable_plane(ovl->id, 0);
3107                         }
3108
3109                         dispc_go(manager->id);
3110                         mdelay(50);
3111                         if (enable)
3112                                 dssdev->driver->enable(dssdev);
3113                 }
3114         }
3115
3116         if (errors & DISPC_IRQ_OCP_ERR) {
3117                 DSSERR("OCP_ERR\n");
3118                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3119                         struct omap_overlay_manager *mgr;
3120                         mgr = omap_dss_get_overlay_manager(i);
3121
3122                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3123                                 mgr->device->driver->disable(mgr->device);
3124                 }
3125         }
3126
3127         spin_lock_irqsave(&dispc.irq_lock, flags);
3128         dispc.irq_error_mask |= errors;
3129         _omap_dispc_set_irqs();
3130         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3131 }
3132
3133 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3134 {
3135         void dispc_irq_wait_handler(void *data, u32 mask)
3136         {
3137                 complete((struct completion *)data);
3138         }
3139
3140         int r;
3141         DECLARE_COMPLETION_ONSTACK(completion);
3142
3143         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3144                         irqmask);
3145
3146         if (r)
3147                 return r;
3148
3149         timeout = wait_for_completion_timeout(&completion, timeout);
3150
3151         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3152
3153         if (timeout == 0)
3154                 return -ETIMEDOUT;
3155
3156         if (timeout == -ERESTARTSYS)
3157                 return -ERESTARTSYS;
3158
3159         return 0;
3160 }
3161
3162 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3163                 unsigned long timeout)
3164 {
3165         void dispc_irq_wait_handler(void *data, u32 mask)
3166         {
3167                 complete((struct completion *)data);
3168         }
3169
3170         int r;
3171         DECLARE_COMPLETION_ONSTACK(completion);
3172
3173         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3174                         irqmask);
3175
3176         if (r)
3177                 return r;
3178
3179         timeout = wait_for_completion_interruptible_timeout(&completion,
3180                         timeout);
3181
3182         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3183
3184         if (timeout == 0)
3185                 return -ETIMEDOUT;
3186
3187         if (timeout == -ERESTARTSYS)
3188                 return -ERESTARTSYS;
3189
3190         return 0;
3191 }
3192
3193 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3194 void dispc_fake_vsync_irq(void)
3195 {
3196         u32 irqstatus = DISPC_IRQ_VSYNC;
3197         int i;
3198
3199         WARN_ON(!in_interrupt());
3200
3201         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3202                 struct omap_dispc_isr_data *isr_data;
3203                 isr_data = &dispc.registered_isr[i];
3204
3205                 if (!isr_data->isr)
3206                         continue;
3207
3208                 if (isr_data->mask & irqstatus)
3209                         isr_data->isr(isr_data->arg, irqstatus);
3210         }
3211 }
3212 #endif
3213
3214 static void _omap_dispc_initialize_irq(void)
3215 {
3216         unsigned long flags;
3217
3218         spin_lock_irqsave(&dispc.irq_lock, flags);
3219
3220         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3221
3222         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3223         if (dss_has_feature(FEAT_MGR_LCD2))
3224                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3225
3226         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3227          * so clear it */
3228         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3229
3230         _omap_dispc_set_irqs();
3231
3232         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3233 }
3234
3235 void dispc_enable_sidle(void)
3236 {
3237         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3238 }
3239
3240 void dispc_disable_sidle(void)
3241 {
3242         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3243 }
3244
3245 static void _omap_dispc_initial_config(void)
3246 {
3247         u32 l;
3248
3249         l = dispc_read_reg(DISPC_SYSCONFIG);
3250         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3251         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3252         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3253         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3254         dispc_write_reg(DISPC_SYSCONFIG, l);
3255
3256         /* FUNCGATED */
3257         if (dss_has_feature(FEAT_FUNCGATED))
3258                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3259
3260         /* L3 firewall setting: enable access to OCM RAM */
3261         /* XXX this should be somewhere in plat-omap */
3262         if (cpu_is_omap24xx())
3263                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3264
3265         _dispc_setup_color_conv_coef();
3266
3267         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3268
3269         dispc_read_plane_fifo_sizes();
3270 }
3271
3272 int dispc_init(void)
3273 {
3274         u32 rev;
3275
3276         spin_lock_init(&dispc.irq_lock);
3277
3278 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3279         spin_lock_init(&dispc.irq_stats_lock);
3280         dispc.irq_stats.last_reset = jiffies;
3281 #endif
3282
3283         INIT_WORK(&dispc.error_work, dispc_error_worker);
3284
3285         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3286         if (!dispc.base) {
3287                 DSSERR("can't ioremap DISPC\n");
3288                 return -ENOMEM;
3289         }
3290
3291         enable_clocks(1);
3292
3293         _omap_dispc_initial_config();
3294
3295         _omap_dispc_initialize_irq();
3296
3297         dispc_save_context();
3298
3299         rev = dispc_read_reg(DISPC_REVISION);
3300         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3301                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3302
3303         enable_clocks(0);
3304
3305         return 0;
3306 }
3307
3308 void dispc_exit(void)
3309 {
3310         iounmap(dispc.base);
3311 }
3312
3313 int dispc_enable_plane(enum omap_plane plane, bool enable)
3314 {
3315         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3316
3317         enable_clocks(1);
3318         _dispc_enable_plane(plane, enable);
3319         enable_clocks(0);
3320
3321         return 0;
3322 }
3323
3324 int dispc_setup_plane(enum omap_plane plane,
3325                        u32 paddr, u16 screen_width,
3326                        u16 pos_x, u16 pos_y,
3327                        u16 width, u16 height,
3328                        u16 out_width, u16 out_height,
3329                        enum omap_color_mode color_mode,
3330                        bool ilace,
3331                        enum omap_dss_rotation_type rotation_type,
3332                        u8 rotation, bool mirror, u8 global_alpha,
3333                        u8 pre_mult_alpha, enum omap_channel channel)
3334 {
3335         int r = 0;
3336
3337         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3338                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3339                plane, paddr, screen_width, pos_x, pos_y,
3340                width, height,
3341                out_width, out_height,
3342                ilace, color_mode,
3343                rotation, mirror, channel);
3344
3345         enable_clocks(1);
3346
3347         r = _dispc_setup_plane(plane,
3348                            paddr, screen_width,
3349                            pos_x, pos_y,
3350                            width, height,
3351                            out_width, out_height,
3352                            color_mode, ilace,
3353                            rotation_type,
3354                            rotation, mirror,
3355                            global_alpha,
3356                            pre_mult_alpha, channel);
3357
3358         enable_clocks(0);
3359
3360         return r;
3361 }