drivers/video/mxsfb.c

   1 /*
   2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
   3  *
   4  * This code is based on:
   5  * Author: Vitaly Wool <vital@embeddedalley.com>
   6  *
   7  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #define DRIVER_NAME "mxsfb"
  21
  22 /**
  23  * @file
  24  * @brief LCDIF driver for i.MX23 and i.MX28
  25  *
  26  * The LCDIF support four modes of operation
  27  * - MPU interface (to drive smart displays) -> not supported yet
  28  * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
  29  * - Dotclock interface (to drive LC displays with RGB data and sync signals)
  30  * - DVI (to drive ITU-R BT656)  -> not supported yet
  31  *
  32  * This driver depends on a correct setup of the pins used for this purpose
  33  * (platform specific).
  34  *
  35  * For the developer: Don't forget to set the data bus width to the display
  36  * in the imx_fb_videomode structure. You will else end up with ugly colours.
  37  * If you fight against jitter you can vary the clock delay. This is a feature
  38  * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
  39  * the required value in the imx_fb_videomode structure.
  40  */
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/of_device.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/clk.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/io.h>
  49 #include <linux/fb.h>
  50 #include <linux/regulator/consumer.h>
  51 #include <video/of_display_timing.h>
  52 #include <video/videomode.h>
  53
  54 #define REG_SET 4
  55 #define REG_CLR 8
  56
  57 #define LCDC_CTRL                       0x00
  58 #define LCDC_CTRL1                      0x10
  59 #define LCDC_V4_CTRL2                   0x20
  60 #define LCDC_V3_TRANSFER_COUNT          0x20
  61 #define LCDC_V4_TRANSFER_COUNT          0x30
  62 #define LCDC_V4_CUR_BUF                 0x40
  63 #define LCDC_V4_NEXT_BUF                0x50
  64 #define LCDC_V3_CUR_BUF                 0x30
  65 #define LCDC_V3_NEXT_BUF                0x40
  66 #define LCDC_TIMING                     0x60
  67 #define LCDC_VDCTRL0                    0x70
  68 #define LCDC_VDCTRL1                    0x80
  69 #define LCDC_VDCTRL2                    0x90
  70 #define LCDC_VDCTRL3                    0xa0
  71 #define LCDC_VDCTRL4                    0xb0
  72 #define LCDC_DVICTRL0                   0xc0
  73 #define LCDC_DVICTRL1                   0xd0
  74 #define LCDC_DVICTRL2                   0xe0
  75 #define LCDC_DVICTRL3                   0xf0
  76 #define LCDC_DVICTRL4                   0x100
  77 #define LCDC_V4_DATA                    0x180
  78 #define LCDC_V3_DATA                    0x1b0
  79 #define LCDC_V4_DEBUG0                  0x1d0
  80 #define LCDC_V3_DEBUG0                  0x1f0
  81
  82 #define CTRL_SFTRST                     (1 << 31)
  83 #define CTRL_CLKGATE                    (1 << 30)
  84 #define CTRL_BYPASS_COUNT               (1 << 19)
  85 #define CTRL_VSYNC_MODE                 (1 << 18)
  86 #define CTRL_DOTCLK_MODE                (1 << 17)
  87 #define CTRL_DATA_SELECT                (1 << 16)
  88 #define CTRL_SET_BUS_WIDTH(x)           (((x) & 0x3) << 10)
  89 #define CTRL_GET_BUS_WIDTH(x)           (((x) >> 10) & 0x3)
  90 #define CTRL_SET_WORD_LENGTH(x)         (((x) & 0x3) << 8)
  91 #define CTRL_GET_WORD_LENGTH(x)         (((x) >> 8) & 0x3)
  92 #define CTRL_MASTER                     (1 << 5)
  93 #define CTRL_DF16                       (1 << 3)
  94 #define CTRL_DF18                       (1 << 2)
  95 #define CTRL_DF24                       (1 << 1)
  96 #define CTRL_RUN                        (1 << 0)
  97
  98 #define CTRL1_FIFO_CLEAR                (1 << 21)
  99 #define CTRL1_SET_BYTE_PACKAGING(x)     (((x) & 0xf) << 16)
 100 #define CTRL1_GET_BYTE_PACKAGING(x)     (((x) >> 16) & 0xf)
 101
 102 #define TRANSFER_COUNT_SET_VCOUNT(x)    (((x) & 0xffff) << 16)
 103 #define TRANSFER_COUNT_GET_VCOUNT(x)    (((x) >> 16) & 0xffff)
 104 #define TRANSFER_COUNT_SET_HCOUNT(x)    ((x) & 0xffff)
 105 #define TRANSFER_COUNT_GET_HCOUNT(x)    ((x) & 0xffff)
 106
 107
 108 #define VDCTRL0_ENABLE_PRESENT          (1 << 28)
 109 #define VDCTRL0_VSYNC_ACT_HIGH          (1 << 27)
 110 #define VDCTRL0_HSYNC_ACT_HIGH          (1 << 26)
 111 #define VDCTRL0_DOTCLK_ACT_FALLING      (1 << 25)
 112 #define VDCTRL0_ENABLE_ACT_HIGH         (1 << 24)
 113 #define VDCTRL0_VSYNC_PERIOD_UNIT       (1 << 21)
 114 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT  (1 << 20)
 115 #define VDCTRL0_HALF_LINE               (1 << 19)
 116 #define VDCTRL0_HALF_LINE_MODE          (1 << 18)
 117 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 118 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
 119
 120 #define VDCTRL2_SET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 121 #define VDCTRL2_GET_HSYNC_PERIOD(x)     ((x) & 0x3ffff)
 122
 123 #define VDCTRL3_MUX_SYNC_SIGNALS        (1 << 29)
 124 #define VDCTRL3_VSYNC_ONLY              (1 << 28)
 125 #define SET_HOR_WAIT_CNT(x)             (((x) & 0xfff) << 16)
 126 #define GET_HOR_WAIT_CNT(x)             (((x) >> 16) & 0xfff)
 127 #define SET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 128 #define GET_VERT_WAIT_CNT(x)            ((x) & 0xffff)
 129
 130 #define VDCTRL4_SET_DOTCLK_DLY(x)       (((x) & 0x7) << 29) /* v4 only */
 131 #define VDCTRL4_GET_DOTCLK_DLY(x)       (((x) >> 29) & 0x7) /* v4 only */
 132 #define VDCTRL4_SYNC_SIGNALS_ON         (1 << 18)
 133 #define SET_DOTCLK_H_VALID_DATA_CNT(x)  ((x) & 0x3ffff)
 134
 135 #define DEBUG0_HSYNC                    (1 < 26)
 136 #define DEBUG0_VSYNC                    (1 < 25)
 137
 138 #define MIN_XRES                        120
 139 #define MIN_YRES                        120
 140
 141 #define RED 0
 142 #define GREEN 1
 143 #define BLUE 2
 144 #define TRANSP 3
 145
 146 #define STMLCDIF_8BIT  1 /** pixel data bus to the display is of 8 bit width */
 147 #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
 148 #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
 149 #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
 150
 151 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
 152 #define MXSFB_SYNC_DOTCLK_FALLING_ACT   (1 << 7) /* negtive edge sampling */
 153
 154 enum mxsfb_devtype {
 155         MXSFB_V3,
 156         MXSFB_V4,
 157 };
 158
 159 /* CPU dependent register offsets */
 160 struct mxsfb_devdata {
 161         unsigned transfer_count;
 162         unsigned cur_buf;
 163         unsigned next_buf;
 164         unsigned debug0;
 165         unsigned hs_wdth_mask;
 166         unsigned hs_wdth_shift;
 167         unsigned ipversion;
 168 };
 169
 170 struct mxsfb_info {
 171         struct fb_info fb_info;
 172         struct platform_device *pdev;
 173         struct clk *clk;
 174         void __iomem *base;     /* registers */
 175         unsigned allocated_size;
 176         int enabled;
 177         unsigned ld_intf_width;
 178         unsigned dotclk_delay;
 179         const struct mxsfb_devdata *devdata;
 180         u32 sync;
 181         struct regulator *reg_lcd;
 182 };
 183
 184 #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
 185 #define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
 186
 187 static const struct mxsfb_devdata mxsfb_devdata[] = {
 188         [MXSFB_V3] = {
 189                 .transfer_count = LCDC_V3_TRANSFER_COUNT,
 190                 .cur_buf = LCDC_V3_CUR_BUF,
 191                 .next_buf = LCDC_V3_NEXT_BUF,
 192                 .debug0 = LCDC_V3_DEBUG0,
 193                 .hs_wdth_mask = 0xff,
 194                 .hs_wdth_shift = 24,
 195                 .ipversion = 3,
 196         },
 197         [MXSFB_V4] = {
 198                 .transfer_count = LCDC_V4_TRANSFER_COUNT,
 199                 .cur_buf = LCDC_V4_CUR_BUF,
 200                 .next_buf = LCDC_V4_NEXT_BUF,
 201                 .debug0 = LCDC_V4_DEBUG0,
 202                 .hs_wdth_mask = 0x3fff,
 203                 .hs_wdth_shift = 18,
 204                 .ipversion = 4,
 205         },
 206 };
 207
 208 #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
 209
 210 /* mask and shift depends on architecture */
 211 static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 212 {
 213         return (val & host->devdata->hs_wdth_mask) <<
 214                 host->devdata->hs_wdth_shift;
 215 }
 216
 217 static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
 218 {
 219         return (val >> host->devdata->hs_wdth_shift) &
 220                 host->devdata->hs_wdth_mask;
 221 }
 222
 223 static const struct fb_bitfield def_rgb565[] = {
 224         [RED] = {
 225                 .offset = 11,
 226                 .length = 5,
 227         },
 228         [GREEN] = {
 229                 .offset = 5,
 230                 .length = 6,
 231         },
 232         [BLUE] = {
 233                 .offset = 0,
 234                 .length = 5,
 235         },
 236         [TRANSP] = {    /* no support for transparency */
 237                 .length = 0,
 238         }
 239 };
 240
 241 static const struct fb_bitfield def_rgb888[] = {
 242         [RED] = {
 243                 .offset = 16,
 244                 .length = 8,
 245         },
 246         [GREEN] = {
 247                 .offset = 8,
 248                 .length = 8,
 249         },
 250         [BLUE] = {
 251                 .offset = 0,
 252                 .length = 8,
 253         },
 254         [TRANSP] = {    /* no support for transparency */
 255                 .length = 0,
 256         }
 257 };
 258
 259 static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
 260 {
 261         chan &= 0xffff;
 262         chan >>= 16 - bf->length;
 263         return chan << bf->offset;
 264 }
 265
 266 static int mxsfb_check_var(struct fb_var_screeninfo *var,
 267                 struct fb_info *fb_info)
 268 {
 269         struct mxsfb_info *host = to_imxfb_host(fb_info);
 270         const struct fb_bitfield *rgb = NULL;
 271
 272         if (var->xres < MIN_XRES)
 273                 var->xres = MIN_XRES;
 274         if (var->yres < MIN_YRES)
 275                 var->yres = MIN_YRES;
 276
 277         var->xres_virtual = var->xres;
 278
 279         var->yres_virtual = var->yres;
 280
 281         switch (var->bits_per_pixel) {
 282         case 16:
 283                 /* always expect RGB 565 */
 284                 rgb = def_rgb565;
 285                 break;
 286         case 32:
 287                 switch (host->ld_intf_width) {
 288                 case STMLCDIF_8BIT:
 289                         pr_debug("Unsupported LCD bus width mapping\n");
 290                         break;
 291                 case STMLCDIF_16BIT:
 292                 case STMLCDIF_18BIT:
 293                 case STMLCDIF_24BIT:
 294                         /* real 24 bit */
 295                         rgb = def_rgb888;
 296                         break;
 297                 }
 298                 break;
 299         default:
 300                 pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
 301                 return -EINVAL;
 302         }
 303
 304         /*
 305          * Copy the RGB parameters for this display
 306          * from the machine specific parameters.
 307          */
 308         var->red    = rgb[RED];
 309         var->green  = rgb[GREEN];
 310         var->blue   = rgb[BLUE];
 311         var->transp = rgb[TRANSP];
 312
 313         return 0;
 314 }
 315
 316 static void mxsfb_enable_controller(struct fb_info *fb_info)
 317 {
 318         struct mxsfb_info *host = to_imxfb_host(fb_info);
 319         u32 reg;
 320         int ret;
 321
 322         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 323
 324         if (host->reg_lcd) {
 325                 ret = regulator_enable(host->reg_lcd);
 326                 if (ret) {
 327                         dev_err(&host->pdev->dev,
 328                                 "lcd regulator enable failed:   %d\n", ret);
 329                         return;
 330                 }
 331         }
 332
 333         clk_prepare_enable(host->clk);
 334         clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
 335
 336         /* if it was disabled, re-enable the mode again */
 337         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
 338
 339         /* enable the SYNC signals first, then the DMA engine */
 340         reg = readl(host->base + LCDC_VDCTRL4);
 341         reg |= VDCTRL4_SYNC_SIGNALS_ON;
 342         writel(reg, host->base + LCDC_VDCTRL4);
 343
 344         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
 345
 346         host->enabled = 1;
 347 }
 348
 349 static void mxsfb_disable_controller(struct fb_info *fb_info)
 350 {
 351         struct mxsfb_info *host = to_imxfb_host(fb_info);
 352         unsigned loop;
 353         u32 reg;
 354         int ret;
 355
 356         dev_dbg(&host->pdev->dev, "%s\n", __func__);
 357
 358         /*
 359          * Even if we disable the controller here, it will still continue
 360          * until its FIFOs are running out of data
 361          */
 362         writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
 363
 364         loop = 1000;
 365         while (loop) {
 366                 reg = readl(host->base + LCDC_CTRL);
 367                 if (!(reg & CTRL_RUN))
 368                         break;
 369                 loop--;
 370         }
 371
 372         reg = readl(host->base + LCDC_VDCTRL4);
 373         writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
 374
 375         clk_disable_unprepare(host->clk);
 376
 377         host->enabled = 0;
 378
 379         if (host->reg_lcd) {
 380                 ret = regulator_disable(host->reg_lcd);
 381                 if (ret)
 382                         dev_err(&host->pdev->dev,
 383                                 "lcd regulator disable failed: %d\n", ret);
 384         }
 385 }
 386
 387 static int mxsfb_set_par(struct fb_info *fb_info)
 388 {
 389         struct mxsfb_info *host = to_imxfb_host(fb_info);
 390         u32 ctrl, vdctrl0, vdctrl4;
 391         int line_size, fb_size;
 392         int reenable = 0;
 393
 394         line_size =  fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
 395         fb_size = fb_info->var.yres_virtual * line_size;
 396
 397         if (fb_size > fb_info->fix.smem_len)
 398                 return -ENOMEM;
 399
 400         fb_info->fix.line_length = line_size;
 401
 402         /*
 403          * It seems, you can't re-program the controller if it is still running.
 404          * This may lead into shifted pictures (FIFO issue?).
 405          * So, first stop the controller and drain its FIFOs
 406          */
 407         if (host->enabled) {
 408                 reenable = 1;
 409                 mxsfb_disable_controller(fb_info);
 410         }
 411
 412         /* clear the FIFOs */
 413         writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
 414
 415         ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
 416                 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
 417
 418         switch (fb_info->var.bits_per_pixel) {
 419         case 16:
 420                 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
 421                 ctrl |= CTRL_SET_WORD_LENGTH(0);
 422                 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
 423                 break;
 424         case 32:
 425                 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
 426                 ctrl |= CTRL_SET_WORD_LENGTH(3);
 427                 switch (host->ld_intf_width) {
 428                 case STMLCDIF_8BIT:
 429                         dev_dbg(&host->pdev->dev,
 430                                         "Unsupported LCD bus width mapping\n");
 431                         return -EINVAL;
 432                 case STMLCDIF_16BIT:
 433                 case STMLCDIF_18BIT:
 434                 case STMLCDIF_24BIT:
 435                         /* real 24 bit */
 436                         break;
 437                 }
 438                 /* do not use packed pixels = one pixel per word instead */
 439                 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
 440                 break;
 441         default:
 442                 dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
 443                                 fb_info->var.bits_per_pixel);
 444                 return -EINVAL;
 445         }
 446
 447         writel(ctrl, host->base + LCDC_CTRL);
 448
 449         writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
 450                         TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
 451                         host->base + host->devdata->transfer_count);
 452
 453         vdctrl0 = VDCTRL0_ENABLE_PRESENT |      /* always in DOTCLOCK mode */
 454                 VDCTRL0_VSYNC_PERIOD_UNIT |
 455                 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 456                 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
 457         if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 458                 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 459         if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 460                 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
 461         if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
 462                 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
 463         if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
 464                 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
 465
 466         writel(vdctrl0, host->base + LCDC_VDCTRL0);
 467
 468         /* frame length in lines */
 469         writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
 470                 fb_info->var.lower_margin + fb_info->var.yres,
 471                 host->base + LCDC_VDCTRL1);
 472
 473         /* line length in units of clocks or pixels */
 474         writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
 475                 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
 476                 fb_info->var.hsync_len + fb_info->var.right_margin +
 477                 fb_info->var.xres),
 478                 host->base + LCDC_VDCTRL2);
 479
 480         writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
 481                 fb_info->var.hsync_len) |
 482                 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
 483                         fb_info->var.vsync_len),
 484                 host->base + LCDC_VDCTRL3);
 485
 486         vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
 487         if (mxsfb_is_v4(host))
 488                 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
 489         writel(vdctrl4, host->base + LCDC_VDCTRL4);
 490
 491         writel(fb_info->fix.smem_start +
 492                         fb_info->fix.line_length * fb_info->var.yoffset,
 493                         host->base + host->devdata->next_buf);
 494
 495         if (reenable)
 496                 mxsfb_enable_controller(fb_info);
 497
 498         return 0;
 499 }
 500
 501 static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 502                 u_int transp, struct fb_info *fb_info)
 503 {
 504         unsigned int val;
 505         int ret = -EINVAL;
 506
 507         /*
 508          * If greyscale is true, then we convert the RGB value
 509          * to greyscale no matter what visual we are using.
 510          */
 511         if (fb_info->var.grayscale)
 512                 red = green = blue = (19595 * red + 38470 * green +
 513                                         7471 * blue) >> 16;
 514
 515         switch (fb_info->fix.visual) {
 516         case FB_VISUAL_TRUECOLOR:
 517                 /*
 518                  * 12 or 16-bit True Colour.  We encode the RGB value
 519                  * according to the RGB bitfield information.
 520                  */
 521                 if (regno < 16) {
 522                         u32 *pal = fb_info->pseudo_palette;
 523
 524                         val  = chan_to_field(red, &fb_info->var.red);
 525                         val |= chan_to_field(green, &fb_info->var.green);
 526                         val |= chan_to_field(blue, &fb_info->var.blue);
 527
 528                         pal[regno] = val;
 529                         ret = 0;
 530                 }
 531                 break;
 532
 533         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 534         case FB_VISUAL_PSEUDOCOLOR:
 535                 break;
 536         }
 537
 538         return ret;
 539 }
 540
 541 static int mxsfb_blank(int blank, struct fb_info *fb_info)
 542 {
 543         struct mxsfb_info *host = to_imxfb_host(fb_info);
 544
 545         switch (blank) {
 546         case FB_BLANK_POWERDOWN:
 547         case FB_BLANK_VSYNC_SUSPEND:
 548         case FB_BLANK_HSYNC_SUSPEND:
 549         case FB_BLANK_NORMAL:
 550                 if (host->enabled)
 551                         mxsfb_disable_controller(fb_info);
 552                 break;
 553
 554         case FB_BLANK_UNBLANK:
 555                 if (!host->enabled)
 556                         mxsfb_enable_controller(fb_info);
 557                 break;
 558         }
 559         return 0;
 560 }
 561
 562 static int mxsfb_pan_display(struct fb_var_screeninfo *var,
 563                 struct fb_info *fb_info)
 564 {
 565         struct mxsfb_info *host = to_imxfb_host(fb_info);
 566         unsigned offset;
 567
 568         if (var->xoffset != 0)
 569                 return -EINVAL;
 570
 571         offset = fb_info->fix.line_length * var->yoffset;
 572
 573         /* update on next VSYNC */
 574         writel(fb_info->fix.smem_start + offset,
 575                         host->base + host->devdata->next_buf);
 576
 577         return 0;
 578 }
 579
 580 static struct fb_ops mxsfb_ops = {
 581         .owner = THIS_MODULE,
 582         .fb_check_var = mxsfb_check_var,
 583         .fb_set_par = mxsfb_set_par,
 584         .fb_setcolreg = mxsfb_setcolreg,
 585         .fb_blank = mxsfb_blank,
 586         .fb_pan_display = mxsfb_pan_display,
 587         .fb_fillrect = cfb_fillrect,
 588         .fb_copyarea = cfb_copyarea,
 589         .fb_imageblit = cfb_imageblit,
 590 };
 591
 592 static int mxsfb_restore_mode(struct mxsfb_info *host)
 593 {
 594         struct fb_info *fb_info = &host->fb_info;
 595         unsigned line_count;
 596         unsigned period;
 597         unsigned long pa, fbsize;
 598         int bits_per_pixel, ofs;
 599         u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
 600         struct fb_videomode vmode;
 601
 602         /* Only restore the mode when the controller is running */
 603         ctrl = readl(host->base + LCDC_CTRL);
 604         if (!(ctrl & CTRL_RUN))
 605                 return -EINVAL;
 606
 607         vdctrl0 = readl(host->base + LCDC_VDCTRL0);
 608         vdctrl2 = readl(host->base + LCDC_VDCTRL2);
 609         vdctrl3 = readl(host->base + LCDC_VDCTRL3);
 610         vdctrl4 = readl(host->base + LCDC_VDCTRL4);
 611
 612         transfer_count = readl(host->base + host->devdata->transfer_count);
 613
 614         vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
 615         vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
 616
 617         switch (CTRL_GET_WORD_LENGTH(ctrl)) {
 618         case 0:
 619                 bits_per_pixel = 16;
 620                 break;
 621         case 3:
 622                 bits_per_pixel = 32;
 623                 break;
 624         case 1:
 625         default:
 626                 return -EINVAL;
 627         }
 628
 629         fb_info->var.bits_per_pixel = bits_per_pixel;
 630
 631         vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
 632         vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
 633         vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
 634         vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
 635                 vmode.left_margin - vmode.xres;
 636         vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
 637         period = readl(host->base + LCDC_VDCTRL1);
 638         vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
 639         vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
 640
 641         vmode.vmode = FB_VMODE_NONINTERLACED;
 642
 643         vmode.sync = 0;
 644         if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
 645                 vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
 646         if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
 647                 vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
 648
 649         pr_debug("Reconstructed video mode:\n");
 650         pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
 651                         vmode.xres, vmode.yres,
 652                         vmode.hsync_len, vmode.left_margin, vmode.right_margin,
 653                         vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
 654         pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
 655
 656         fb_add_videomode(&vmode, &fb_info->modelist);
 657
 658         host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
 659         host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
 660
 661         fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
 662
 663         pa = readl(host->base + host->devdata->cur_buf);
 664         fbsize = fb_info->fix.line_length * vmode.yres;
 665         if (pa < fb_info->fix.smem_start)
 666                 return -EINVAL;
 667         if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
 668                 return -EINVAL;
 669         ofs = pa - fb_info->fix.smem_start;
 670         if (ofs) {
 671                 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
 672                 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
 673         }
 674
 675         line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
 676         fb_info->fix.ypanstep = 1;
 677
 678         clk_prepare_enable(host->clk);
 679         host->enabled = 1;
 680
 681         return 0;
 682 }
 683
 684 static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
 685 {
 686         struct fb_info *fb_info = &host->fb_info;
 687         struct fb_var_screeninfo *var = &fb_info->var;
 688         struct device *dev = &host->pdev->dev;
 689         struct device_node *np = host->pdev->dev.of_node;
 690         struct device_node *display_np;
 691         struct device_node *timings_np;
 692         struct display_timings *timings;
 693         u32 width;
 694         int i;
 695         int ret = 0;
 696
 697         display_np = of_parse_phandle(np, "display", 0);
 698         if (!display_np) {
 699                 dev_err(dev, "failed to find display phandle\n");
 700                 return -ENOENT;
 701         }
 702
 703         ret = of_property_read_u32(display_np, "bus-width", &width);
 704         if (ret < 0) {
 705                 dev_err(dev, "failed to get property bus-width\n");
 706                 goto put_display_node;
 707         }
 708
 709         switch (width) {
 710         case 8:
 711                 host->ld_intf_width = STMLCDIF_8BIT;
 712                 break;
 713         case 16:
 714                 host->ld_intf_width = STMLCDIF_16BIT;
 715                 break;
 716         case 18:
 717                 host->ld_intf_width = STMLCDIF_18BIT;
 718                 break;
 719         case 24:
 720                 host->ld_intf_width = STMLCDIF_24BIT;
 721                 break;
 722         default:
 723                 dev_err(dev, "invalid bus-width value\n");
 724                 ret = -EINVAL;
 725                 goto put_display_node;
 726         }
 727
 728         ret = of_property_read_u32(display_np, "bits-per-pixel",
 729                                    &var->bits_per_pixel);
 730         if (ret < 0) {
 731                 dev_err(dev, "failed to get property bits-per-pixel\n");
 732                 goto put_display_node;
 733         }
 734
 735         timings = of_get_display_timings(display_np);
 736         if (!timings) {
 737                 dev_err(dev, "failed to get display timings\n");
 738                 ret = -ENOENT;
 739                 goto put_display_node;
 740         }
 741
 742         timings_np = of_find_node_by_name(display_np,
 743                                           "display-timings");
 744         if (!timings_np) {
 745                 dev_err(dev, "failed to find display-timings node\n");
 746                 ret = -ENOENT;
 747                 goto put_display_node;
 748         }
 749
 750         for (i = 0; i < of_get_child_count(timings_np); i++) {
 751                 struct videomode vm;
 752                 struct fb_videomode fb_vm;
 753
 754                 ret = videomode_from_timings(timings, &vm, i);
 755                 if (ret < 0)
 756                         goto put_timings_node;
 757                 ret = fb_videomode_from_videomode(&vm, &fb_vm);
 758                 if (ret < 0)
 759                         goto put_timings_node;
 760
 761                 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 762                         host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
 763                 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 764                         host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
 765                 fb_add_videomode(&fb_vm, &fb_info->modelist);
 766         }
 767
 768 put_timings_node:
 769         of_node_put(timings_np);
 770 put_display_node:
 771         of_node_put(display_np);
 772         return ret;
 773 }
 774
 775 static int mxsfb_init_fbinfo(struct mxsfb_info *host)
 776 {
 777         struct fb_info *fb_info = &host->fb_info;
 778         struct fb_var_screeninfo *var = &fb_info->var;
 779         dma_addr_t fb_phys;
 780         void *fb_virt;
 781         unsigned fb_size;
 782         int ret;
 783
 784         fb_info->fbops = &mxsfb_ops;
 785         fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
 786         strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
 787         fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
 788         fb_info->fix.ypanstep = 1;
 789         fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
 790         fb_info->fix.accel = FB_ACCEL_NONE;
 791
 792         ret = mxsfb_init_fbinfo_dt(host);
 793         if (ret)
 794                 return ret;
 795
 796         var->nonstd = 0;
 797         var->activate = FB_ACTIVATE_NOW;
 798         var->accel_flags = 0;
 799         var->vmode = FB_VMODE_NONINTERLACED;
 800
 801         /* Memory allocation for framebuffer */
 802         fb_size = SZ_2M;
 803         fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
 804         if (!fb_virt)
 805                 return -ENOMEM;
 806
 807         fb_phys = virt_to_phys(fb_virt);
 808
 809         fb_info->fix.smem_start = fb_phys;
 810         fb_info->screen_base = fb_virt;
 811         fb_info->screen_size = fb_info->fix.smem_len = fb_size;
 812
 813         if (mxsfb_restore_mode(host))
 814                 memset(fb_virt, 0, fb_size);
 815
 816         return 0;
 817 }
 818
 819 static void mxsfb_free_videomem(struct mxsfb_info *host)
 820 {
 821         struct fb_info *fb_info = &host->fb_info;
 822
 823         free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
 824 }
 825
 826 static struct platform_device_id mxsfb_devtype[] = {
 827         {
 828                 .name = "imx23-fb",
 829                 .driver_data = MXSFB_V3,
 830         }, {
 831                 .name = "imx28-fb",
 832                 .driver_data = MXSFB_V4,
 833         }, {
 834                 /* sentinel */
 835         }
 836 };
 837 MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
 838
 839 static const struct of_device_id mxsfb_dt_ids[] = {
 840         { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
 841         { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
 842         { /* sentinel */ }
 843 };
 844 MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
 845
 846 static int mxsfb_probe(struct platform_device *pdev)
 847 {
 848         const struct of_device_id *of_id =
 849                         of_match_device(mxsfb_dt_ids, &pdev->dev);
 850         struct resource *res;
 851         struct mxsfb_info *host;
 852         struct fb_info *fb_info;
 853         struct fb_modelist *modelist;
 854         int ret;
 855
 856         if (of_id)
 857                 pdev->id_entry = of_id->data;
 858
 859         fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
 860         if (!fb_info) {
 861                 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
 862                 return -ENOMEM;
 863         }
 864
 865         host = to_imxfb_host(fb_info);
 866
 867         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 868         host->base = devm_ioremap_resource(&pdev->dev, res);
 869         if (IS_ERR(host->base)) {
 870                 ret = PTR_ERR(host->base);
 871                 goto fb_release;
 872         }
 873
 874         host->pdev = pdev;
 875         platform_set_drvdata(pdev, host);
 876
 877         host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 878
 879         host->clk = devm_clk_get(&host->pdev->dev, NULL);
 880         if (IS_ERR(host->clk)) {
 881                 ret = PTR_ERR(host->clk);
 882                 goto fb_release;
 883         }
 884
 885         host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
 886         if (IS_ERR(host->reg_lcd))
 887                 host->reg_lcd = NULL;
 888
 889         fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
 890                                                GFP_KERNEL);
 891         if (!fb_info->pseudo_palette) {
 892                 ret = -ENOMEM;
 893                 goto fb_release;
 894         }
 895
 896         INIT_LIST_HEAD(&fb_info->modelist);
 897
 898         ret = mxsfb_init_fbinfo(host);
 899         if (ret != 0)
 900                 goto fb_release;
 901
 902         modelist = list_first_entry(&fb_info->modelist,
 903                         struct fb_modelist, list);
 904         fb_videomode_to_var(&fb_info->var, &modelist->mode);
 905
 906         /* init the color fields */
 907         mxsfb_check_var(&fb_info->var, fb_info);
 908
 909         platform_set_drvdata(pdev, fb_info);
 910
 911         ret = register_framebuffer(fb_info);
 912         if (ret != 0) {
 913                 dev_err(&pdev->dev,"Failed to register framebuffer\n");
 914                 goto fb_destroy;
 915         }
 916
 917         if (!host->enabled) {
 918                 writel(0, host->base + LCDC_CTRL);
 919                 mxsfb_set_par(fb_info);
 920                 mxsfb_enable_controller(fb_info);
 921         }
 922
 923         dev_info(&pdev->dev, "initialized\n");
 924
 925         return 0;
 926
 927 fb_destroy:
 928         if (host->enabled)
 929                 clk_disable_unprepare(host->clk);
 930         fb_destroy_modelist(&fb_info->modelist);
 931 fb_release:
 932         framebuffer_release(fb_info);
 933
 934         return ret;
 935 }
 936
 937 static int mxsfb_remove(struct platform_device *pdev)
 938 {
 939         struct fb_info *fb_info = platform_get_drvdata(pdev);
 940         struct mxsfb_info *host = to_imxfb_host(fb_info);
 941
 942         if (host->enabled)
 943                 mxsfb_disable_controller(fb_info);
 944
 945         unregister_framebuffer(fb_info);
 946         mxsfb_free_videomem(host);
 947
 948         framebuffer_release(fb_info);
 949
 950         return 0;
 951 }
 952
 953 static void mxsfb_shutdown(struct platform_device *pdev)
 954 {
 955         struct fb_info *fb_info = platform_get_drvdata(pdev);
 956         struct mxsfb_info *host = to_imxfb_host(fb_info);
 957
 958         /*
 959          * Force stop the LCD controller as keeping it running during reboot
 960          * might interfere with the BootROM's boot mode pads sampling.
 961          */
 962         writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
 963 }
 964
 965 static struct platform_driver mxsfb_driver = {
 966         .probe = mxsfb_probe,
 967         .remove = mxsfb_remove,
 968         .shutdown = mxsfb_shutdown,
 969         .id_table = mxsfb_devtype,
 970         .driver = {
 971                    .name = DRIVER_NAME,
 972                    .of_match_table = mxsfb_dt_ids,
 973         },
 974 };
 975
 976 module_platform_driver(mxsfb_driver);
 977
 978 MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
 979 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 980 MODULE_LICENSE("GPL");