drivers/video/meson/meson_venc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic Meson Video Processing Unit driver
   4  *
   5  * Copyright (c) 2018 BayLibre, SAS.
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <edid.h>
  12 #include <fdtdec.h>
  13 #include <log.h>
  14 #include <asm/io.h>
  15 #include "meson_vpu.h"
  16
  17 enum {
  18         MESON_VENC_MODE_NONE = 0,
  19         MESON_VENC_MODE_CVBS_PAL,
  20         MESON_VENC_MODE_CVBS_NTSC,
  21         MESON_VENC_MODE_HDMI,
  22 };
  23
  24 enum meson_venc_source {
  25         MESON_VENC_SOURCE_NONE = 0,
  26         MESON_VENC_SOURCE_ENCI = 1,
  27         MESON_VENC_SOURCE_ENCP = 2,
  28 };
  29
  30 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
  31 #define HHI_VDAC_CNTL0_G12A     0x2EC /* 0xbb offset in data sheet */
  32 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
  33 #define HHI_VDAC_CNTL1_G12A     0x2F0 /* 0xbc offset in data sheet */
  34
  35 struct meson_cvbs_enci_mode {
  36         unsigned int mode_tag;
  37         unsigned int hso_begin; /* HSO begin position */
  38         unsigned int hso_end; /* HSO end position */
  39         unsigned int vso_even; /* VSO even line */
  40         unsigned int vso_odd; /* VSO odd line */
  41         unsigned int macv_max_amp; /* Macrovision max amplitude */
  42         unsigned int video_prog_mode;
  43         unsigned int video_mode;
  44         unsigned int sch_adjust;
  45         unsigned int yc_delay;
  46         unsigned int pixel_start;
  47         unsigned int pixel_end;
  48         unsigned int top_field_line_start;
  49         unsigned int top_field_line_end;
  50         unsigned int bottom_field_line_start;
  51         unsigned int bottom_field_line_end;
  52         unsigned int video_saturation;
  53         unsigned int video_contrast;
  54         unsigned int video_brightness;
  55         unsigned int video_hue;
  56         unsigned int analog_sync_adj;
  57 };
  58
  59 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
  60         .mode_tag = MESON_VENC_MODE_CVBS_PAL,
  61         .hso_begin = 3,
  62         .hso_end = 129,
  63         .vso_even = 3,
  64         .vso_odd = 260,
  65         .macv_max_amp = 7,
  66         .video_prog_mode = 0xff,
  67         .video_mode = 0x13,
  68         .sch_adjust = 0x28,
  69         .yc_delay = 0x343,
  70         .pixel_start = 251,
  71         .pixel_end = 1691,
  72         .top_field_line_start = 22,
  73         .top_field_line_end = 310,
  74         .bottom_field_line_start = 23,
  75         .bottom_field_line_end = 311,
  76         .video_saturation = 9,
  77         .video_contrast = 0,
  78         .video_brightness = 0,
  79         .video_hue = 0,
  80         .analog_sync_adj = 0x8080,
  81 };
  82
  83 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
  84         .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
  85         .hso_begin = 5,
  86         .hso_end = 129,
  87         .vso_even = 3,
  88         .vso_odd = 260,
  89         .macv_max_amp = 0xb,
  90         .video_prog_mode = 0xf0,
  91         .video_mode = 0x8,
  92         .sch_adjust = 0x20,
  93         .yc_delay = 0x333,
  94         .pixel_start = 227,
  95         .pixel_end = 1667,
  96         .top_field_line_start = 18,
  97         .top_field_line_end = 258,
  98         .bottom_field_line_start = 19,
  99         .bottom_field_line_end = 259,
 100         .video_saturation = 18,
 101         .video_contrast = 3,
 102         .video_brightness = 0,
 103         .video_hue = 0,
 104         .analog_sync_adj = 0x9c00,
 105 };
 106
 107 union meson_hdmi_venc_mode {
 108         struct {
 109                 unsigned int mode_tag;
 110                 unsigned int hso_begin;
 111                 unsigned int hso_end;
 112                 unsigned int vso_even;
 113                 unsigned int vso_odd;
 114                 unsigned int macv_max_amp;
 115                 unsigned int video_prog_mode;
 116                 unsigned int video_mode;
 117                 unsigned int sch_adjust;
 118                 unsigned int yc_delay;
 119                 unsigned int pixel_start;
 120                 unsigned int pixel_end;
 121                 unsigned int top_field_line_start;
 122                 unsigned int top_field_line_end;
 123                 unsigned int bottom_field_line_start;
 124                 unsigned int bottom_field_line_end;
 125         } enci;
 126         struct {
 127                 unsigned int dvi_settings;
 128                 unsigned int video_mode;
 129                 unsigned int video_mode_adv;
 130                 unsigned int video_prog_mode;
 131                 bool video_prog_mode_present;
 132                 unsigned int video_sync_mode;
 133                 bool video_sync_mode_present;
 134                 unsigned int video_yc_dly;
 135                 bool video_yc_dly_present;
 136                 unsigned int video_rgb_ctrl;
 137                 bool video_rgb_ctrl_present;
 138                 unsigned int video_filt_ctrl;
 139                 bool video_filt_ctrl_present;
 140                 unsigned int video_ofld_voav_ofst;
 141                 bool video_ofld_voav_ofst_present;
 142                 unsigned int yfp1_htime;
 143                 unsigned int yfp2_htime;
 144                 unsigned int max_pxcnt;
 145                 unsigned int hspuls_begin;
 146                 unsigned int hspuls_end;
 147                 unsigned int hspuls_switch;
 148                 unsigned int vspuls_begin;
 149                 unsigned int vspuls_end;
 150                 unsigned int vspuls_bline;
 151                 unsigned int vspuls_eline;
 152                 unsigned int eqpuls_begin;
 153                 bool eqpuls_begin_present;
 154                 unsigned int eqpuls_end;
 155                 bool eqpuls_end_present;
 156                 unsigned int eqpuls_bline;
 157                 bool eqpuls_bline_present;
 158                 unsigned int eqpuls_eline;
 159                 bool eqpuls_eline_present;
 160                 unsigned int havon_begin;
 161                 unsigned int havon_end;
 162                 unsigned int vavon_bline;
 163                 unsigned int vavon_eline;
 164                 unsigned int hso_begin;
 165                 unsigned int hso_end;
 166                 unsigned int vso_begin;
 167                 unsigned int vso_end;
 168                 unsigned int vso_bline;
 169                 unsigned int vso_eline;
 170                 bool vso_eline_present;
 171                 unsigned int sy_val;
 172                 bool sy_val_present;
 173                 unsigned int sy2_val;
 174                 bool sy2_val_present;
 175                 unsigned int max_lncnt;
 176         } encp;
 177 };
 178
 179 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
 180         .enci = {
 181                 .hso_begin = 5,
 182                 .hso_end = 129,
 183                 .vso_even = 3,
 184                 .vso_odd = 260,
 185                 .macv_max_amp = 0xb,
 186                 .video_prog_mode = 0xf0,
 187                 .video_mode = 0x8,
 188                 .sch_adjust = 0x20,
 189                 .yc_delay = 0,
 190                 .pixel_start = 227,
 191                 .pixel_end = 1667,
 192                 .top_field_line_start = 18,
 193                 .top_field_line_end = 258,
 194                 .bottom_field_line_start = 19,
 195                 .bottom_field_line_end = 259,
 196         },
 197 };
 198
 199 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
 200         .enci = {
 201                 .hso_begin = 3,
 202                 .hso_end = 129,
 203                 .vso_even = 3,
 204                 .vso_odd = 260,
 205                 .macv_max_amp = 0x7,
 206                 .video_prog_mode = 0xff,
 207                 .video_mode = 0x13,
 208                 .sch_adjust = 0x28,
 209                 .yc_delay = 0x333,
 210                 .pixel_start = 251,
 211                 .pixel_end = 1691,
 212                 .top_field_line_start = 22,
 213                 .top_field_line_end = 310,
 214                 .bottom_field_line_start = 23,
 215                 .bottom_field_line_end = 311,
 216         },
 217 };
 218
 219 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
 220         .encp = {
 221                 .dvi_settings = 0x21,
 222                 .video_mode = 0x4000,
 223                 .video_mode_adv = 0x9,
 224                 .video_prog_mode = 0,
 225                 .video_prog_mode_present = true,
 226                 .video_sync_mode = 7,
 227                 .video_sync_mode_present = true,
 228                 /* video_yc_dly */
 229                 /* video_rgb_ctrl */
 230                 .video_filt_ctrl = 0x2052,
 231                 .video_filt_ctrl_present = true,
 232                 /* video_ofld_voav_ofst */
 233                 .yfp1_htime = 244,
 234                 .yfp2_htime = 1630,
 235                 .max_pxcnt = 1715,
 236                 .hspuls_begin = 0x22,
 237                 .hspuls_end = 0xa0,
 238                 .hspuls_switch = 88,
 239                 .vspuls_begin = 0,
 240                 .vspuls_end = 1589,
 241                 .vspuls_bline = 0,
 242                 .vspuls_eline = 5,
 243                 .havon_begin = 249,
 244                 .havon_end = 1689,
 245                 .vavon_bline = 42,
 246                 .vavon_eline = 521,
 247                 /* eqpuls_begin */
 248                 /* eqpuls_end */
 249                 /* eqpuls_bline */
 250                 /* eqpuls_eline */
 251                 .hso_begin = 3,
 252                 .hso_end = 5,
 253                 .vso_begin = 3,
 254                 .vso_end = 5,
 255                 .vso_bline = 0,
 256                 /* vso_eline */
 257                 .sy_val = 8,
 258                 .sy_val_present = true,
 259                 .sy2_val = 0x1d8,
 260                 .sy2_val_present = true,
 261                 .max_lncnt = 524,
 262         },
 263 };
 264
 265 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
 266         .encp = {
 267                 .dvi_settings = 0x21,
 268                 .video_mode = 0x4000,
 269                 .video_mode_adv = 0x9,
 270                 .video_prog_mode = 0,
 271                 .video_prog_mode_present = true,
 272                 .video_sync_mode = 7,
 273                 .video_sync_mode_present = true,
 274                 /* video_yc_dly */
 275                 /* video_rgb_ctrl */
 276                 .video_filt_ctrl = 0x52,
 277                 .video_filt_ctrl_present = true,
 278                 /* video_ofld_voav_ofst */
 279                 .yfp1_htime = 235,
 280                 .yfp2_htime = 1674,
 281                 .max_pxcnt = 1727,
 282                 .hspuls_begin = 0,
 283                 .hspuls_end = 0x80,
 284                 .hspuls_switch = 88,
 285                 .vspuls_begin = 0,
 286                 .vspuls_end = 1599,
 287                 .vspuls_bline = 0,
 288                 .vspuls_eline = 4,
 289                 .havon_begin = 235,
 290                 .havon_end = 1674,
 291                 .vavon_bline = 44,
 292                 .vavon_eline = 619,
 293                 /* eqpuls_begin */
 294                 /* eqpuls_end */
 295                 /* eqpuls_bline */
 296                 /* eqpuls_eline */
 297                 .hso_begin = 0x80,
 298                 .hso_end = 0,
 299                 .vso_begin = 0,
 300                 .vso_end = 5,
 301                 .vso_bline = 0,
 302                 /* vso_eline */
 303                 .sy_val = 8,
 304                 .sy_val_present = true,
 305                 .sy2_val = 0x1d8,
 306                 .sy2_val_present = true,
 307                 .max_lncnt = 624,
 308         },
 309 };
 310
 311 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
 312         .encp = {
 313                 .dvi_settings = 0x2029,
 314                 .video_mode = 0x4040,
 315                 .video_mode_adv = 0x19,
 316                 /* video_prog_mode */
 317                 /* video_sync_mode */
 318                 /* video_yc_dly */
 319                 /* video_rgb_ctrl */
 320                 /* video_filt_ctrl */
 321                 /* video_ofld_voav_ofst */
 322                 .yfp1_htime = 648,
 323                 .yfp2_htime = 3207,
 324                 .max_pxcnt = 3299,
 325                 .hspuls_begin = 80,
 326                 .hspuls_end = 240,
 327                 .hspuls_switch = 80,
 328                 .vspuls_begin = 688,
 329                 .vspuls_end = 3248,
 330                 .vspuls_bline = 4,
 331                 .vspuls_eline = 8,
 332                 .havon_begin = 648,
 333                 .havon_end = 3207,
 334                 .vavon_bline = 29,
 335                 .vavon_eline = 748,
 336                 /* eqpuls_begin */
 337                 /* eqpuls_end */
 338                 /* eqpuls_bline */
 339                 /* eqpuls_eline */
 340                 .hso_begin = 256,
 341                 .hso_end = 168,
 342                 .vso_begin = 168,
 343                 .vso_end = 256,
 344                 .vso_bline = 0,
 345                 .vso_eline = 5,
 346                 .vso_eline_present = true,
 347                 /* sy_val */
 348                 /* sy2_val */
 349                 .max_lncnt = 749,
 350         },
 351 };
 352
 353 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
 354         .encp = {
 355                 .dvi_settings = 0x202d,
 356                 .video_mode = 0x4040,
 357                 .video_mode_adv = 0x19,
 358                 .video_prog_mode = 0x100,
 359                 .video_prog_mode_present = true,
 360                 .video_sync_mode = 0x407,
 361                 .video_sync_mode_present = true,
 362                 .video_yc_dly = 0,
 363                 .video_yc_dly_present = true,
 364                 /* video_rgb_ctrl */
 365                 /* video_filt_ctrl */
 366                 /* video_ofld_voav_ofst */
 367                 .yfp1_htime = 648,
 368                 .yfp2_htime = 3207,
 369                 .max_pxcnt = 3959,
 370                 .hspuls_begin = 80,
 371                 .hspuls_end = 240,
 372                 .hspuls_switch = 80,
 373                 .vspuls_begin = 688,
 374                 .vspuls_end = 3248,
 375                 .vspuls_bline = 4,
 376                 .vspuls_eline = 8,
 377                 .havon_begin = 648,
 378                 .havon_end = 3207,
 379                 .vavon_bline = 29,
 380                 .vavon_eline = 748,
 381                 /* eqpuls_begin */
 382                 /* eqpuls_end */
 383                 /* eqpuls_bline */
 384                 /* eqpuls_eline */
 385                 .hso_begin = 128,
 386                 .hso_end = 208,
 387                 .vso_begin = 128,
 388                 .vso_end = 128,
 389                 .vso_bline = 0,
 390                 .vso_eline = 5,
 391                 .vso_eline_present = true,
 392                 /* sy_val */
 393                 /* sy2_val */
 394                 .max_lncnt = 749,
 395         },
 396 };
 397
 398 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
 399         .encp = {
 400                 .dvi_settings = 0x2029,
 401                 .video_mode = 0x5ffc,
 402                 .video_mode_adv = 0x19,
 403                 .video_prog_mode = 0x100,
 404                 .video_prog_mode_present = true,
 405                 .video_sync_mode = 0x207,
 406                 .video_sync_mode_present = true,
 407                 /* video_yc_dly */
 408                 /* video_rgb_ctrl */
 409                 /* video_filt_ctrl */
 410                 .video_ofld_voav_ofst = 0x11,
 411                 .video_ofld_voav_ofst_present = true,
 412                 .yfp1_htime = 516,
 413                 .yfp2_htime = 4355,
 414                 .max_pxcnt = 4399,
 415                 .hspuls_begin = 88,
 416                 .hspuls_end = 264,
 417                 .hspuls_switch = 88,
 418                 .vspuls_begin = 440,
 419                 .vspuls_end = 2200,
 420                 .vspuls_bline = 0,
 421                 .vspuls_eline = 4,
 422                 .havon_begin = 516,
 423                 .havon_end = 4355,
 424                 .vavon_bline = 20,
 425                 .vavon_eline = 559,
 426                 .eqpuls_begin = 2288,
 427                 .eqpuls_begin_present = true,
 428                 .eqpuls_end = 2464,
 429                 .eqpuls_end_present = true,
 430                 .eqpuls_bline = 0,
 431                 .eqpuls_bline_present = true,
 432                 .eqpuls_eline = 4,
 433                 .eqpuls_eline_present = true,
 434                 .hso_begin = 264,
 435                 .hso_end = 176,
 436                 .vso_begin = 88,
 437                 .vso_end = 88,
 438                 .vso_bline = 0,
 439                 .vso_eline = 5,
 440                 .vso_eline_present = true,
 441                 /* sy_val */
 442                 /* sy2_val */
 443                 .max_lncnt = 1124,
 444         },
 445 };
 446
 447 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
 448         .encp = {
 449                 .dvi_settings = 0x202d,
 450                 .video_mode = 0x5ffc,
 451                 .video_mode_adv = 0x19,
 452                 .video_prog_mode = 0x100,
 453                 .video_prog_mode_present = true,
 454                 .video_sync_mode = 0x7,
 455                 .video_sync_mode_present = true,
 456                 /* video_yc_dly */
 457                 /* video_rgb_ctrl */
 458                 /* video_filt_ctrl */
 459                 .video_ofld_voav_ofst = 0x11,
 460                 .video_ofld_voav_ofst_present = true,
 461                 .yfp1_htime = 526,
 462                 .yfp2_htime = 4365,
 463                 .max_pxcnt = 5279,
 464                 .hspuls_begin = 88,
 465                 .hspuls_end = 264,
 466                 .hspuls_switch = 88,
 467                 .vspuls_begin = 440,
 468                 .vspuls_end = 2200,
 469                 .vspuls_bline = 0,
 470                 .vspuls_eline = 4,
 471                 .havon_begin = 526,
 472                 .havon_end = 4365,
 473                 .vavon_bline = 20,
 474                 .vavon_eline = 559,
 475                 .eqpuls_begin = 2288,
 476                 .eqpuls_begin_present = true,
 477                 .eqpuls_end = 2464,
 478                 .eqpuls_end_present = true,
 479                 .eqpuls_bline = 0,
 480                 .eqpuls_bline_present = true,
 481                 .eqpuls_eline = 4,
 482                 .eqpuls_eline_present = true,
 483                 .hso_begin = 142,
 484                 .hso_end = 230,
 485                 .vso_begin = 142,
 486                 .vso_end = 142,
 487                 .vso_bline = 0,
 488                 .vso_eline = 5,
 489                 .vso_eline_present = true,
 490                 /* sy_val */
 491                 /* sy2_val */
 492                 .max_lncnt = 1124,
 493         },
 494 };
 495
 496 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
 497         .encp = {
 498                 .dvi_settings = 0xd,
 499                 .video_mode = 0x4040,
 500                 .video_mode_adv = 0x18,
 501                 .video_prog_mode = 0x100,
 502                 .video_prog_mode_present = true,
 503                 .video_sync_mode = 0x7,
 504                 .video_sync_mode_present = true,
 505                 .video_yc_dly = 0,
 506                 .video_yc_dly_present = true,
 507                 .video_rgb_ctrl = 2,
 508                 .video_rgb_ctrl_present = true,
 509                 .video_filt_ctrl = 0x1052,
 510                 .video_filt_ctrl_present = true,
 511                 /* video_ofld_voav_ofst */
 512                 .yfp1_htime = 271,
 513                 .yfp2_htime = 2190,
 514                 .max_pxcnt = 2749,
 515                 .hspuls_begin = 44,
 516                 .hspuls_end = 132,
 517                 .hspuls_switch = 44,
 518                 .vspuls_begin = 220,
 519                 .vspuls_end = 2140,
 520                 .vspuls_bline = 0,
 521                 .vspuls_eline = 4,
 522                 .havon_begin = 271,
 523                 .havon_end = 2190,
 524                 .vavon_bline = 41,
 525                 .vavon_eline = 1120,
 526                 /* eqpuls_begin */
 527                 /* eqpuls_end */
 528                 .eqpuls_bline = 0,
 529                 .eqpuls_bline_present = true,
 530                 .eqpuls_eline = 4,
 531                 .eqpuls_eline_present = true,
 532                 .hso_begin = 79,
 533                 .hso_end = 123,
 534                 .vso_begin = 79,
 535                 .vso_end = 79,
 536                 .vso_bline = 0,
 537                 .vso_eline = 5,
 538                 .vso_eline_present = true,
 539                 /* sy_val */
 540                 /* sy2_val */
 541                 .max_lncnt = 1124,
 542         },
 543 };
 544
 545 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
 546         .encp = {
 547                 .dvi_settings = 0x1,
 548                 .video_mode = 0x4040,
 549                 .video_mode_adv = 0x18,
 550                 .video_prog_mode = 0x100,
 551                 .video_prog_mode_present = true,
 552                 /* video_sync_mode */
 553                 /* video_yc_dly */
 554                 /* video_rgb_ctrl */
 555                 .video_filt_ctrl = 0x1052,
 556                 .video_filt_ctrl_present = true,
 557                 /* video_ofld_voav_ofst */
 558                 .yfp1_htime = 140,
 559                 .yfp2_htime = 2060,
 560                 .max_pxcnt = 2199,
 561                 .hspuls_begin = 2156,
 562                 .hspuls_end = 44,
 563                 .hspuls_switch = 44,
 564                 .vspuls_begin = 140,
 565                 .vspuls_end = 2059,
 566                 .vspuls_bline = 0,
 567                 .vspuls_eline = 4,
 568                 .havon_begin = 148,
 569                 .havon_end = 2067,
 570                 .vavon_bline = 41,
 571                 .vavon_eline = 1120,
 572                 /* eqpuls_begin */
 573                 /* eqpuls_end */
 574                 /* eqpuls_bline */
 575                 /* eqpuls_eline */
 576                 .hso_begin = 44,
 577                 .hso_end = 2156,
 578                 .vso_begin = 2100,
 579                 .vso_end = 2164,
 580                 .vso_bline = 0,
 581                 .vso_eline = 5,
 582                 .vso_eline_present = true,
 583                 /* sy_val */
 584                 /* sy2_val */
 585                 .max_lncnt = 1124,
 586         },
 587 };
 588
 589 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
 590         .encp = {
 591                 .dvi_settings = 0xd,
 592                 .video_mode = 0x4040,
 593                 .video_mode_adv = 0x18,
 594                 .video_prog_mode = 0x100,
 595                 .video_prog_mode_present = true,
 596                 .video_sync_mode = 0x7,
 597                 .video_sync_mode_present = true,
 598                 .video_yc_dly = 0,
 599                 .video_yc_dly_present = true,
 600                 .video_rgb_ctrl = 2,
 601                 .video_rgb_ctrl_present = true,
 602                 /* video_filt_ctrl */
 603                 /* video_ofld_voav_ofst */
 604                 .yfp1_htime = 271,
 605                 .yfp2_htime = 2190,
 606                 .max_pxcnt = 2639,
 607                 .hspuls_begin = 44,
 608                 .hspuls_end = 132,
 609                 .hspuls_switch = 44,
 610                 .vspuls_begin = 220,
 611                 .vspuls_end = 2140,
 612                 .vspuls_bline = 0,
 613                 .vspuls_eline = 4,
 614                 .havon_begin = 271,
 615                 .havon_end = 2190,
 616                 .vavon_bline = 41,
 617                 .vavon_eline = 1120,
 618                 /* eqpuls_begin */
 619                 /* eqpuls_end */
 620                 .eqpuls_bline = 0,
 621                 .eqpuls_bline_present = true,
 622                 .eqpuls_eline = 4,
 623                 .eqpuls_eline_present = true,
 624                 .hso_begin = 79,
 625                 .hso_end = 123,
 626                 .vso_begin = 79,
 627                 .vso_end = 79,
 628                 .vso_bline = 0,
 629                 .vso_eline = 5,
 630                 .vso_eline_present = true,
 631                 /* sy_val */
 632                 /* sy2_val */
 633                 .max_lncnt = 1124,
 634         },
 635 };
 636
 637 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
 638         .encp = {
 639                 .dvi_settings = 0x1,
 640                 .video_mode = 0x4040,
 641                 .video_mode_adv = 0x18,
 642                 .video_prog_mode = 0x100,
 643                 .video_prog_mode_present = true,
 644                 /* video_sync_mode */
 645                 /* video_yc_dly */
 646                 /* video_rgb_ctrl */
 647                 .video_filt_ctrl = 0x1052,
 648                 .video_filt_ctrl_present = true,
 649                 /* video_ofld_voav_ofst */
 650                 .yfp1_htime = 140,
 651                 .yfp2_htime = 2060,
 652                 .max_pxcnt = 2199,
 653                 .hspuls_begin = 2156,
 654                 .hspuls_end = 44,
 655                 .hspuls_switch = 44,
 656                 .vspuls_begin = 140,
 657                 .vspuls_end = 2059,
 658                 .vspuls_bline = 0,
 659                 .vspuls_eline = 4,
 660                 .havon_begin = 148,
 661                 .havon_end = 2067,
 662                 .vavon_bline = 41,
 663                 .vavon_eline = 1120,
 664                 /* eqpuls_begin */
 665                 /* eqpuls_end */
 666                 /* eqpuls_bline */
 667                 /* eqpuls_eline */
 668                 .hso_begin = 44,
 669                 .hso_end = 2156,
 670                 .vso_begin = 2100,
 671                 .vso_end = 2164,
 672                 .vso_bline = 0,
 673                 .vso_eline = 5,
 674                 .vso_eline_present = true,
 675                 /* sy_val */
 676                 /* sy2_val */
 677                 .max_lncnt = 1124,
 678         },
 679 };
 680
 681 static signed int to_signed(unsigned int a)
 682 {
 683         if (a <= 7)
 684                 return a;
 685         else
 686                 return a - 16;
 687 }
 688
 689 static unsigned long modulo(unsigned long a, unsigned long b)
 690 {
 691         if (a >= b)
 692                 return a - b;
 693         else
 694                 return a;
 695 }
 696
 697 bool meson_venc_hdmi_supported_mode(const struct display_timing *mode)
 698 {
 699         if (mode->flags & ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH |
 700                             DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH))
 701                 return false;
 702
 703         if (mode->hactive.typ < 640 || mode->hactive.typ > 1920)
 704                 return false;
 705
 706         if (mode->vactive.typ < 480 || mode->vactive.typ > 1200)
 707                 return false;
 708
 709         return true;
 710 }
 711
 712 static void meson_venc_hdmi_get_dmt_vmode(const struct display_timing *mode,
 713                                           union meson_hdmi_venc_mode *dmt_mode)
 714 {
 715         memset(dmt_mode, 0, sizeof(*dmt_mode));
 716
 717         dmt_mode->encp.dvi_settings = 0x21;
 718         dmt_mode->encp.video_mode = 0x4040;
 719         dmt_mode->encp.video_mode_adv = 0x18;
 720
 721         dmt_mode->encp.max_pxcnt = mode->hactive.typ +
 722                                    mode->hfront_porch.typ +
 723                                    mode->hback_porch.typ +
 724                                    mode->hsync_len.typ - 1;
 725
 726         dmt_mode->encp.havon_begin = mode->hback_porch.typ +
 727                                      mode->hsync_len.typ;
 728
 729         dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
 730                                    mode->hactive.typ - 1;
 731
 732         dmt_mode->encp.vavon_bline = mode->vback_porch.typ +
 733                                      mode->vsync_len.typ;
 734         dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
 735                                      mode->vactive.typ - 1;
 736
 737         /* to investigate */
 738         dmt_mode->encp.hso_begin = 0;
 739         dmt_mode->encp.hso_end = mode->hsync_len.typ;
 740         dmt_mode->encp.vso_begin = 30;
 741         dmt_mode->encp.vso_end = 50;
 742
 743         dmt_mode->encp.vso_bline = 0;
 744         dmt_mode->encp.vso_eline = mode->vsync_len.typ;
 745         dmt_mode->encp.vso_eline_present = true;
 746
 747         dmt_mode->encp.max_lncnt = mode->vactive.typ +
 748                             mode->vfront_porch.typ +
 749                             mode->vback_porch.typ +
 750                             mode->vsync_len.typ - 1;
 751 }
 752
 753 static void meson_venc_hdmi_mode_set(struct meson_vpu_priv *priv,
 754                                      const struct display_timing *mode)
 755 {
 756         union meson_hdmi_venc_mode *vmode = NULL;
 757         union meson_hdmi_venc_mode vmode_dmt;
 758         bool use_enci = false;
 759         bool venc_repeat = false;
 760         bool hdmi_repeat = false;
 761         unsigned int venc_hdmi_latency = 2;
 762         unsigned long total_pixels_venc = 0;
 763         unsigned long active_pixels_venc = 0;
 764         unsigned long front_porch_venc = 0;
 765         unsigned long hsync_pixels_venc = 0;
 766         unsigned long de_h_begin = 0;
 767         unsigned long de_h_end = 0;
 768         unsigned long de_v_begin_even = 0;
 769         unsigned long de_v_end_even = 0;
 770         unsigned long de_v_begin_odd = 0;
 771         unsigned long de_v_end_odd = 0;
 772         unsigned long hs_begin = 0;
 773         unsigned long hs_end = 0;
 774         unsigned long vs_adjust = 0;
 775         unsigned long vs_bline_evn = 0;
 776         unsigned long vs_eline_evn = 0;
 777         unsigned long vs_bline_odd = 0;
 778         unsigned long vs_eline_odd = 0;
 779         unsigned long vso_begin_evn = 0;
 780         unsigned long vso_begin_odd = 0;
 781         unsigned int eof_lines;
 782         unsigned int sof_lines;
 783         unsigned int vsync_lines;
 784         u32 reg;
 785
 786         /* Use VENCI for 480i and 576i and double HDMI pixels */
 787         if (mode->flags & DISPLAY_FLAGS_DOUBLECLK) {
 788                 hdmi_repeat = true;
 789                 use_enci = true;
 790                 venc_hdmi_latency = 1;
 791         }
 792
 793         meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
 794         vmode = &vmode_dmt;
 795         use_enci = false;
 796
 797         debug(" max_pxcnt   %04d, max_lncnt   %04d\n"
 798               " havon_begin %04d, havon_end   %04d\n"
 799               " vavon_bline %04d, vavon_eline %04d\n"
 800               " hso_begin   %04d, hso_end     %04d\n"
 801               " vso_begin   %04d, vso_end     %04d\n"
 802               " vso_bline   %04d, vso_eline   %04d\n",
 803                 vmode->encp.max_pxcnt,   vmode->encp.max_lncnt,
 804                 vmode->encp.havon_begin, vmode->encp.havon_end,
 805                 vmode->encp.vavon_bline, vmode->encp.vavon_eline,
 806                 vmode->encp.hso_begin,   vmode->encp.hso_end,
 807                 vmode->encp.vso_begin,   vmode->encp.vso_end,
 808                 vmode->encp.vso_bline,   vmode->encp.vso_eline);
 809
 810         eof_lines = mode->vfront_porch.typ;
 811         if (mode->flags & DISPLAY_FLAGS_INTERLACED)
 812                 eof_lines /= 2;
 813
 814         sof_lines = mode->vback_porch.typ;
 815         if (mode->flags & DISPLAY_FLAGS_INTERLACED)
 816                 sof_lines /= 2;
 817
 818         vsync_lines = mode->vsync_len.typ;
 819         if (mode->flags & DISPLAY_FLAGS_INTERLACED)
 820                 vsync_lines /= 2;
 821
 822         total_pixels_venc = mode->hback_porch.typ + mode->hactive.typ +
 823                         mode->hfront_porch.typ + mode->hsync_len.typ;
 824         if (hdmi_repeat)
 825                 total_pixels_venc /= 2;
 826         if (venc_repeat)
 827                 total_pixels_venc *= 2;
 828
 829         active_pixels_venc = mode->hactive.typ;
 830         if (hdmi_repeat)
 831                 active_pixels_venc /= 2;
 832         if (venc_repeat)
 833                 active_pixels_venc *= 2;
 834
 835         front_porch_venc = mode->hfront_porch.typ;
 836         if (hdmi_repeat)
 837                 front_porch_venc /= 2;
 838         if (venc_repeat)
 839                 front_porch_venc *= 2;
 840
 841         hsync_pixels_venc = mode->hsync_len.typ;
 842         if (hdmi_repeat)
 843                 hsync_pixels_venc /= 2;
 844         if (venc_repeat)
 845                 hsync_pixels_venc *= 2;
 846
 847         /* Disable VDACs */
 848         writel_bits(0xff, 0xff,
 849                     priv->io_base + _REG(VENC_VDAC_SETTING));
 850
 851         writel(0, priv->io_base + _REG(ENCI_VIDEO_EN));
 852         writel(0, priv->io_base + _REG(ENCP_VIDEO_EN));
 853
 854         debug("use_enci: %d, hdmi_repeat: %d\n", use_enci, hdmi_repeat);
 855
 856         if (use_enci) {
 857                 unsigned int lines_f0;
 858                 unsigned int lines_f1;
 859
 860                 /* CVBS Filter settings */
 861                 writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
 862                        priv->io_base + _REG(ENCI_CFILT_CTRL));
 863                 writel(ENCI_CFILT_CMPT_CR_DLY(2) |
 864                        ENCI_CFILT_CMPT_CB_DLY(1),
 865                        priv->io_base + _REG(ENCI_CFILT_CTRL2));
 866
 867                 /* Digital Video Select : Interlace, clk27 clk, external */
 868                 writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
 869
 870                 /* Reset Video Mode */
 871                 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
 872                 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
 873
 874                 /* Horizontal sync signal output */
 875                 writel(vmode->enci.hso_begin,
 876                        priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
 877                 writel(vmode->enci.hso_end,
 878                        priv->io_base + _REG(ENCI_SYNC_HSO_END));
 879
 880                 /* Vertical Sync lines */
 881                 writel(vmode->enci.vso_even,
 882                        priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
 883                 writel(vmode->enci.vso_odd,
 884                        priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
 885
 886                 /* Macrovision max amplitude change */
 887                 writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
 888                        ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp),
 889                        priv->io_base + _REG(ENCI_MACV_MAX_AMP));
 890
 891                 /* Video mode */
 892                 writel(vmode->enci.video_prog_mode,
 893                        priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
 894                 writel(vmode->enci.video_mode,
 895                        priv->io_base + _REG(ENCI_VIDEO_MODE));
 896
 897                 /*
 898                  * Advanced Video Mode :
 899                  * Demux shifting 0x2
 900                  * Blank line end at line17/22
 901                  * High bandwidth Luma Filter
 902                  * Low bandwidth Chroma Filter
 903                  * Bypass luma low pass filter
 904                  * No macrovision on CSYNC
 905                  */
 906                 writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
 907                        ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
 908                        ENCI_VIDEO_MODE_ADV_YBW_HIGH,
 909                        priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
 910
 911                 writel(vmode->enci.sch_adjust,
 912                        priv->io_base + _REG(ENCI_VIDEO_SCH));
 913
 914                 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
 915                 writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
 916
 917                 if (vmode->enci.yc_delay)
 918                         writel(vmode->enci.yc_delay,
 919                                priv->io_base + _REG(ENCI_YC_DELAY));
 920
 921                 /* UNreset Interlaced TV Encoder */
 922                 writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
 923
 924                 /*
 925                  * Enable Vfifo2vd and set Y_Cb_Y_Cr:
 926                  * Corresponding value:
 927                  * Y  => 00 or 10
 928                  * Cb => 01
 929                  * Cr => 11
 930                  * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
 931                  */
 932                 writel(ENCI_VFIFO2VD_CTL_ENABLE |
 933                        ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
 934                        priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
 935
 936                 /* Timings */
 937                 writel(vmode->enci.pixel_start,
 938                        priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
 939                 writel(vmode->enci.pixel_end,
 940                        priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
 941
 942                 writel(vmode->enci.top_field_line_start,
 943                        priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
 944                 writel(vmode->enci.top_field_line_end,
 945                        priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
 946
 947                 writel(vmode->enci.bottom_field_line_start,
 948                        priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
 949                 writel(vmode->enci.bottom_field_line_end,
 950                        priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
 951
 952                 /* Select ENCI for VIU */
 953                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
 954
 955                 /* Interlace video enable */
 956                 writel(ENCI_VIDEO_EN_ENABLE,
 957                        priv->io_base + _REG(ENCI_VIDEO_EN));
 958
 959                 lines_f0 = mode->vback_porch.typ + mode->vactive.typ +
 960                            mode->vback_porch.typ + mode->vsync_len.typ;
 961                 lines_f0 = lines_f0 >> 1;
 962                 lines_f1 = lines_f0 + 1;
 963
 964                 de_h_begin = modulo(readl(priv->io_base +
 965                                         _REG(ENCI_VFIFO2VD_PIXEL_START))
 966                                         + venc_hdmi_latency,
 967                                     total_pixels_venc);
 968                 de_h_end  = modulo(de_h_begin + active_pixels_venc,
 969                                    total_pixels_venc);
 970
 971                 writel(de_h_begin,
 972                        priv->io_base + _REG(ENCI_DE_H_BEGIN));
 973                 writel(de_h_end,
 974                        priv->io_base + _REG(ENCI_DE_H_END));
 975
 976                 de_v_begin_even = readl(priv->io_base +
 977                                         _REG(ENCI_VFIFO2VD_LINE_TOP_START));
 978                 de_v_end_even  = de_v_begin_even + mode->vactive.typ;
 979                 de_v_begin_odd = readl(priv->io_base +
 980                                         _REG(ENCI_VFIFO2VD_LINE_BOT_START));
 981                 de_v_end_odd = de_v_begin_odd + mode->vactive.typ;
 982
 983                 writel(de_v_begin_even,
 984                        priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
 985                 writel(de_v_end_even,
 986                        priv->io_base + _REG(ENCI_DE_V_END_EVEN));
 987                 writel(de_v_begin_odd,
 988                        priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
 989                 writel(de_v_end_odd,
 990                        priv->io_base + _REG(ENCI_DE_V_END_ODD));
 991
 992                 /* Program Hsync timing */
 993                 hs_begin = de_h_end + front_porch_venc;
 994                 if (de_h_end + front_porch_venc >= total_pixels_venc) {
 995                         hs_begin -= total_pixels_venc;
 996                         vs_adjust  = 1;
 997                 } else {
 998                         hs_begin = de_h_end + front_porch_venc;
 999                         vs_adjust  = 0;
1000                 }
1001
1002                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1003                                 total_pixels_venc);
1004                 writel(hs_begin,
1005                        priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1006                 writel(hs_end,
1007                        priv->io_base + _REG(ENCI_DVI_HSO_END));
1008
1009                 /* Program Vsync timing for even field */
1010                 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1011                         vs_bline_evn = (de_v_end_odd - 1)
1012                                         + eof_lines
1013                                         + vs_adjust
1014                                         - lines_f1;
1015                         vs_eline_evn = vs_bline_evn + vsync_lines;
1016
1017                         writel(vs_bline_evn,
1018                                priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1019
1020                         writel(vs_eline_evn,
1021                                priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1022
1023                         writel(hs_begin,
1024                                priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1025                         writel(hs_begin,
1026                                priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1027                 } else {
1028                         vs_bline_odd = (de_v_end_odd - 1)
1029                                         + eof_lines
1030                                         + vs_adjust;
1031
1032                         writel(vs_bline_odd,
1033                                priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1034
1035                         writel(hs_begin,
1036                                priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1037
1038                         if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1039                                 vs_eline_evn = vs_bline_odd
1040                                                 + vsync_lines
1041                                                 - lines_f1;
1042
1043                                 writel(vs_eline_evn, priv->io_base
1044                                        + _REG(ENCI_DVI_VSO_ELINE_EVN));
1045
1046                                 writel(hs_begin, priv->io_base
1047                                        + _REG(ENCI_DVI_VSO_END_EVN));
1048                         } else {
1049                                 vs_eline_odd = vs_bline_odd
1050                                                 + vsync_lines;
1051
1052                                 writel(vs_eline_odd, priv->io_base
1053                                        + _REG(ENCI_DVI_VSO_ELINE_ODD));
1054
1055                                 writel(hs_begin, priv->io_base
1056                                        + _REG(ENCI_DVI_VSO_END_ODD));
1057                         }
1058                 }
1059
1060                 /* Program Vsync timing for odd field */
1061                 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1062                         vs_bline_odd = (de_v_end_even - 1)
1063                                         + (eof_lines + 1)
1064                                         - lines_f0;
1065                         vs_eline_odd = vs_bline_odd + vsync_lines;
1066
1067                         writel(vs_bline_odd,
1068                                priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1069
1070                         writel(vs_eline_odd,
1071                                priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1072
1073                         vso_begin_odd  = modulo(hs_begin
1074                                                 + (total_pixels_venc >> 1),
1075                                                 total_pixels_venc);
1076
1077                         writel(vso_begin_odd,
1078                                priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1079                         writel(vso_begin_odd,
1080                                priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1081                 } else {
1082                         vs_bline_evn = (de_v_end_even - 1)
1083                                         + (eof_lines + 1);
1084
1085                         writel(vs_bline_evn,
1086                                priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1087
1088                         vso_begin_evn  = modulo(hs_begin
1089                                                 + (total_pixels_venc >> 1),
1090                                                 total_pixels_venc);
1091
1092                         writel(vso_begin_evn, priv->io_base
1093                                         + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1094
1095                         if (vs_bline_evn + vsync_lines >= lines_f0) {
1096                                 vs_eline_odd = vs_bline_evn
1097                                                 + vsync_lines
1098                                                 - lines_f0;
1099
1100                                 writel(vs_eline_odd, priv->io_base
1101                                                 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1102
1103                                 writel(vso_begin_evn, priv->io_base
1104                                                 + _REG(ENCI_DVI_VSO_END_ODD));
1105                         } else {
1106                                 vs_eline_evn = vs_bline_evn + vsync_lines;
1107
1108                                 writel(vs_eline_evn, priv->io_base
1109                                                 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1110
1111                                 writel(vso_begin_evn, priv->io_base
1112                                                 + _REG(ENCI_DVI_VSO_END_EVN));
1113                         }
1114                 }
1115         } else {
1116                 writel(vmode->encp.dvi_settings,
1117                        priv->io_base + _REG(VENC_DVI_SETTING));
1118                 writel(vmode->encp.video_mode,
1119                        priv->io_base + _REG(ENCP_VIDEO_MODE));
1120                 writel(vmode->encp.video_mode_adv,
1121                        priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1122                 if (vmode->encp.video_prog_mode_present)
1123                         writel(vmode->encp.video_prog_mode,
1124                                priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1125                 if (vmode->encp.video_sync_mode_present)
1126                         writel(vmode->encp.video_sync_mode,
1127                                priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1128                 if (vmode->encp.video_yc_dly_present)
1129                         writel(vmode->encp.video_yc_dly,
1130                                priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1131                 if (vmode->encp.video_rgb_ctrl_present)
1132                         writel(vmode->encp.video_rgb_ctrl,
1133                                priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1134                 if (vmode->encp.video_filt_ctrl_present)
1135                         writel(vmode->encp.video_filt_ctrl,
1136                                priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1137                 if (vmode->encp.video_ofld_voav_ofst_present)
1138                         writel(vmode->encp.video_ofld_voav_ofst,
1139                                priv->io_base
1140                                + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1141                 writel(vmode->encp.yfp1_htime,
1142                        priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1143                 writel(vmode->encp.yfp2_htime,
1144                        priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1145                 writel(vmode->encp.max_pxcnt,
1146                        priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1147                 writel(vmode->encp.hspuls_begin,
1148                        priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1149                 writel(vmode->encp.hspuls_end,
1150                        priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1151                 writel(vmode->encp.hspuls_switch,
1152                        priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1153                 writel(vmode->encp.vspuls_begin,
1154                        priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1155                 writel(vmode->encp.vspuls_end,
1156                        priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1157                 writel(vmode->encp.vspuls_bline,
1158                        priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1159                 writel(vmode->encp.vspuls_eline,
1160                        priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1161                 if (vmode->encp.eqpuls_begin_present)
1162                         writel(vmode->encp.eqpuls_begin,
1163                                priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1164                 if (vmode->encp.eqpuls_end_present)
1165                         writel(vmode->encp.eqpuls_end,
1166                                priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1167                 if (vmode->encp.eqpuls_bline_present)
1168                         writel(vmode->encp.eqpuls_bline,
1169                                priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1170                 if (vmode->encp.eqpuls_eline_present)
1171                         writel(vmode->encp.eqpuls_eline,
1172                                priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1173                 writel(vmode->encp.havon_begin,
1174                        priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1175                 writel(vmode->encp.havon_end,
1176                        priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1177                 writel(vmode->encp.vavon_bline,
1178                        priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1179                 writel(vmode->encp.vavon_eline,
1180                        priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1181                 writel(vmode->encp.hso_begin,
1182                        priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1183                 writel(vmode->encp.hso_end,
1184                        priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1185                 writel(vmode->encp.vso_begin,
1186                        priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1187                 writel(vmode->encp.vso_end,
1188                        priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1189                 writel(vmode->encp.vso_bline,
1190                        priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1191                 if (vmode->encp.vso_eline_present)
1192                         writel(vmode->encp.vso_eline,
1193                                priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1194                 if (vmode->encp.sy_val_present)
1195                         writel(vmode->encp.sy_val,
1196                                priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1197                 if (vmode->encp.sy2_val_present)
1198                         writel(vmode->encp.sy2_val,
1199                                priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1200                 writel(vmode->encp.max_lncnt,
1201                        priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1202
1203                 writel(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1204
1205                 /* Set DE signal's polarity is active high */
1206                 writel_bits(ENCP_VIDEO_MODE_DE_V_HIGH,
1207                             ENCP_VIDEO_MODE_DE_V_HIGH,
1208                             priv->io_base + _REG(ENCP_VIDEO_MODE));
1209
1210                 /* Program DE timing */
1211                 de_h_begin = modulo(readl(priv->io_base +
1212                                         _REG(ENCP_VIDEO_HAVON_BEGIN))
1213                                         + venc_hdmi_latency,
1214                                     total_pixels_venc);
1215                 de_h_end = modulo(de_h_begin + active_pixels_venc,
1216                                   total_pixels_venc);
1217
1218                 writel(de_h_begin,
1219                        priv->io_base + _REG(ENCP_DE_H_BEGIN));
1220                 writel(de_h_end,
1221                        priv->io_base + _REG(ENCP_DE_H_END));
1222
1223                 /* Program DE timing for even field */
1224                 de_v_begin_even = readl(priv->io_base
1225                                                 + _REG(ENCP_VIDEO_VAVON_BLINE));
1226                 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
1227                         de_v_end_even = de_v_begin_even +
1228                                         (mode->vactive.typ / 2);
1229                 else
1230                         de_v_end_even = de_v_begin_even + mode->vactive.typ;
1231
1232                 writel(de_v_begin_even,
1233                        priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1234                 writel(de_v_end_even,
1235                        priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1236
1237                 /* Program DE timing for odd field if needed */
1238                 if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
1239                         unsigned int ofld_voav_ofst =
1240                                 readl(priv->io_base +
1241                                         _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1242                         de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1243                                         + de_v_begin_even
1244                                         + ((mode->vfront_porch.typ +
1245                                             mode->vactive.typ +
1246                                             mode->vsync_len.typ - 1) / 2);
1247                         de_v_end_odd = de_v_begin_odd + (mode->vactive.typ / 2);
1248
1249                         writel(de_v_begin_odd,
1250                                priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1251                         writel(de_v_end_odd,
1252                                priv->io_base + _REG(ENCP_DE_V_END_ODD));
1253                 }
1254
1255                 /* Program Hsync timing */
1256                 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1257                         hs_begin = de_h_end
1258                                    + front_porch_venc
1259                                    - total_pixels_venc;
1260                         vs_adjust  = 1;
1261                 } else {
1262                         hs_begin = de_h_end
1263                                    + front_porch_venc;
1264                         vs_adjust  = 0;
1265                 }
1266
1267                 hs_end = modulo(hs_begin + hsync_pixels_venc,
1268                                 total_pixels_venc);
1269
1270                 writel(hs_begin,
1271                        priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1272                 writel(hs_end,
1273                        priv->io_base + _REG(ENCP_DVI_HSO_END));
1274
1275                 /* Program Vsync timing for even field */
1276                 if (de_v_begin_even >=
1277                                 (sof_lines + vsync_lines + (1 - vs_adjust)))
1278                         vs_bline_evn = de_v_begin_even
1279                                         - sof_lines
1280                                         - vsync_lines
1281                                         - (1 - vs_adjust);
1282                 else
1283                         vs_bline_evn = (mode->vfront_porch.typ +
1284                                         mode->vactive.typ +
1285                                         mode->vsync_len.typ) +
1286                                         + de_v_begin_even
1287                                         - sof_lines
1288                                         - vsync_lines
1289                                         - (1 - vs_adjust);
1290
1291                 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1292                                       mode->hfront_porch.typ +
1293                                       mode->hactive.typ +
1294                                       mode->hsync_len.typ);
1295
1296                 writel(vs_bline_evn,
1297                        priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1298                 writel(vs_eline_evn,
1299                        priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1300
1301                 vso_begin_evn = hs_begin;
1302                 writel(vso_begin_evn,
1303                        priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1304                 writel(vso_begin_evn,
1305                        priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1306
1307                 /* Program Vsync timing for odd field if needed */
1308                 if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
1309                         vs_bline_odd = (de_v_begin_odd - 1)
1310                                         - sof_lines
1311                                         - vsync_lines;
1312                         vs_eline_odd = (de_v_begin_odd - 1)
1313                                         - vsync_lines;
1314                         vso_begin_odd  = modulo(hs_begin
1315                                                 + (total_pixels_venc >> 1),
1316                                                 total_pixels_venc);
1317
1318                         writel(vs_bline_odd,
1319                                priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1320                         writel(vs_eline_odd,
1321                                priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1322                         writel(vso_begin_odd,
1323                                priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1324                         writel(vso_begin_odd,
1325                                priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1326                 }
1327
1328                 /* Select ENCP for VIU */
1329                 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1330         }
1331
1332         /* Set VPU HDMI setting */
1333         /* Select ENCP or ENCI data to HDMI */
1334         if (use_enci)
1335                 reg = VPU_HDMI_ENCI_DATA_TO_HDMI;
1336         else
1337                 reg = VPU_HDMI_ENCP_DATA_TO_HDMI;
1338
1339         /* Invert polarity of HSYNC from VENC */
1340         if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
1341                 reg |= VPU_HDMI_INV_HSYNC;
1342
1343         /* Invert polarity of VSYNC from VENC */
1344         if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
1345                 reg |= VPU_HDMI_INV_VSYNC;
1346
1347         /* Output data format: CbYCr */
1348         reg |= VPU_HDMI_OUTPUT_CBYCR;
1349
1350         /*
1351          * Write rate to the async FIFO between VENC and HDMI.
1352          * One write every 2 wr_clk.
1353          */
1354         if (venc_repeat)
1355                 reg |= VPU_HDMI_WR_RATE(2);
1356
1357         /*
1358          * Read rate to the async FIFO between VENC and HDMI.
1359          * One read every 2 wr_clk.
1360          */
1361         if (hdmi_repeat)
1362                 reg |= VPU_HDMI_RD_RATE(2);
1363
1364         writel(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
1365 }
1366
1367 static void meson_venci_cvbs_mode_set(struct meson_vpu_priv *priv,
1368                                       struct meson_cvbs_enci_mode *mode)
1369 {
1370         u32 reg;
1371
1372         /* CVBS Filter settings */
1373         writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
1374                priv->io_base + _REG(ENCI_CFILT_CTRL));
1375         writel(ENCI_CFILT_CMPT_CR_DLY(2) |
1376                ENCI_CFILT_CMPT_CB_DLY(1),
1377                priv->io_base + _REG(ENCI_CFILT_CTRL2));
1378
1379         /* Digital Video Select : Interlace, clk27 clk, external */
1380         writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
1381
1382         /* Reset Video Mode */
1383         writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1384         writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1385
1386         /* Horizontal sync signal output */
1387         writel(mode->hso_begin,
1388                priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1389         writel(mode->hso_end,
1390                priv->io_base + _REG(ENCI_SYNC_HSO_END));
1391
1392         /* Vertical Sync lines */
1393         writel(mode->vso_even,
1394                priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1395         writel(mode->vso_odd,
1396                priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1397
1398         /* Macrovision max amplitude change */
1399         writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
1400                ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp),
1401                priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1402
1403         /* Video mode */
1404         writel(mode->video_prog_mode,
1405                priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1406         writel(mode->video_mode,
1407                priv->io_base + _REG(ENCI_VIDEO_MODE));
1408
1409         /*
1410          * Advanced Video Mode :
1411          * Demux shifting 0x2
1412          * Blank line end at line17/22
1413          * High bandwidth Luma Filter
1414          * Low bandwidth Chroma Filter
1415          * Bypass luma low pass filter
1416          * No macrovision on CSYNC
1417          */
1418         writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
1419                ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
1420                ENCI_VIDEO_MODE_ADV_YBW_HIGH,
1421                priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1422
1423         writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1424
1425         /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1426         writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1427
1428         /* 0x3 Y, C, and Component Y delay */
1429         writel(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1430
1431         /* Timings */
1432         writel(mode->pixel_start,
1433                priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1434         writel(mode->pixel_end,
1435                priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1436
1437         writel(mode->top_field_line_start,
1438                priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1439         writel(mode->top_field_line_end,
1440                priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1441
1442         writel(mode->bottom_field_line_start,
1443                priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1444         writel(mode->bottom_field_line_end,
1445                priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1446
1447         /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1448         writel(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1449
1450         /* UNreset Interlaced TV Encoder */
1451         writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1452
1453         /*
1454          * Enable Vfifo2vd and set Y_Cb_Y_Cr:
1455          * Corresponding value:
1456          * Y  => 00 or 10
1457          * Cb => 01
1458          * Cr => 11
1459          * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
1460          */
1461         writel(ENCI_VFIFO2VD_CTL_ENABLE |
1462                ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
1463                priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1464
1465         /* Power UP Dacs */
1466         writel(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1467
1468         /* Video Upsampling */
1469         /*
1470          * CTRL0, CTRL1 and CTRL2:
1471          * Filter0: input data sample every 2 cloks
1472          * Filter1: filtering and upsample enable
1473          */
1474         reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN |
1475                 VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN;
1476
1477         /*
1478          * Upsample CTRL0:
1479          * Interlace High Bandwidth Luma
1480          */
1481         writel(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
1482                priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1483
1484         /*
1485          * Upsample CTRL1:
1486          * Interlace Pb
1487          */
1488         writel(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
1489                priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1490
1491         /*
1492          * Upsample CTRL2:
1493          * Interlace R
1494          */
1495         writel(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
1496                priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1497
1498         /* Select Interlace Y DACs */
1499         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1500         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1501         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1502         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1503         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1504         writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1505
1506         /* Select ENCI for VIU */
1507         meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1508
1509         /* Enable ENCI FIFO */
1510         writel(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
1511                priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1512
1513         /* Select ENCI DACs 0, 1, 4, and 5 */
1514         writel(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1515         writel(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1516
1517         /* Interlace video enable */
1518         writel(ENCI_VIDEO_EN_ENABLE,
1519                priv->io_base + _REG(ENCI_VIDEO_EN));
1520
1521         /* Configure Video Saturation / Contrast / Brightness / Hue */
1522         writel(mode->video_saturation,
1523                priv->io_base + _REG(ENCI_VIDEO_SAT));
1524         writel(mode->video_contrast,
1525                priv->io_base + _REG(ENCI_VIDEO_CONT));
1526         writel(mode->video_brightness,
1527                priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1528         writel(mode->video_hue,
1529                priv->io_base + _REG(ENCI_VIDEO_HUE));
1530
1531         /* Enable DAC0 Filter */
1532         writel(VENC_VDAC_DAC0_FILT_CTRL0_EN,
1533                priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1534         writel(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1535
1536         /* 0 in Macrovision register 0 */
1537         writel(0, priv->io_base + _REG(ENCI_MACV_N0));
1538
1539         /* Analog Synchronization and color burst value adjust */
1540         writel(mode->analog_sync_adj,
1541                priv->io_base + _REG(ENCI_SYNC_ADJ));
1542
1543         /* enable VDAC */
1544         writel_bits(VENC_VDAC_SEL_ATV_DMD, 0,
1545                     priv->io_base + _REG(VENC_VDAC_DACSEL0));
1546
1547         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
1548                 hhi_write(HHI_VDAC_CNTL0, 1);
1549         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
1550                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
1551                 hhi_write(HHI_VDAC_CNTL0, 0xf0001);
1552         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
1553                 hhi_write(HHI_VDAC_CNTL0_G12A, 0x906001);
1554
1555         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
1556                 hhi_write(HHI_VDAC_CNTL1_G12A, 0);
1557         else
1558                 hhi_write(HHI_VDAC_CNTL1, 0);
1559 }
1560
1561 void meson_vpu_setup_venc(struct udevice *dev,
1562                           const struct display_timing *mode, bool is_cvbs)
1563 {
1564         struct meson_vpu_priv *priv = dev_get_priv(dev);
1565
1566         if (is_cvbs)
1567                 return meson_venci_cvbs_mode_set(priv, &meson_cvbs_enci_pal);
1568
1569         meson_venc_hdmi_mode_set(priv, mode);
1570 }