drivers/video/meson/meson_dw_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 BayLibre, SAS
   4  * Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
   5  */
   6
   7 #include <common.h>
   8 #include <display.h>
   9 #include <dm.h>
  10 #include <edid.h>
  11 #include <log.h>
  12 #include <asm/io.h>
  13 #include <dw_hdmi.h>
  14 #include <dm/device-internal.h>
  15 #include <dm/uclass-internal.h>
  16 #include <linux/bitops.h>
  17 #include <power/regulator.h>
  18 #include <clk.h>
  19 #include <linux/delay.h>
  20 #include <reset.h>
  21 #include <media_bus_format.h>
  22 #include "meson_dw_hdmi.h"
  23 #include "meson_vpu.h"
  24
  25 /* TOP Block Communication Channel */
  26 #define HDMITX_TOP_ADDR_REG     0x0
  27 #define HDMITX_TOP_DATA_REG     0x4
  28 #define HDMITX_TOP_CTRL_REG     0x8
  29 #define HDMITX_TOP_G12A_OFFSET  0x8000
  30
  31 /* Controller Communication Channel */
  32 #define HDMITX_DWC_ADDR_REG     0x10
  33 #define HDMITX_DWC_DATA_REG     0x14
  34 #define HDMITX_DWC_CTRL_REG     0x18
  35
  36 /* HHI Registers */
  37 #define HHI_MEM_PD_REG0         0x100 /* 0x40 */
  38 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 */
  39 #define HHI_HDMI_PHY_CNTL0      0x3a0 /* 0xe8 */
  40 #define HHI_HDMI_PHY_CNTL1      0x3a4 /* 0xe9 */
  41 #define HHI_HDMI_PHY_CNTL2      0x3a8 /* 0xea */
  42 #define HHI_HDMI_PHY_CNTL3      0x3ac /* 0xeb */
  43 #define HHI_HDMI_PHY_CNTL4      0x3b0 /* 0xec */
  44 #define HHI_HDMI_PHY_CNTL5      0x3b4 /* 0xed */
  45
  46 struct meson_dw_hdmi {
  47         struct udevice *dev;
  48         struct dw_hdmi hdmi;
  49         void __iomem *hhi_base;
  50 };
  51
  52 enum hdmi_compatible {
  53         HDMI_COMPATIBLE_GXBB = 0,
  54         HDMI_COMPATIBLE_GXL = 1,
  55         HDMI_COMPATIBLE_GXM = 2,
  56         HDMI_COMPATIBLE_G12A = 3,
  57 };
  58
  59 static inline bool meson_hdmi_is_compatible(struct meson_dw_hdmi *priv,
  60                                             enum hdmi_compatible family)
  61 {
  62         enum hdmi_compatible compat = dev_get_driver_data(priv->dev);
  63
  64         return compat == family;
  65 }
  66
  67 static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)
  68 {
  69         struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  70                                                   hdmi);
  71         unsigned int data;
  72
  73         if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
  74                 return readl(hdmi->ioaddr +
  75                              HDMITX_TOP_G12A_OFFSET + (addr << 2));
  76
  77         /* ADDR must be written twice */
  78         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  79         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
  80
  81         /* Read needs a second DATA read */
  82         data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  83         data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);
  84
  85         return data;
  86 }
  87
  88 static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,
  89                                      unsigned int addr, unsigned int data)
  90 {
  91         struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
  92                                                   hdmi);
  93
  94         if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
  95                 writel(data, hdmi->ioaddr +
  96                        HDMITX_TOP_G12A_OFFSET + (addr << 2));
  97                 return;
  98         }
  99
 100         /* ADDR must be written twice */
 101         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
 102         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);
 103
 104         /* Write needs single DATA write */
 105         writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);
 106 }
 107
 108 static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,
 109                                           unsigned int addr,
 110                                           unsigned int mask,
 111                                           unsigned int val)
 112 {
 113         unsigned int data = dw_hdmi_top_read(hdmi, addr);
 114
 115         data &= ~mask;
 116         data |= val;
 117         dw_hdmi_top_write(hdmi, addr, data);
 118 }
 119
 120 static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)
 121 {
 122         unsigned int data;
 123
 124         /* ADDR must be written twice */
 125         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
 126         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
 127
 128         /* Read needs a second DATA read */
 129         data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
 130         data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);
 131
 132         return data;
 133 }
 134
 135 static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)
 136 {
 137         /* ADDR must be written twice */
 138         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
 139         writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);
 140
 141         /* Write needs single DATA write */
 142         writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);
 143 }
 144
 145 static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,
 146                                           unsigned int addr,
 147                                           unsigned int mask,
 148                                           unsigned int val)
 149 {
 150         u8 data = dw_hdmi_dwc_read(hdmi, addr);
 151
 152         data &= ~mask;
 153         data |= val;
 154
 155         dw_hdmi_dwc_write(hdmi, data, addr);
 156 }
 157
 158 static inline void dw_hdmi_hhi_write(struct meson_dw_hdmi *priv,
 159                                      unsigned int addr, unsigned int data)
 160 {
 161         hhi_write(addr, data);
 162 }
 163
 164 __attribute__((unused))
 165 static unsigned int dw_hdmi_hhi_read(struct meson_dw_hdmi *priv,
 166                                      unsigned int addr)
 167 {
 168         return hhi_read(addr);
 169 }
 170
 171 static inline void dw_hdmi_hhi_update_bits(struct meson_dw_hdmi *priv,
 172                                            unsigned int addr,
 173                                            unsigned int mask,
 174                                            unsigned int val)
 175 {
 176         hhi_update_bits(addr, mask, val);
 177 }
 178
 179 static int meson_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 180 {
 181 #if defined DEBUG
 182         struct display_timing timing;
 183         int panel_bits_per_colour;
 184 #endif
 185         struct meson_dw_hdmi *priv = dev_get_priv(dev);
 186         int ret;
 187
 188         ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 189
 190 #if defined DEBUG
 191         if (!ret)
 192                 return ret;
 193
 194         edid_print_info((struct edid1_info *)buf);
 195         edid_get_timing(buf, ret, &timing, &panel_bits_per_colour);
 196         debug("Display timing:\n");
 197         debug(" hactive %04d, hfrontp %04d, hbackp %04d hsync %04d\n"
 198               " vactive %04d, vfrontp %04d, vbackp %04d vsync %04d\n",
 199                timing.hactive.typ, timing.hfront_porch.typ,
 200                timing.hback_porch.typ, timing.hsync_len.typ,
 201                timing.vactive.typ, timing.vfront_porch.typ,
 202                timing.vback_porch.typ, timing.vsync_len.typ);
 203         debug(" flags: ");
 204         if (timing.flags & DISPLAY_FLAGS_INTERLACED)
 205                 debug("interlaced ");
 206         if (timing.flags & DISPLAY_FLAGS_DOUBLESCAN)
 207                 debug("doublescan ");
 208         if (timing.flags & DISPLAY_FLAGS_DOUBLECLK)
 209                 debug("doubleclk ");
 210         if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
 211                 debug("hsync_low ");
 212         if (timing.flags & DISPLAY_FLAGS_HSYNC_HIGH)
 213                 debug("hsync_high ");
 214         if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
 215                 debug("vsync_low ");
 216         if (timing.flags & DISPLAY_FLAGS_VSYNC_HIGH)
 217                 debug("vsync_high ");
 218         debug("\n");
 219 #endif
 220
 221         return ret;
 222 }
 223
 224 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi *priv)
 225 {
 226         /* Enable and software reset */
 227         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xf);
 228
 229         mdelay(2);
 230
 231         /* Enable and unreset */
 232         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0xe);
 233
 234         mdelay(2);
 235 }
 236
 237 static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
 238                                          uint pixel_clock)
 239 {
 240         pixel_clock = pixel_clock / 1000;
 241
 242         if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
 243             meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM)) {
 244                 if (pixel_clock >= 371250) {
 245                         /* 5.94Gbps, 3.7125Gbps */
 246                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x333d3282);
 247                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2136315b);
 248                 } else if (pixel_clock >= 297000) {
 249                         /* 2.97Gbps */
 250                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303382);
 251                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2036315b);
 252                 } else if (pixel_clock >= 148500) {
 253                         /* 1.485Gbps */
 254                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33303362);
 255                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2016315b);
 256                 } else {
 257                         /* 742.5Mbps, and below */
 258                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33604142);
 259                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x0016315b);
 260                 }
 261         } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXBB)) {
 262                 if (pixel_clock >= 371250) {
 263                         /* 5.94Gbps, 3.7125Gbps */
 264                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33353245);
 265                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2100115b);
 266                 } else if (pixel_clock >= 297000) {
 267                         /* 2.97Gbps */
 268                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33634283);
 269                         hhi_write(HHI_HDMI_PHY_CNTL3, 0xb000115b);
 270                 } else {
 271                         /* 1.485Gbps, and below */
 272                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33632122);
 273                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2000115b);
 274                 }
 275         } else if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
 276                 if (pixel_clock >= 371250) {
 277                         /* 5.94Gbps, 3.7125Gbps */
 278                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
 279                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
 280                         hhi_write(HHI_HDMI_PHY_CNTL5, 0x0000080b);
 281                 } else if (pixel_clock >= 297000) {
 282                         /* 2.97Gbps */
 283                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb6262);
 284                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
 285                         hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
 286                 } else {
 287                         /* 1.485Gbps, and below */
 288                         hhi_write(HHI_HDMI_PHY_CNTL0, 0x33eb4242);
 289                         hhi_write(HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
 290                         hhi_write(HHI_HDMI_PHY_CNTL5, 0x00000003);
 291                 }
 292         }
 293 }
 294
 295 static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
 296 {
 297         struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
 298                                                   hdmi);
 299         /* Enable clocks */
 300         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
 301
 302         /* Bring HDMITX MEM output of power down */
 303         dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
 304
 305         /* Bring out of reset */
 306         dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET,  0);
 307
 308         /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
 309         dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);
 310         dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);
 311
 312         /* Enable normal output to PHY */
 313         dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
 314
 315         /* TMDS pattern setup (TOFIX pattern for 4k2k scrambling) */
 316         dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
 317         dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
 318
 319         /* Load TMDS pattern */
 320         dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
 321         mdelay(20);
 322         dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
 323
 324         /* Setup PHY parameters */
 325         meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
 326
 327         /* Setup PHY */
 328         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
 329                                 0xffff << 16, 0x0390 << 16);
 330
 331         /* BIT_INVERT */
 332         if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXL) ||
 333             meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_GXM) ||
 334             meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
 335                 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, BIT(17), 0);
 336         else
 337                 dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
 338                                         BIT(17), BIT(17));
 339
 340         /* Disable clock, fifo, fifo_wr */
 341         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, 0xf, 0);
 342
 343         mdelay(100);
 344
 345         /* Reset PHY 3 times in a row */
 346         meson_dw_hdmi_phy_reset(priv);
 347         meson_dw_hdmi_phy_reset(priv);
 348         meson_dw_hdmi_phy_reset(priv);
 349
 350         return 0;
 351 }
 352
 353 static int meson_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 354                                 const struct display_timing *edid)
 355 {
 356         struct meson_dw_hdmi *priv = dev_get_priv(dev);
 357
 358         /* will back into meson_dw_hdmi_phy_init */
 359         return dw_hdmi_enable(&priv->hdmi, edid);
 360 }
 361
 362 static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)
 363 {
 364         int i;
 365
 366         /* Poll 1 second for HPD signal */
 367         for (i = 0; i < 10; ++i) {
 368                 if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))
 369                         return 0;
 370
 371                 mdelay(100);
 372         }
 373
 374         return -ETIMEDOUT;
 375 }
 376
 377 static int meson_dw_hdmi_probe(struct udevice *dev)
 378 {
 379         struct meson_dw_hdmi *priv = dev_get_priv(dev);
 380         struct reset_ctl_bulk resets;
 381         struct clk_bulk clocks;
 382         struct udevice *supply;
 383         int ret;
 384
 385         priv->dev = dev;
 386
 387         priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);
 388         if (!priv->hdmi.ioaddr)
 389                 return -EINVAL;
 390
 391         priv->hhi_base = dev_remap_addr_index(dev, 1);
 392         if (!priv->hhi_base)
 393                 return -EINVAL;
 394
 395         priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 396         priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;
 397         priv->hdmi.phy_set = meson_dw_hdmi_phy_init;
 398         if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A))
 399                 priv->hdmi.reg_io_width = 1;
 400         else {
 401                 priv->hdmi.write_reg = dw_hdmi_dwc_write;
 402                 priv->hdmi.read_reg = dw_hdmi_dwc_read;
 403         }
 404         priv->hdmi.i2c_clk_high = 0x67;
 405         priv->hdmi.i2c_clk_low = 0x78;
 406
 407 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 408         ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
 409         if (ret && ret != -ENOENT) {
 410                 pr_err("Failed to get HDMI regulator\n");
 411                 return ret;
 412         }
 413
 414         if (!ret) {
 415                 ret = regulator_set_enable(supply, true);
 416                 if (ret)
 417                         return ret;
 418         }
 419 #endif
 420
 421         uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
 422                                      &priv->hdmi.ddc_bus);
 423
 424         ret = reset_get_bulk(dev, &resets);
 425         if (ret)
 426                 return ret;
 427
 428         ret = clk_get_bulk(dev, &clocks);
 429         if (ret)
 430                 return ret;
 431
 432         ret = clk_enable_bulk(&clocks);
 433         if (ret)
 434                 return ret;
 435
 436         /* Enable clocks */
 437         dw_hdmi_hhi_update_bits(priv, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
 438
 439         /* Bring HDMITX MEM output of power down */
 440         dw_hdmi_hhi_update_bits(priv, HHI_MEM_PD_REG0, 0xff << 8, 0);
 441
 442         /* Reset HDMITX APB & TX & PHY: cycle needed for EDID */
 443         ret = reset_deassert_bulk(&resets);
 444         if (ret)
 445                 return ret;
 446
 447         ret = reset_assert_bulk(&resets);
 448         if (ret)
 449                 return ret;
 450
 451         ret = reset_deassert_bulk(&resets);
 452         if (ret)
 453                 return ret;
 454
 455         if (!meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) {
 456                 /* Enable APB3 fail on error */
 457                 writel_bits(BIT(15), BIT(15),
 458                             priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);
 459                 writel_bits(BIT(15), BIT(15),
 460                             priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);
 461         }
 462
 463         /* Bring out of reset */
 464         dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET,  0);
 465         mdelay(20);
 466         dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
 467
 468         dw_hdmi_init(&priv->hdmi);
 469         dw_hdmi_phy_init(&priv->hdmi);
 470
 471         /* wait for connector */
 472         ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);
 473         if (ret)
 474                 debug("hdmi can not get hpd signal\n");
 475
 476         return ret;
 477 }
 478
 479 static bool meson_dw_hdmi_mode_valid(struct udevice *dev,
 480                                      const struct display_timing *timing)
 481 {
 482         return meson_venc_hdmi_supported_mode(timing);
 483 }
 484
 485 static const struct dm_display_ops meson_dw_hdmi_ops = {
 486         .read_edid = meson_dw_hdmi_read_edid,
 487         .enable = meson_dw_hdmi_enable,
 488         .mode_valid = meson_dw_hdmi_mode_valid,
 489 };
 490
 491 static const struct udevice_id meson_dw_hdmi_ids[] = {
 492         { .compatible = "amlogic,meson-gxbb-dw-hdmi",
 493                 .data = HDMI_COMPATIBLE_GXBB },
 494         { .compatible = "amlogic,meson-gxl-dw-hdmi",
 495                 .data = HDMI_COMPATIBLE_GXL },
 496         { .compatible = "amlogic,meson-gxm-dw-hdmi",
 497                 .data = HDMI_COMPATIBLE_GXM },
 498         { .compatible = "amlogic,meson-g12a-dw-hdmi",
 499                 .data = HDMI_COMPATIBLE_G12A },
 500         { }
 501 };
 502
 503 U_BOOT_DRIVER(meson_dw_hdmi) = {
 504         .name = "meson_dw_hdmi",
 505         .id = UCLASS_DISPLAY,
 506         .of_match = meson_dw_hdmi_ids,
 507         .ops = &meson_dw_hdmi_ops,
 508         .probe = meson_dw_hdmi_probe,
 509         .priv_auto_alloc_size = sizeof(struct meson_dw_hdmi),
 510 };