1 // SPDX-License-Identifier: GPL-2.0+
4 * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
8 * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
9 * PCI and video mode code was derived from smiLynxEM driver.
13 #include <linux/delay.h>
19 #include "videomodes.h"
22 #if defined(CONFIG_POST)
29 GraphicDevice mb862xx;
32 * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
34 #define VIDEO_MEM_SIZE 0x01FC0000
36 #if defined(CONFIG_PCI)
37 #if defined(CONFIG_VIDEO_CORALP)
39 static struct pci_device_id supported[] = {
40 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
41 { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
45 /* Internal clock frequency divider table, index is mode number */
46 unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
50 #if defined(CONFIG_VIDEO_CORALP)
54 #define rd_io(addr) in_be32((volatile unsigned *)(addr))
55 #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
58 #define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
59 #define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
61 #define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
62 #define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
64 #define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
65 #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
67 #if defined(CONFIG_VIDEO_CORALP)
68 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
70 #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
73 #define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
74 (GC_DISP_BASE | GC_L0PAL0) + \
77 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
78 static void gdc_sw_reset (void)
80 GraphicDevice *dev = &mb862xx;
82 HOST_WR_REG (GC_SRST, 0x1);
88 static void de_wait (void)
90 GraphicDevice *dev = &mb862xx;
94 * Sync with software writes to framebuffer,
95 * try to reset if engine locked
97 while (DE_RD_REG (GC_CTR) & 0x00000131)
100 puts ("gdc reset done after drawing engine lock.\n");
105 static void de_wait_slots (int slots)
107 GraphicDevice *dev = &mb862xx;
110 /* Wait for free fifo slots */
111 while (DE_RD_REG (GC_IFCNT) < slots)
114 puts ("gdc reset done after drawing engine lock.\n");
120 #if !defined(CONFIG_VIDEO_CORALP)
121 static void board_disp_init (void)
123 GraphicDevice *dev = &mb862xx;
124 const gdc_regs *regs = board_get_regs ();
126 while (regs->index) {
127 DISP_WR_REG (regs->index, regs->value);
134 * Init drawing engine if accel enabled.
135 * Also clears visible framebuffer.
137 static void de_init (void)
139 GraphicDevice *dev = &mb862xx;
140 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
141 int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
143 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
145 /* Setup mode and fbbase, xres, fg, bg */
147 DE_WR_FIFO (0xf1010108);
148 DE_WR_FIFO (cf | 0x0300);
149 DE_WR_REG (GC_FBR, 0x0);
150 DE_WR_REG (GC_XRES, dev->winSizeX);
151 DE_WR_REG (GC_FC, 0x0);
152 DE_WR_REG (GC_BC, 0x0);
154 DE_WR_REG (GC_CXMIN, 0x0);
155 DE_WR_REG (GC_CXMAX, dev->winSizeX);
156 DE_WR_REG (GC_CYMIN, 0x0);
157 DE_WR_REG (GC_CYMAX, dev->winSizeY);
159 /* Clear framebuffer using drawing engine */
161 DE_WR_FIFO (0x09410000);
162 DE_WR_FIFO (0x00000000);
163 DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
164 /* sync with SW access to framebuffer */
169 i = dev->winSizeX * dev->winSizeY;
170 p = (unsigned int *)dev->frameAdrs;
176 #if defined(CONFIG_VIDEO_CORALP)
177 /* use CCF and MMR parameters for Coral-P Eval. Board as default */
178 #ifndef CONFIG_SYS_MB862xx_CCF
179 #define CONFIG_SYS_MB862xx_CCF 0x00090000
181 #ifndef CONFIG_SYS_MB862xx_MMR
182 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
185 unsigned int pci_video_init (void)
187 GraphicDevice *dev = &mb862xx;
191 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
192 puts("controller not present\n");
197 pci_write_config_dword (devbusfn, PCI_COMMAND,
198 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
199 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
200 dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
202 if (dev->frameAdrs == 0) {
203 puts ("PCI config: failed to get base address\n");
207 dev->pciBase = dev->frameAdrs;
211 pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
213 case PCI_DEVICE_ID_CORAL_P:
216 case PCI_DEVICE_ID_CORAL_PA:
224 /* Setup clocks and memory mode for Coral-P(A) */
225 HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
227 HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
229 return dev->frameAdrs;
232 unsigned int card_init (void)
234 GraphicDevice *dev = &mb862xx;
235 unsigned int cf, videomode, div = 0;
236 unsigned long t1, hsync, vsync;
239 struct ctfb_res_modes *res_mode;
240 struct ctfb_res_modes var_mode;
242 memset (dev, 0, sizeof (GraphicDevice));
244 if (!pci_video_init ())
249 /* get video mode via environment */
250 penv = env_get("videomode");
252 /* decide if it is a string */
253 if (penv[0] <= '9') {
254 videomode = (int) simple_strtoul (penv, NULL, 16);
262 /* parameter are vesa modes, search params */
263 for (i = 0; i < VESA_MODES_COUNT; i++) {
264 if (vesa_modes[i].vesanr == videomode)
267 if (i == VESA_MODES_COUNT) {
268 printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
272 res_mode = (struct ctfb_res_modes *)
273 &res_mode_init[vesa_modes[i].resindex];
274 if (vesa_modes[i].resindex > 2) {
275 puts ("\tUnsupported resolution, using default\n");
276 bpp = vesa_modes[1].bits_per_pixel;
279 bpp = vesa_modes[i].bits_per_pixel;
280 div = fr_div[vesa_modes[i].resindex];
282 res_mode = (struct ctfb_res_modes *) &var_mode;
283 bpp = video_get_params (res_mode, penv);
286 /* calculate hsync and vsync freq (info only) */
287 t1 = (res_mode->left_margin + res_mode->xres +
288 res_mode->right_margin + res_mode->hsync_len) / 8;
290 t1 *= res_mode->pixclock;
292 hsync = 1000000000L / t1;
293 t1 *= (res_mode->upper_margin + res_mode->yres +
294 res_mode->lower_margin + res_mode->vsync_len);
296 vsync = 1000000000L / t1;
298 /* fill in Graphic device struct */
299 sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
300 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
301 printf ("\t%s\n", dev->modeIdent);
302 dev->winSizeX = res_mode->xres;
303 dev->winSizeY = res_mode->yres;
304 dev->memSize = VIDEO_MEM_SIZE;
308 dev->gdfIndex = GDF__8BIT_INDEX;
313 dev->gdfIndex = GDF_15BIT_555RGB;
317 printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
319 puts ("\tfallback to 15bpp\n");
320 dev->gdfIndex = GDF_15BIT_555RGB;
324 /* Setup dot clock (internal pll, division rate) */
325 DISP_WR_REG (GC_DCM1, div);
327 cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
328 DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
329 (dev->winSizeY - 1) | cf);
330 DISP_WR_REG (GC_L0OA0, 0x0);
331 DISP_WR_REG (GC_L0DA0, 0x0);
332 DISP_WR_REG (GC_L0DY_L0DX, 0x0);
333 DISP_WR_REG (GC_L0EM, 0x0);
334 DISP_WR_REG (GC_L0WY_L0WX, 0x0);
335 DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
337 /* Display timing init */
338 DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
339 res_mode->left_margin +
340 res_mode->right_margin +
341 res_mode->hsync_len - 1) << 16);
342 DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
343 (dev->winSizeX - 1));
344 DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
345 (res_mode->hsync_len - 1) << 16 |
347 res_mode->right_margin - 1));
348 DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
349 res_mode->upper_margin +
350 res_mode->vsync_len - 1) << 16);
351 DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
353 res_mode->lower_margin - 1));
354 DISP_WR_REG (GC_WY_WX, 0x0);
355 DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
356 /* Display enable, L0 layer */
357 DISP_WR_REG (GC_DCM1, 0x80010000 | div);
359 return dev->frameAdrs;
364 #if !defined(CONFIG_VIDEO_CORALP)
365 int mb862xx_probe(unsigned int addr)
367 GraphicDevice *dev = &mb862xx;
370 dev->frameAdrs = addr;
371 dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
373 /* Try to access GDC ID/Revision registers */
374 reg = HOST_RD_REG (GC_CID);
375 reg = HOST_RD_REG (GC_CID);
377 reg = DE_RD_REG(GC_REV);
378 reg = DE_RD_REG(GC_REV);
379 if ((reg & ~0xff) == 0x20050100)
380 return MB862XX_TYPE_LIME;
387 void *video_hw_init (void)
389 GraphicDevice *dev = &mb862xx;
391 puts ("Video: Fujitsu ");
393 memset (dev, 0, sizeof (GraphicDevice));
395 #if defined(CONFIG_VIDEO_CORALP)
396 if (card_init () == 0)
400 * Preliminary init of the onboard graphic controller,
401 * retrieve base address
403 if ((dev->frameAdrs = board_video_init ()) == 0) {
404 puts ("Controller not found!\n");
409 /* Set Change of Clock Frequency Register */
410 HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
413 /* Set Memory I/F Mode Register) */
414 HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
420 #if !defined(CONFIG_VIDEO_CORALP)
424 #if (defined(CONFIG_LWMON5) || \
425 defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
427 board_backlight_switch (1);
434 * Set a RGB color in the LUT
436 void video_set_lut (unsigned int index, unsigned char r,
437 unsigned char g, unsigned char b)
439 GraphicDevice *dev = &mb862xx;
441 L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
444 #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
446 * Drawing engine Fill and BitBlt screen region
448 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
449 unsigned int dst_y, unsigned int dim_x,
450 unsigned int dim_y, unsigned int color)
452 GraphicDevice *dev = &mb862xx;
455 DE_WR_REG (GC_FC, color);
456 DE_WR_FIFO (0x09410000);
457 DE_WR_FIFO ((dst_y << 16) | dst_x);
458 DE_WR_FIFO ((dim_y << 16) | dim_x);
462 void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
463 unsigned int src_y, unsigned int dst_x,
464 unsigned int dst_y, unsigned int width,
467 GraphicDevice *dev = &mb862xx;
468 unsigned int ctrl = 0x0d000000L;
470 if (src_x >= dst_x && src_y >= dst_y)
472 else if (src_x >= dst_x && src_y <= dst_y)
474 else if (src_x <= dst_x && src_y >= dst_y)
481 DE_WR_FIFO ((src_y << 16) | src_x);
482 DE_WR_FIFO ((dst_y << 16) | dst_x);
483 DE_WR_FIFO ((height << 16) | width);
484 de_wait (); /* sync */