5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 * Linux IPU driver for MX51:
9 * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #ifndef __IPU_REGS_INCLUDED__
31 #define __IPU_REGS_INCLUDED__
33 #define IPU_DISP0_BASE 0x00000000
34 #define IPU_MCU_T_DEFAULT 8
35 #define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
36 #define IPU_CM_REG_BASE 0x1E000000
37 #define IPU_STAT_REG_BASE 0x1E000200
38 #define IPU_IDMAC_REG_BASE 0x1E008000
39 #define IPU_ISP_REG_BASE 0x1E010000
40 #define IPU_DP_REG_BASE 0x1E018000
41 #define IPU_IC_REG_BASE 0x1E020000
42 #define IPU_IRT_REG_BASE 0x1E028000
43 #define IPU_CSI0_REG_BASE 0x1E030000
44 #define IPU_CSI1_REG_BASE 0x1E038000
45 #define IPU_DI0_REG_BASE 0x1E040000
46 #define IPU_DI1_REG_BASE 0x1E048000
47 #define IPU_SMFC_REG_BASE 0x1E050000
48 #define IPU_DC_REG_BASE 0x1E058000
49 #define IPU_DMFC_REG_BASE 0x1E060000
50 #define IPU_CPMEM_REG_BASE 0x1F000000
51 #define IPU_LUT_REG_BASE 0x1F020000
52 #define IPU_SRM_REG_BASE 0x1F040000
53 #define IPU_TPM_REG_BASE 0x1F060000
54 #define IPU_DC_TMPL_REG_BASE 0x1F080000
55 #define IPU_ISP_TBPR_REG_BASE 0x1F0C0000
56 #define IPU_VDI_REG_BASE 0x1E068000
59 extern u32 *ipu_dc_tmpl_reg;
64 #define DC_EVT_NFIELD 3
66 #define DC_EVT_EOFIELD 5
67 #define DC_EVT_NEW_ADDR 6
68 #define DC_EVT_NEW_CHAN 7
69 #define DC_EVT_NEW_DATA 8
71 #define DC_EVT_NEW_ADDR_W_0 0
72 #define DC_EVT_NEW_ADDR_W_1 1
73 #define DC_EVT_NEW_CHAN_W_0 2
74 #define DC_EVT_NEW_CHAN_W_1 3
75 #define DC_EVT_NEW_DATA_W_0 4
76 #define DC_EVT_NEW_DATA_W_1 5
77 #define DC_EVT_NEW_ADDR_R_0 6
78 #define DC_EVT_NEW_ADDR_R_1 7
79 #define DC_EVT_NEW_CHAN_R_0 8
80 #define DC_EVT_NEW_CHAN_R_1 9
81 #define DC_EVT_NEW_DATA_R_0 10
82 #define DC_EVT_NEW_DATA_R_1 11
84 /* Software reset for ipu */
88 IPU_CONF_DP_EN = 0x00000020,
89 IPU_CONF_DI0_EN = 0x00000040,
90 IPU_CONF_DI1_EN = 0x00000080,
91 IPU_CONF_DMFC_EN = 0x00000400,
92 IPU_CONF_DC_EN = 0x00000200,
94 DI0_COUNTER_RELEASE = 0x01000000,
95 DI1_COUNTER_RELEASE = 0x02000000,
97 DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
98 DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
100 DI_GEN_DI_CLK_EXT = 0x100000,
101 DI_GEN_POLARITY_1 = 0x00000001,
102 DI_GEN_POLARITY_2 = 0x00000002,
103 DI_GEN_POLARITY_3 = 0x00000004,
104 DI_GEN_POLARITY_4 = 0x00000008,
105 DI_GEN_POLARITY_5 = 0x00000010,
106 DI_GEN_POLARITY_6 = 0x00000020,
107 DI_GEN_POLARITY_7 = 0x00000040,
108 DI_GEN_POLARITY_8 = 0x00000080,
109 DI_GEN_POL_CLK = 0x20000,
111 DI_POL_DRDY_DATA_POLARITY = 0x00000080,
112 DI_POL_DRDY_POLARITY_15 = 0x00000010,
113 DI_VSYNC_SEL_OFFSET = 13,
115 DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
116 DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
117 DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
118 DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
119 DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
120 DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
122 DP_COM_CONF_FG_EN = 0x00000001,
123 DP_COM_CONF_GWSEL = 0x00000002,
124 DP_COM_CONF_GWAM = 0x00000004,
125 DP_COM_CONF_GWCKE = 0x00000008,
126 DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
127 DP_COM_CONF_CSC_DEF_OFFSET = 8,
128 DP_COM_CONF_CSC_DEF_FG = 0x00000300,
129 DP_COM_CONF_CSC_DEF_BG = 0x00000200,
130 DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
131 DP_COM_CONF_GAMMA_EN = 0x00001000,
132 DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
152 DI_SYNC_INT_HSYNC = 1,
179 u32 ch_db_mode_sel[2];
181 u32 alt_ch_db_mode_sel[2];
183 u32 ch_trb_mode_sel[2];
201 struct ipu_com_async {
203 u32 graph_wind_ctrl_async;
207 u32 gamma_c_async[8];
208 u32 gamma_s_async[4];
209 u32 dp_csca_async[4];
215 u32 graph_wind_ctrl_sync;
224 struct ipu_com_async async[2];
255 u32 triple_cur_buf[4];
258 u32 alt_ch_buf0_rdy[2];
259 u32 alt_ch_buf1_rdy[2];
270 struct ipu_dc_ch dc_ch0_1_2[3];
273 struct ipu_dc_ch dc_ch5_6[2];
274 struct ipu_dc_ch dc_ch8;
276 struct ipu_dc_ch dc_ch9;
288 u32 wr_ch_addr_5_alt;
306 #define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
308 #define IPU_CONF (&IPU_CM_REG->conf)
309 #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
310 #define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
311 #define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
312 #define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
313 #define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
314 #define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
315 #define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
316 #define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
317 #define IPU_GPR (&IPU_CM_REG->gpr)
318 #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
320 #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
322 #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
323 #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
324 #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
326 #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
328 #define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
330 #define IDMAC_CONF (&IDMAC_REG->conf)
331 #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
332 #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
334 #define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
335 ((di == 1) ? IPU_DI1_REG_BASE : \
337 #define DI_GENERAL(di) (&DI_REG(di)->general)
338 #define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
339 #define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
341 #define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
342 #define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
343 #define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
344 #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
345 #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
346 #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
347 #define DI_POL(di) (&DI_REG(di)->pol)
348 #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
350 #define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
352 #define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
353 #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
354 #define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
355 #define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
356 #define DMFC_GENERAL1 (&DMFC_REG->general[0])
357 #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
360 #define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
362 #define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
363 #define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
366 static inline struct ipu_dc_ch *dc_ch_offset(int ch)
372 return &DC_REG->dc_ch0_1_2[ch];
375 return &DC_REG->dc_ch5_6[ch - 5];
377 return &DC_REG->dc_ch8;
379 return &DC_REG->dc_ch9;
381 printf("%s: invalid channel %d\n", __func__, ch);
387 #define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
389 #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
390 #define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
392 #define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
393 #define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
395 #define DC_GEN (&DC_REG->gen)
396 #define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
397 #define DC_STAT (&DC_REG->stat)
400 #define DP_ASYNC0 0x60
401 #define DP_ASYNC1 0xBC
403 #define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
405 #define DP_COM_CONF(flow) (&DP_REG->com_conf_sync)
406 #define DP_GRAPH_WIND_CTRL(flow) (&DP_REG->graph_wind_ctrl_sync)
407 #define DP_CSC_A_0(flow) (&DP_REG->csca_sync[0])
408 #define DP_CSC_A_1(flow) (&DP_REG->csca_sync[1])
409 #define DP_CSC_A_2(flow) (&DP_REG->csca_sync[2])
410 #define DP_CSC_A_3(flow) (&DP_REG->csca_sync[3])
412 #define DP_CSC_0(flow) (&DP_REG->csc_sync[0])
413 #define DP_CSC_1(flow) (&DP_REG->csc_sync[1])
415 /* DC template opcodes */
416 #define WROD(lf) (0x18 | (lf << 1))